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79964ac8 1/** @file\r
2 This protocol abstracts the 8259 interrupt controller. This includes\r
3 PCI IRQ routing need to program the PCI Interrupt Line register.\r
4\r
5 Copyright (c) 2007, Intel Corporation\r
6 All rights reserved. This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14 Module Name: Legacy8259.h\r
15\r
16 @par Revision Reference:\r
17 This protocol is defined in Framework for EFI Compatibility Support Module spec\r
18 Version 0.96\r
19\r
20**/\r
21\r
22#ifndef _EFI_LEGACY_8259_H_\r
23#define _EFI_LEGACY_8259_H_\r
24\r
b80fbe85 25#include <PiDxe.h>\r
26\r
79964ac8 27#define EFI_LEGACY_8259_PROTOCOL_GUID \\r
28 { \\r
29 0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 } \\r
30 }\r
31\r
32typedef struct _EFI_LEGACY_8259_PROTOCOL EFI_LEGACY_8259_PROTOCOL;\r
33\r
34typedef enum {\r
35 Efi8259Irq0,\r
36 Efi8259Irq1,\r
37 Efi8259Irq2,\r
38 Efi8259Irq3,\r
39 Efi8259Irq4,\r
40 Efi8259Irq5,\r
41 Efi8259Irq6,\r
42 Efi8259Irq7,\r
43 Efi8259Irq8,\r
44 Efi8259Irq9,\r
45 Efi8259Irq10,\r
46 Efi8259Irq11,\r
47 Efi8259Irq12,\r
48 Efi8259Irq13,\r
49 Efi8259Irq14,\r
50 Efi8259Irq15,\r
51 Efi8259IrqMax\r
52} EFI_8259_IRQ;\r
53\r
54typedef enum {\r
55 Efi8259LegacyMode,\r
56 Efi8259ProtectedMode,\r
57 Efi8259MaxMode\r
58} EFI_8259_MODE;\r
59\r
60/**\r
61 Get the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for\r
62 the legacy mode mask and the protected mode mask. The base address for the 8259\r
63 is different for legacy and protected mode, so two masks are required.\r
64\r
65 @param This Protocol instance pointer.\r
66 @param MasterBase The base vector for the Master PIC in the 8259 controller\r
67 @param Slavebase The base vector for the Master PIC in the 8259 controller\r
68\r
69 @retval EFI_SUCCESS The new bases were programmed\r
70 @retval EFI_DEVICE_ERROR A device erro occured programming the vector bases\r
71\r
72**/\r
73typedef\r
74EFI_STATUS\r
75(EFIAPI *EFI_LEGACY_8259_SET_VECTOR_BASE) (\r
76 IN EFI_LEGACY_8259_PROTOCOL *This,\r
77 IN UINT8 MasterBase,\r
78 IN UINT8 SlaveBase\r
79 );\r
80\r
81/**\r
82 Get the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for\r
83 the legacy mode mask and the protected mode mask. The base address for the 8259\r
84 is different for legacy and protected mode, so two masks are required.\r
85\r
86 @param This Protocol instance pointer.\r
87 @param LegacyMask Bit 0 is Irq0 - Bit 15 is Irq15\r
88 @param LegacyEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
89 @param ProtectedMask Bit 0 is Irq0 - Bit 15 is Irq15\r
90 @param ProtectedEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
91\r
92 @retval EFI_SUCCESS 8259 status returned\r
93 @retval EFI_DEVICE_ERROR Error reading 8259\r
94\r
95**/\r
96typedef\r
97EFI_STATUS\r
98(EFIAPI *EFI_LEGACY_8259_GET_MASK) (\r
99 IN EFI_LEGACY_8259_PROTOCOL *This,\r
100 OUT UINT16 *LegacyMask, OPTIONAL\r
101 OUT UINT16 *LegacyEdgeLevel, OPTIONAL\r
102 OUT UINT16 *ProtectedMask, OPTIONAL\r
103 OUT UINT16 *ProtectedEdgeLevel OPTIONAL\r
104 );\r
105\r
106/**\r
107 Set the 8259 interrupt masks for Irq0 - Irq15. A different mask exists for\r
108 the legacy mode mask and the protected mode mask. The base address for the 8259\r
109 is different for legacy and protected mode, so two masks are required.\r
110 Also set the edge/level masks.\r
111\r
112 @param This Protocol instance pointer.\r
113 @param LegacyMask Bit 0 is Irq0 - Bit 15 is Irq15\r
114 @param LegacyEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
115 @param ProtectedMask Bit 0 is Irq0 - Bit 15 is Irq15\r
116 @param ProtectedEdgeLevel Bit 0 is Irq0 - Bit 15 is Irq15\r
117\r
118 @retval EFI_SUCCESS 8259 status returned\r
119 @retval EFI_DEVICE_ERROR Error reading 8259\r
120\r
121**/\r
122typedef\r
123EFI_STATUS\r
124(EFIAPI *EFI_LEGACY_8259_SET_MASK) (\r
125 IN EFI_LEGACY_8259_PROTOCOL *This,\r
126 IN UINT16 *LegacyMask, OPTIONAL\r
127 IN UINT16 *LegacyEdgeLevel, OPTIONAL\r
128 IN UINT16 *ProtectedMask, OPTIONAL\r
129 IN UINT16 *ProtectedEdgeLevel OPTIONAL\r
130 );\r
131\r
132/**\r
133 Set the 8259 mode of operation. The base address for the 8259 is different for\r
134 legacy and protected mode. The legacy mode requires the master 8259 to have a\r
135 master base of 0x08 and the slave base of 0x70. The protected mode base locations\r
136 are not defined. Interrupts must be masked by the caller before this function\r
137 is called. The interrupt mask from the current mode is saved. The interrupt\r
138 mask for the new mode is Mask, or if Mask does not exist the previously saved\r
139 mask is used.\r
140\r
141 @param This Protocol instance pointer.\r
142 @param Mode Mode of operation. i.e. real mode or protected mode\r
143 @param Mask Optional interupt mask for the new mode.\r
144 @param EdgeLevel Optional trigger mask for the new mode.\r
145\r
146 @retval EFI_SUCCESS 8259 programmed\r
147 @retval EFI_DEVICE_ERROR Error writting to 8259\r
148\r
149**/\r
150typedef\r
151EFI_STATUS\r
152(EFIAPI *EFI_LEGACY_8259_SET_MODE) (\r
153 IN EFI_LEGACY_8259_PROTOCOL *This,\r
154 IN EFI_8259_MODE Mode,\r
155 IN UINT16 *Mask, OPTIONAL\r
156 IN UINT16 *EdgeLevel OPTIONAL\r
157 );\r
158\r
159/**\r
160 Convert from IRQ to processor interrupt vector number.\r
161\r
162 @param This Protocol instance pointer.\r
163 @param Irq 8259 IRQ0 - IRQ15\r
164 @param Vector Processor vector number that matches Irq\r
165\r
166 @retval EFI_SUCCESS The Vector matching Irq is returned\r
167 @retval EFI_INVALID_PARAMETER Irq not valid\r
168\r
169**/\r
170typedef\r
171EFI_STATUS\r
172(EFIAPI *EFI_LEGACY_8259_GET_VECTOR) (\r
173 IN EFI_LEGACY_8259_PROTOCOL *This,\r
174 IN EFI_8259_IRQ Irq,\r
175 OUT UINT8 *Vector\r
176 );\r
177\r
178/**\r
179 Enable Irq by unmasking interrupt in 8259\r
180\r
181 @param This Protocol instance pointer.\r
182 @param Irq 8259 IRQ0 - IRQ15\r
183 @param LevelTriggered TRUE if level triggered. FALSE if edge triggered.\r
184\r
185 @retval EFI_SUCCESS Irq enabled on 8259\r
186 @retval EFI_INVALID_PARAMETER Irq not valid\r
187\r
188**/\r
189typedef\r
190EFI_STATUS\r
191(EFIAPI *EFI_LEGACY_8259_ENABLE_IRQ) (\r
192 IN EFI_LEGACY_8259_PROTOCOL *This,\r
193 IN EFI_8259_IRQ Irq,\r
194 IN BOOLEAN LevelTriggered\r
195 );\r
196\r
197/**\r
198 Disable Irq by masking interrupt in 8259\r
199\r
200 @param This Protocol instance pointer.\r
201 @param Irq 8259 IRQ0 - IRQ15\r
202\r
203 @retval EFI_SUCCESS Irq disabled on 8259\r
204 @retval EFI_INVALID_PARAMETER Irq not valid\r
205\r
206**/\r
207typedef\r
208EFI_STATUS\r
209(EFIAPI *EFI_LEGACY_8259_DISABLE_IRQ) (\r
210 IN EFI_LEGACY_8259_PROTOCOL *This,\r
211 IN EFI_8259_IRQ Irq\r
212 );\r
213\r
214/**\r
215 PciHandle represents a PCI config space of a PCI function. Vector\r
216 represents Interrupt Pin (from PCI config space) and it is the data\r
217 that is programmed into the Interrupt Line (from the PCI config space)\r
218 register.\r
219\r
220 @param This Protocol instance pointer.\r
221 @param PciHandle PCI function to return vector for\r
222 @param Vector Vector for fucntion that matches\r
223\r
224 @retval EFI_SUCCESS A valid Vector is returned\r
225 @retval EFI_INVALID_PARAMETER PciHandle not valid\r
226\r
227**/\r
228typedef\r
229EFI_STATUS\r
230(EFIAPI *EFI_LEGACY_8259_GET_INTERRUPT_LINE) (\r
231 IN EFI_LEGACY_8259_PROTOCOL *This,\r
232 IN EFI_HANDLE PciHandle,\r
233 OUT UINT8 *Vector\r
234 );\r
235\r
236/**\r
237 Send an EOI to 8259\r
238\r
239 @param This Protocol instance pointer.\r
240 @param Irq 8259 IRQ0 - IRQ15\r
241\r
242 @retval EFI_SUCCESS EOI successfully sent to 8259\r
243 @retval EFI_INVALID_PARAMETER Irq not valid\r
244\r
245**/\r
246typedef\r
247EFI_STATUS\r
248(EFIAPI *EFI_LEGACY_8259_END_OF_INTERRUPT) (\r
249 IN EFI_LEGACY_8259_PROTOCOL *This,\r
250 IN EFI_8259_IRQ Irq\r
251 );\r
252\r
253/**\r
254 @par Protocol Description:\r
255 Abstracts the 8259 and APIC hardware control between EFI usage and\r
256 Compatibility16 usage.\r
257\r
258 @param SetVectorBase\r
259 Sets the vector bases for master and slave PICs.\r
260\r
261 @param GetMask\r
262 Gets IRQ and edge/level masks for 16-bit real mode and 32-bit protected mode.\r
263\r
264 @param SetMask\r
265 Sets the IRQ and edge\level masks for 16-bit real mode and 32-bit protected mode.\r
266\r
267 @param SetMode\r
268 Sets PIC mode to 16-bit real mode or 32-bit protected mode.\r
269\r
270 @param GetVector\r
271 Gets the base vector assigned to an IRQ.\r
272\r
273 @param EnableIrq\r
274 Enables an IRQ.\r
275\r
276 @param DisableIrq\r
277 Disables an IRQ.\r
278\r
279 @param GetInterruptLine\r
280 Gets an IRQ that is assigned to a PCI device.\r
281\r
282 @param EndOfInterrupt\r
283 Issues the end of interrupt command.\r
284\r
285**/\r
286struct _EFI_LEGACY_8259_PROTOCOL {\r
287 EFI_LEGACY_8259_SET_VECTOR_BASE SetVectorBase;\r
288 EFI_LEGACY_8259_GET_MASK GetMask;\r
289 EFI_LEGACY_8259_SET_MASK SetMask;\r
290 EFI_LEGACY_8259_SET_MODE SetMode;\r
291 EFI_LEGACY_8259_GET_VECTOR GetVector;\r
292 EFI_LEGACY_8259_ENABLE_IRQ EnableIrq;\r
293 EFI_LEGACY_8259_DISABLE_IRQ DisableIrq;\r
294 EFI_LEGACY_8259_GET_INTERRUPT_LINE GetInterruptLine;\r
295 EFI_LEGACY_8259_END_OF_INTERRUPT EndOfInterrupt;\r
296};\r
297\r
298extern EFI_GUID gEfiLegacy8259ProtocolGuid;\r
299\r
300#endif\r