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79964ac8 | 1 | /** @file\r |
2 | I/O Library.\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | Module Name: IoLib.c\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "DxeCpuIoLibInternal.h"\r | |
18 | \r | |
19 | //\r | |
20 | // Globle varible to cache pointer to CpuIo protocol.\r | |
21 | //\r | |
22 | STATIC EFI_CPU_IO_PROTOCOL *mCpuIo = NULL;\r | |
23 | STATIC EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r | |
24 | \r | |
25 | /**\r | |
26 | The constructor function caches the pointer to CpuIo protocol.\r | |
27 | \r | |
28 | The constructor function locates CpuIo protocol from protocol database.\r | |
29 | It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.\r | |
30 | \r | |
31 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
32 | @param SystemTable A pointer to the EFI System Table.\r | |
33 | \r | |
34 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r | |
35 | \r | |
36 | **/\r | |
37 | EFI_STATUS\r | |
38 | EFIAPI\r | |
39 | IoLibConstructor (\r | |
40 | IN EFI_HANDLE ImageHandle,\r | |
41 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
42 | )\r | |
43 | {\r | |
44 | EFI_STATUS Status;\r | |
45 | \r | |
46 | Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, &mPciRootBridgeIo);\r | |
47 | if (EFI_ERROR (Status)) {\r | |
48 | Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, &mCpuIo);\r | |
49 | }\r | |
50 | ASSERT_EFI_ERROR (Status);\r | |
51 | \r | |
52 | return Status;\r | |
53 | }\r | |
54 | \r | |
55 | /**\r | |
56 | Reads registers in the EFI CPU I/O space.\r | |
57 | \r | |
58 | Reads the I/O port specified by Port with registers width specified by Width.\r | |
59 | The read value is returned. If such operations are not supported, then ASSERT().\r | |
60 | This function must guarantee that all I/O read and write operations are serialized.\r | |
61 | \r | |
62 | @param Port The base address of the I/O operation.\r | |
63 | The caller is responsible for aligning the Address if required.\r | |
64 | @param Width The width of the I/O operation.\r | |
65 | \r | |
66 | @return Data read from registers in the EFI CPU I/O space.\r | |
67 | \r | |
68 | **/\r | |
69 | UINT64\r | |
70 | EFIAPI\r | |
71 | IoReadWorker (\r | |
72 | IN UINTN Port,\r | |
73 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r | |
74 | )\r | |
75 | {\r | |
76 | EFI_STATUS Status;\r | |
77 | UINT64 Data;\r | |
78 | \r | |
79 | if (mPciRootBridgeIo != NULL) {\r | |
80 | Status = mPciRootBridgeIo->Io.Read (mPciRootBridgeIo, Width, Port, 1, &Data);\r | |
81 | } else {\r | |
82 | Status = mCpuIo->Io.Read (mCpuIo, Width, Port, 1, &Data);\r | |
83 | }\r | |
84 | ASSERT_EFI_ERROR (Status);\r | |
85 | \r | |
86 | return Data;\r | |
87 | }\r | |
88 | \r | |
89 | /**\r | |
90 | Writes registers in the EFI CPU I/O space.\r | |
91 | \r | |
92 | Writes the I/O port specified by Port with registers width and value specified by Width\r | |
93 | and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r | |
94 | This function must guarantee that all I/O read and write operations are serialized.\r | |
95 | \r | |
96 | @param Port The base address of the I/O operation.\r | |
97 | The caller is responsible for aligning the Address if required.\r | |
98 | @param Width The width of the I/O operation.\r | |
99 | @param Data The value to write to the I/O port.\r | |
100 | \r | |
101 | @return The paramter of Data.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT64\r | |
105 | EFIAPI\r | |
106 | IoWriteWorker (\r | |
107 | IN UINTN Port,\r | |
108 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
109 | IN UINT64 Data\r | |
110 | )\r | |
111 | {\r | |
112 | EFI_STATUS Status;\r | |
113 | \r | |
114 | if (mPciRootBridgeIo != NULL) {\r | |
115 | Status = mPciRootBridgeIo->Io.Write (mPciRootBridgeIo, Width, Port, 1, &Data);\r | |
116 | } else {\r | |
117 | Status = mCpuIo->Io.Write (mCpuIo, Width, Port, 1, &Data);\r | |
118 | }\r | |
119 | ASSERT_EFI_ERROR (Status);\r | |
120 | \r | |
121 | return Data;\r | |
122 | }\r | |
123 | \r | |
124 | /**\r | |
125 | Reads memory-mapped registers in the EFI system memory space.\r | |
126 | \r | |
127 | Reads the MMIO registers specified by Address with registers width specified by Width.\r | |
128 | The read value is returned. If such operations are not supported, then ASSERT().\r | |
129 | This function must guarantee that all MMIO read and write operations are serialized.\r | |
130 | \r | |
131 | @param Address The MMIO register to read.\r | |
132 | The caller is responsible for aligning the Address if required.\r | |
133 | @param Width The width of the I/O operation.\r | |
134 | \r | |
135 | @return Data read from registers in the EFI system memory space.\r | |
136 | \r | |
137 | **/\r | |
138 | UINT64\r | |
139 | EFIAPI\r | |
140 | MmioReadWorker (\r | |
141 | IN UINTN Address,\r | |
142 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r | |
143 | )\r | |
144 | {\r | |
145 | EFI_STATUS Status;\r | |
146 | UINT64 Data;\r | |
147 | \r | |
148 | if (mPciRootBridgeIo != NULL) {\r | |
53f93f7e | 149 | Status = mPciRootBridgeIo->Mem.Read (mPciRootBridgeIo, Width, Address, 1, &Data);\r |
79964ac8 | 150 | } else {\r |
151 | Status = mCpuIo->Mem.Read (mCpuIo, Width, Address, 1, &Data);\r | |
152 | }\r | |
153 | ASSERT_EFI_ERROR (Status);\r | |
154 | \r | |
155 | return Data;\r | |
156 | }\r | |
157 | \r | |
158 | /**\r | |
159 | Writes memory-mapped registers in the EFI system memory space.\r | |
160 | \r | |
161 | Writes the MMIO registers specified by Address with registers width and value specified by Width\r | |
162 | and Data respectively. Data is returned. If such operations are not supported, then ASSERT().\r | |
163 | This function must guarantee that all MMIO read and write operations are serialized.\r | |
164 | \r | |
165 | @param Address The MMIO register to read.\r | |
166 | The caller is responsible for aligning the Address if required.\r | |
167 | @param Width The width of the I/O operation.\r | |
168 | \r | |
169 | @return Data read from registers in the EFI system memory space.\r | |
170 | \r | |
171 | **/\r | |
172 | UINT64\r | |
173 | EFIAPI\r | |
174 | MmioWriteWorker (\r | |
175 | IN UINTN Address,\r | |
176 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
177 | IN UINT64 Data\r | |
178 | )\r | |
179 | {\r | |
180 | EFI_STATUS Status;\r | |
181 | \r | |
182 | if (mPciRootBridgeIo != NULL) {\r | |
183 | Status = mPciRootBridgeIo->Mem.Write (mPciRootBridgeIo, Width, Address, 1, &Data);\r | |
184 | } else {\r | |
185 | Status = mCpuIo->Mem.Write (mCpuIo, Width, Address, 1, &Data);\r | |
186 | }\r | |
187 | ASSERT_EFI_ERROR (Status);\r | |
188 | \r | |
189 | return Data;\r | |
190 | }\r | |
191 | \r | |
192 | /**\r | |
193 | Reads an 8-bit I/O port.\r | |
194 | \r | |
195 | Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r | |
196 | This function must guarantee that all I/O read and write operations are\r | |
197 | serialized.\r | |
198 | \r | |
199 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
200 | \r | |
201 | @param Port The I/O port to read.\r | |
202 | \r | |
203 | @return The value read.\r | |
204 | \r | |
205 | **/\r | |
206 | UINT8\r | |
207 | EFIAPI\r | |
208 | IoRead8 (\r | |
209 | IN UINTN Port\r | |
210 | )\r | |
211 | {\r | |
212 | return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r | |
213 | }\r | |
214 | \r | |
215 | /**\r | |
216 | Writes an 8-bit I/O port.\r | |
217 | \r | |
218 | Writes the 8-bit I/O port specified by Port with the value specified by Value\r | |
219 | and returns Value. This function must guarantee that all I/O read and write\r | |
220 | operations are serialized.\r | |
221 | \r | |
222 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
223 | \r | |
224 | @param Port The I/O port to write.\r | |
225 | @param Value The value to write to the I/O port.\r | |
226 | \r | |
227 | @return The value written the I/O port.\r | |
228 | \r | |
229 | **/\r | |
230 | UINT8\r | |
231 | EFIAPI\r | |
232 | IoWrite8 (\r | |
233 | IN UINTN Port,\r | |
234 | IN UINT8 Value\r | |
235 | )\r | |
236 | {\r | |
237 | return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r | |
238 | }\r | |
239 | \r | |
240 | /**\r | |
241 | Reads a 16-bit I/O port.\r | |
242 | \r | |
243 | Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r | |
244 | This function must guarantee that all I/O read and write operations are\r | |
245 | serialized.\r | |
246 | \r | |
247 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
248 | \r | |
249 | @param Port The I/O port to read.\r | |
250 | \r | |
251 | @return The value read.\r | |
252 | \r | |
253 | **/\r | |
254 | UINT16\r | |
255 | EFIAPI\r | |
256 | IoRead16 (\r | |
257 | IN UINTN Port\r | |
258 | )\r | |
259 | {\r | |
260 | //\r | |
261 | // Make sure Port is aligned on a 16-bit boundary.\r | |
262 | //\r | |
263 | ASSERT ((Port & 1) == 0);\r | |
264 | return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);\r | |
265 | }\r | |
266 | \r | |
267 | /**\r | |
268 | Writes a 16-bit I/O port.\r | |
269 | \r | |
270 | Writes the 16-bit I/O port specified by Port with the value specified by Value\r | |
271 | and returns Value. This function must guarantee that all I/O read and write\r | |
272 | operations are serialized.\r | |
273 | \r | |
274 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
275 | \r | |
276 | @param Port The I/O port to write.\r | |
277 | @param Value The value to write to the I/O port.\r | |
278 | \r | |
279 | @return The value written the I/O port.\r | |
280 | \r | |
281 | **/\r | |
282 | UINT16\r | |
283 | EFIAPI\r | |
284 | IoWrite16 (\r | |
285 | IN UINTN Port,\r | |
286 | IN UINT16 Value\r | |
287 | )\r | |
288 | {\r | |
289 | //\r | |
290 | // Make sure Port is aligned on a 16-bit boundary.\r | |
291 | //\r | |
292 | ASSERT ((Port & 1) == 0);\r | |
293 | return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);\r | |
294 | }\r | |
295 | \r | |
296 | /**\r | |
297 | Reads a 32-bit I/O port.\r | |
298 | \r | |
299 | Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r | |
300 | This function must guarantee that all I/O read and write operations are\r | |
301 | serialized.\r | |
302 | \r | |
303 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
304 | \r | |
305 | @param Port The I/O port to read.\r | |
306 | \r | |
307 | @return The value read.\r | |
308 | \r | |
309 | **/\r | |
310 | UINT32\r | |
311 | EFIAPI\r | |
312 | IoRead32 (\r | |
313 | IN UINTN Port\r | |
314 | )\r | |
315 | {\r | |
316 | //\r | |
317 | // Make sure Port is aligned on a 32-bit boundary.\r | |
318 | //\r | |
319 | ASSERT ((Port & 3) == 0);\r | |
320 | return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);\r | |
321 | }\r | |
322 | \r | |
323 | /**\r | |
324 | Writes a 32-bit I/O port.\r | |
325 | \r | |
326 | Writes the 32-bit I/O port specified by Port with the value specified by Value\r | |
327 | and returns Value. This function must guarantee that all I/O read and write\r | |
328 | operations are serialized.\r | |
329 | \r | |
330 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
331 | \r | |
332 | @param Port The I/O port to write.\r | |
333 | @param Value The value to write to the I/O port.\r | |
334 | \r | |
335 | @return The value written the I/O port.\r | |
336 | \r | |
337 | **/\r | |
338 | UINT32\r | |
339 | EFIAPI\r | |
340 | IoWrite32 (\r | |
341 | IN UINTN Port,\r | |
342 | IN UINT32 Value\r | |
343 | )\r | |
344 | {\r | |
345 | //\r | |
346 | // Make sure Port is aligned on a 32-bit boundary.\r | |
347 | //\r | |
348 | ASSERT ((Port & 3) == 0);\r | |
349 | return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);\r | |
350 | }\r | |
351 | \r | |
352 | /**\r | |
353 | Reads a 64-bit I/O port.\r | |
354 | \r | |
355 | Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r | |
356 | This function must guarantee that all I/O read and write operations are\r | |
357 | serialized.\r | |
358 | \r | |
359 | If 64-bit I/O port operations are not supported, then ASSERT().\r | |
360 | \r | |
361 | @param Port The I/O port to read.\r | |
362 | \r | |
363 | @return The value read.\r | |
364 | \r | |
365 | **/\r | |
366 | UINT64\r | |
367 | EFIAPI\r | |
368 | IoRead64 (\r | |
369 | IN UINTN Port\r | |
370 | )\r | |
371 | {\r | |
372 | //\r | |
373 | // Make sure Port is aligned on a 64-bit boundary.\r | |
374 | //\r | |
375 | ASSERT ((Port & 7) == 0);\r | |
376 | return IoReadWorker (Port, EfiCpuIoWidthUint64);\r | |
377 | }\r | |
378 | \r | |
379 | /**\r | |
380 | Writes a 64-bit I/O port.\r | |
381 | \r | |
382 | Writes the 64-bit I/O port specified by Port with the value specified by Value\r | |
383 | and returns Value. This function must guarantee that all I/O read and write\r | |
384 | operations are serialized.\r | |
385 | \r | |
386 | If 64-bit I/O port operations are not supported, then ASSERT().\r | |
387 | \r | |
388 | @param Port The I/O port to write.\r | |
389 | @param Value The value to write to the I/O port.\r | |
390 | \r | |
391 | @return The value written the I/O port.\r | |
392 | \r | |
393 | **/\r | |
394 | UINT64\r | |
395 | EFIAPI\r | |
396 | IoWrite64 (\r | |
397 | IN UINTN Port,\r | |
398 | IN UINT64 Value\r | |
399 | )\r | |
400 | {\r | |
401 | //\r | |
402 | // Make sure Port is aligned on a 64-bit boundary.\r | |
403 | //\r | |
404 | ASSERT ((Port & 7) == 0);\r | |
405 | return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);\r | |
406 | }\r | |
407 | \r | |
408 | /**\r | |
409 | Reads an 8-bit MMIO register.\r | |
410 | \r | |
411 | Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r | |
412 | returned. This function must guarantee that all MMIO read and write\r | |
413 | operations are serialized.\r | |
414 | \r | |
415 | If 8-bit MMIO register operations are not supported, then ASSERT().\r | |
416 | \r | |
417 | @param Address The MMIO register to read.\r | |
418 | \r | |
419 | @return The value read.\r | |
420 | \r | |
421 | **/\r | |
422 | UINT8\r | |
423 | EFIAPI\r | |
424 | MmioRead8 (\r | |
425 | IN UINTN Address\r | |
426 | )\r | |
427 | {\r | |
428 | return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r | |
429 | }\r | |
430 | \r | |
431 | /**\r | |
432 | Writes an 8-bit MMIO register.\r | |
433 | \r | |
434 | Writes the 8-bit MMIO register specified by Address with the value specified\r | |
435 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
436 | and write operations are serialized.\r | |
437 | \r | |
438 | If 8-bit MMIO register operations are not supported, then ASSERT().\r | |
439 | \r | |
440 | @param Address The MMIO register to write.\r | |
441 | @param Value The value to write to the MMIO register.\r | |
442 | \r | |
443 | **/\r | |
444 | UINT8\r | |
445 | EFIAPI\r | |
446 | MmioWrite8 (\r | |
447 | IN UINTN Address,\r | |
448 | IN UINT8 Value\r | |
449 | )\r | |
450 | {\r | |
451 | return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r | |
452 | }\r | |
453 | \r | |
454 | /**\r | |
455 | Reads a 16-bit MMIO register.\r | |
456 | \r | |
457 | Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r | |
458 | returned. This function must guarantee that all MMIO read and write\r | |
459 | operations are serialized.\r | |
460 | \r | |
461 | If 16-bit MMIO register operations are not supported, then ASSERT().\r | |
462 | \r | |
463 | @param Address The MMIO register to read.\r | |
464 | \r | |
465 | @return The value read.\r | |
466 | \r | |
467 | **/\r | |
468 | UINT16\r | |
469 | EFIAPI\r | |
470 | MmioRead16 (\r | |
471 | IN UINTN Address\r | |
472 | )\r | |
473 | {\r | |
474 | //\r | |
475 | // Make sure Address is aligned on a 16-bit boundary.\r | |
476 | //\r | |
477 | ASSERT ((Address & 1) == 0);\r | |
478 | return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);\r | |
479 | }\r | |
480 | \r | |
481 | /**\r | |
482 | Writes a 16-bit MMIO register.\r | |
483 | \r | |
484 | Writes the 16-bit MMIO register specified by Address with the value specified\r | |
485 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
486 | and write operations are serialized.\r | |
487 | \r | |
488 | If 16-bit MMIO register operations are not supported, then ASSERT().\r | |
489 | \r | |
490 | @param Address The MMIO register to write.\r | |
491 | @param Value The value to write to the MMIO register.\r | |
492 | \r | |
493 | **/\r | |
494 | UINT16\r | |
495 | EFIAPI\r | |
496 | MmioWrite16 (\r | |
497 | IN UINTN Address,\r | |
498 | IN UINT16 Value\r | |
499 | )\r | |
500 | {\r | |
501 | //\r | |
502 | // Make sure Address is aligned on a 16-bit boundary.\r | |
503 | //\r | |
504 | ASSERT ((Address & 1) == 0);\r | |
505 | return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);\r | |
506 | }\r | |
507 | \r | |
508 | /**\r | |
509 | Reads a 32-bit MMIO register.\r | |
510 | \r | |
511 | Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r | |
512 | returned. This function must guarantee that all MMIO read and write\r | |
513 | operations are serialized.\r | |
514 | \r | |
515 | If 32-bit MMIO register operations are not supported, then ASSERT().\r | |
516 | \r | |
517 | @param Address The MMIO register to read.\r | |
518 | \r | |
519 | @return The value read.\r | |
520 | \r | |
521 | **/\r | |
522 | UINT32\r | |
523 | EFIAPI\r | |
524 | MmioRead32 (\r | |
525 | IN UINTN Address\r | |
526 | )\r | |
527 | {\r | |
528 | //\r | |
529 | // Make sure Address is aligned on a 32-bit boundary.\r | |
530 | //\r | |
531 | ASSERT ((Address & 3) == 0);\r | |
532 | return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);\r | |
533 | }\r | |
534 | \r | |
535 | /**\r | |
536 | Writes a 32-bit MMIO register.\r | |
537 | \r | |
538 | Writes the 32-bit MMIO register specified by Address with the value specified\r | |
539 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
540 | and write operations are serialized.\r | |
541 | \r | |
542 | If 32-bit MMIO register operations are not supported, then ASSERT().\r | |
543 | \r | |
544 | @param Address The MMIO register to write.\r | |
545 | @param Value The value to write to the MMIO register.\r | |
546 | \r | |
547 | **/\r | |
548 | UINT32\r | |
549 | EFIAPI\r | |
550 | MmioWrite32 (\r | |
551 | IN UINTN Address,\r | |
552 | IN UINT32 Value\r | |
553 | )\r | |
554 | {\r | |
555 | //\r | |
556 | // Make sure Address is aligned on a 32-bit boundary.\r | |
557 | //\r | |
558 | ASSERT ((Address & 3) == 0);\r | |
559 | return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);\r | |
560 | }\r | |
561 | \r | |
562 | /**\r | |
563 | Reads a 64-bit MMIO register.\r | |
564 | \r | |
565 | Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r | |
566 | returned. This function must guarantee that all MMIO read and write\r | |
567 | operations are serialized.\r | |
568 | \r | |
569 | If 64-bit MMIO register operations are not supported, then ASSERT().\r | |
570 | \r | |
571 | @param Address The MMIO register to read.\r | |
572 | \r | |
573 | @return The value read.\r | |
574 | \r | |
575 | **/\r | |
576 | UINT64\r | |
577 | EFIAPI\r | |
578 | MmioRead64 (\r | |
579 | IN UINTN Address\r | |
580 | )\r | |
581 | {\r | |
582 | //\r | |
583 | // Make sure Address is aligned on a 64-bit boundary.\r | |
584 | //\r | |
585 | ASSERT ((Address & 7) == 0);\r | |
586 | return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);\r | |
587 | }\r | |
588 | \r | |
589 | /**\r | |
590 | Writes a 64-bit MMIO register.\r | |
591 | \r | |
592 | Writes the 64-bit MMIO register specified by Address with the value specified\r | |
593 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
594 | and write operations are serialized.\r | |
595 | \r | |
596 | If 64-bit MMIO register operations are not supported, then ASSERT().\r | |
597 | \r | |
598 | @param Address The MMIO register to write.\r | |
599 | @param Value The value to write to the MMIO register.\r | |
600 | \r | |
601 | **/\r | |
602 | UINT64\r | |
603 | EFIAPI\r | |
604 | MmioWrite64 (\r | |
605 | IN UINTN Address,\r | |
606 | IN UINT64 Value\r | |
607 | )\r | |
608 | {\r | |
609 | //\r | |
610 | // Make sure Address is aligned on a 64-bit boundary.\r | |
611 | //\r | |
612 | ASSERT ((Address & 7) == 0);\r | |
613 | return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);\r | |
614 | }\r |