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1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r | |
4 | ; This program and the accompanying materials\r | |
5 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
6 | ; which accompanies this distribution. The full text of the license may be found at\r | |
7 | ; http://opensource.org/licenses/bsd-license.php.\r | |
8 | ;\r | |
9 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | ;\r | |
12 | ; Abstract:\r | |
13 | ;\r | |
14 | ;------------------------------------------------------------------------------\r | |
15 | \r | |
16 | \r | |
17 | SECTION .data\r | |
18 | ;\r | |
19 | ; Float control word initial value:\r | |
20 | ; all exceptions masked, double-precision, round-to-nearest\r | |
21 | ;\r | |
22 | ASM_PFX(mFpuControlWord):\r | |
23 | dw 0x027F\r | |
24 | ;\r | |
25 | ; Multimedia-extensions control word:\r | |
26 | ; all exceptions masked, round-to-nearest, flush to zero for masked underflow\r | |
27 | ;\r | |
28 | ASM_PFX(mMmxControlWord):\r | |
29 | dd 0x01F80\r | |
30 | \r | |
31 | SECTION .text\r | |
32 | \r | |
33 | ;\r | |
34 | ; Initializes floating point units for requirement of UEFI specification.\r | |
35 | ;\r | |
36 | ; This function initializes floating-point control word to 0x027F (all exceptions\r | |
37 | ; masked,double-precision, round-to-nearest) and multimedia-extensions control word\r | |
38 | ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero\r | |
39 | ; for masked underflow).\r | |
40 | ;\r | |
41 | \r | |
42 | global ASM_PFX(InitializeFloatingPointUnits)\r | |
43 | ASM_PFX(InitializeFloatingPointUnits):\r | |
44 | \r | |
45 | \r | |
46 | push ebx\r | |
47 | \r | |
48 | ;\r | |
49 | ; Initialize floating point units\r | |
50 | ;\r | |
51 | finit\r | |
52 | fldcw [ASM_PFX(mFpuControlWord)]\r | |
53 | \r | |
54 | ;\r | |
55 | ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r | |
56 | ; whether the processor supports SSE instruction.\r | |
57 | ;\r | |
58 | mov eax, 1\r | |
59 | cpuid\r | |
60 | bt edx, 25\r | |
61 | jnc Done\r | |
62 | \r | |
63 | ;\r | |
64 | ; Set OSFXSR bit 9 in CR4\r | |
65 | ;\r | |
66 | mov eax, cr4\r | |
67 | or eax, BIT9\r | |
68 | mov cr4, eax\r | |
69 | \r | |
70 | ;\r | |
71 | ; The processor should support SSE instruction and we can use\r | |
72 | ; ldmxcsr instruction\r | |
73 | ;\r | |
74 | ldmxcsr [ASM_PFX(mMmxControlWord)]\r | |
75 | Done:\r | |
76 | pop ebx\r | |
77 | \r | |
78 | ret\r |