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a33a2f62 JY |
1 | /** @file\r |
2 | Sample to provide FSP platform information related function.\r | |
3 | \r | |
4 | Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r | |
19486360 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a33a2f62 JY |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include <PiPei.h>\r | |
10 | #include <Library/PcdLib.h>\r | |
11 | \r | |
12 | /**\r | |
13 | Get current boot mode.\r | |
14 | \r | |
15 | @note At this point, memory is ready, PeiServices are NOT available to use.\r | |
16 | Platform can get some data from chipset register.\r | |
17 | \r | |
18 | @return BootMode current boot mode.\r | |
19 | **/\r | |
20 | UINT32\r | |
21 | EFIAPI\r | |
22 | GetBootMode (\r | |
23 | VOID\r | |
24 | )\r | |
25 | {\r | |
26 | return BOOT_WITH_FULL_CONFIGURATION;\r | |
27 | }\r | |
28 | \r | |
29 | /**\r | |
30 | Get NVS buffer parameter.\r | |
31 | \r | |
32 | @note At this point, memory is NOT ready, PeiServices are available to use.\r | |
33 | \r | |
34 | @return NvsBuffer NVS buffer parameter.\r | |
35 | **/\r | |
36 | VOID *\r | |
37 | EFIAPI\r | |
38 | GetNvsBuffer (\r | |
39 | VOID\r | |
40 | )\r | |
41 | {\r | |
42 | return NULL;\r | |
43 | }\r | |
44 | \r | |
45 | /**\r | |
46 | Get UPD region size.\r | |
47 | \r | |
48 | @note At this point, memory is NOT ready, PeiServices are available to use.\r | |
49 | \r | |
50 | @return UPD region size.\r | |
51 | **/\r | |
52 | UINT32\r | |
53 | EFIAPI\r | |
54 | GetUpdRegionSize (\r | |
55 | VOID\r | |
56 | )\r | |
57 | {\r | |
58 | return 0;\r | |
59 | }\r | |
60 | \r | |
61 | /**\r | |
62 | This function overrides the default configurations in the UPD data region.\r | |
63 | \r | |
64 | @note At this point, memory is NOT ready, PeiServices are available to use.\r | |
65 | \r | |
66 | @param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strcture.\r | |
67 | \r | |
68 | @return FspUpdRgnPtr A pointer to the UPD data region data strcture.\r | |
69 | **/\r | |
70 | VOID *\r | |
71 | EFIAPI\r | |
72 | UpdateFspUpdConfigs (\r | |
73 | IN OUT VOID *FspUpdRgnPtr\r | |
74 | )\r | |
75 | {\r | |
76 | return NULL;\r | |
77 | }\r | |
78 | \r | |
88a539ca JY |
79 | /**\r |
80 | Get BootLoader Tolum size.\r | |
81 | \r | |
82 | @note At this point, memory is NOT ready, PeiServices are available to use.\r | |
83 | \r | |
84 | @return BootLoader Tolum size.\r | |
85 | **/\r | |
86 | UINT32\r | |
87 | EFIAPI\r | |
88 | GetBootLoaderTolumSize (\r | |
89 | VOID\r | |
90 | )\r | |
91 | {\r | |
92 | return 0;\r | |
93 | }\r | |
94 | \r | |
d8043ce9 JY |
95 | /**\r |
96 | Get TempRamExit parameter.\r | |
97 | \r | |
98 | @note At this point, memory is ready, PeiServices are available to use.\r | |
99 | \r | |
100 | @return TempRamExit parameter.\r | |
101 | **/\r | |
102 | VOID *\r | |
103 | EFIAPI\r | |
104 | GetTempRamExitParam (\r | |
105 | VOID\r | |
106 | )\r | |
107 | {\r | |
108 | return NULL;\r | |
109 | }\r | |
110 | \r | |
111 | /**\r | |
112 | Get FspSiliconInit parameter.\r | |
113 | \r | |
114 | @note At this point, memory is ready, PeiServices are available to use.\r | |
115 | \r | |
116 | @return FspSiliconInit parameter.\r | |
117 | **/\r | |
118 | VOID *\r | |
119 | EFIAPI\r | |
120 | GetFspSiliconInitParam (\r | |
121 | VOID\r | |
122 | )\r | |
123 | {\r | |
124 | return NULL;\r | |
125 | }\r | |
126 | \r | |
a33a2f62 JY |
127 | /**\r |
128 | Get S3 PEI memory information.\r | |
129 | \r | |
130 | @note At this point, memory is ready, and PeiServices are available to use.\r | |
131 | Platform can get some data from SMRAM directly.\r | |
132 | \r | |
133 | @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.\r | |
134 | @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.\r | |
135 | \r | |
136 | @return If S3 PEI memory information is got successfully.\r | |
137 | **/\r | |
138 | EFI_STATUS\r | |
139 | EFIAPI\r | |
140 | GetS3MemoryInfo (\r | |
141 | OUT UINT64 *S3PeiMemSize,\r | |
142 | OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase\r | |
143 | )\r | |
144 | {\r | |
145 | return EFI_UNSUPPORTED;\r | |
146 | }\r | |
147 | \r | |
148 | /**\r | |
149 | Get stack information according to boot mode.\r | |
150 | \r | |
151 | @note If BootMode is BOOT_ON_S3_RESUME or BOOT_ON_FLASH_UPDATE,\r | |
152 | this stack should be in some reserved memory space.\r | |
153 | \r | |
154 | @note If FspInitDone is TRUE, memory is ready, but no PeiServices there.\r | |
155 | Platform can get some data from SMRAM directly.\r | |
156 | @note If FspInitDone is FALSE, memory is NOT ready, but PeiServices are available to use.\r | |
157 | Platform can get some data from variable via VariablePpi.\r | |
158 | \r | |
159 | @param[in] BootMode Current boot mode.\r | |
160 | @param[in] FspInitDone If FspInit is called.\r | |
161 | @param[out] StackSize Stack size to be used in PEI phase.\r | |
162 | @param[out] StackBase Stack base to be used in PEI phase.\r | |
163 | \r | |
164 | @return If Stack information is got successfully.\r | |
165 | **/\r | |
166 | EFI_STATUS\r | |
167 | EFIAPI\r | |
168 | GetStackInfo (\r | |
169 | IN UINT32 BootMode,\r | |
170 | IN BOOLEAN FspInitDone,\r | |
171 | OUT UINT64 *StackSize,\r | |
172 | OUT EFI_PHYSICAL_ADDRESS *StackBase\r | |
173 | )\r | |
174 | {\r | |
175 | *StackBase = PcdGet32 (PcdTemporaryRamBase);\r | |
176 | *StackSize = PcdGet32 (PcdTemporaryRamSize);\r | |
177 | \r | |
178 | if (BootMode == BOOT_ON_S3_RESUME) {\r | |
179 | if (!FspInitDone) {\r | |
180 | } else {\r | |
181 | }\r | |
182 | } else if (BootMode == BOOT_ON_FLASH_UPDATE) {\r | |
183 | if (!FspInitDone) {\r | |
184 | } else {\r | |
185 | }\r | |
186 | }\r | |
187 | \r | |
188 | return EFI_SUCCESS;\r | |
189 | }\r |