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a41b5272 | 1 | /** @file\r |
2 | Header file for IDE mode of ATA host controller.\r | |
3 | \r | |
490b5ea1 | 4 | Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r |
a41b5272 | 5 | This program and the accompanying materials \r |
6 | are licensed and made available under the terms and conditions of the BSD License \r | |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
13 | **/\r | |
14 | #ifndef __ATA_HC_IDE_MODE_H__\r | |
15 | #define __ATA_HC_IDE_MODE_H__\r | |
16 | \r | |
17 | typedef enum {\r | |
18 | EfiIdePrimary = 0,\r | |
19 | EfiIdeSecondary = 1,\r | |
20 | EfiIdeMaxChannel = 2\r | |
21 | } EFI_IDE_CHANNEL;\r | |
22 | \r | |
23 | typedef enum {\r | |
24 | EfiIdeMaster = 0,\r | |
25 | EfiIdeSlave = 1,\r | |
26 | EfiIdeMaxDevice = 2\r | |
27 | } EFI_IDE_DEVICE;\r | |
28 | \r | |
29 | ///\r | |
30 | /// PIO mode definition\r | |
31 | ///\r | |
32 | typedef enum {\r | |
33 | EfiAtaPioModeBelow2,\r | |
34 | EfiAtaPioMode2,\r | |
35 | EfiAtaPioMode3,\r | |
36 | EfiAtaPioMode4\r | |
37 | } EFI_ATA_PIO_MODE;\r | |
38 | \r | |
39 | //\r | |
40 | // Multi word DMA definition\r | |
41 | //\r | |
42 | typedef enum {\r | |
43 | EfiAtaMdmaMode0,\r | |
44 | EfiAtaMdmaMode1,\r | |
45 | EfiAtaMdmaMode2\r | |
46 | } EFI_ATA_MDMA_MODE;\r | |
47 | \r | |
48 | //\r | |
49 | // UDMA mode definition\r | |
50 | //\r | |
51 | typedef enum {\r | |
52 | EfiAtaUdmaMode0,\r | |
53 | EfiAtaUdmaMode1,\r | |
54 | EfiAtaUdmaMode2,\r | |
55 | EfiAtaUdmaMode3,\r | |
56 | EfiAtaUdmaMode4,\r | |
57 | EfiAtaUdmaMode5\r | |
58 | } EFI_ATA_UDMA_MODE;\r | |
59 | \r | |
60 | //\r | |
61 | // Bus Master Reg\r | |
62 | //\r | |
63 | #define BMIC_NREAD BIT3\r | |
64 | #define BMIC_START BIT0\r | |
65 | #define BMIS_INTERRUPT BIT2\r | |
66 | #define BMIS_ERROR BIT1\r | |
67 | \r | |
68 | #define BMIC_OFFSET 0x00\r | |
69 | #define BMIS_OFFSET 0x02\r | |
70 | #define BMID_OFFSET 0x04\r | |
71 | \r | |
72 | //\r | |
73 | // IDE transfer mode\r | |
74 | //\r | |
75 | #define EFI_ATA_MODE_DEFAULT_PIO 0x00\r | |
76 | #define EFI_ATA_MODE_FLOW_PIO 0x01\r | |
77 | #define EFI_ATA_MODE_MDMA 0x04\r | |
78 | #define EFI_ATA_MODE_UDMA 0x08\r | |
79 | \r | |
80 | typedef struct {\r | |
81 | UINT32 RegionBaseAddr;\r | |
82 | UINT16 ByteCount;\r | |
83 | UINT16 EndOfTable;\r | |
84 | } EFI_ATA_DMA_PRD;\r | |
85 | \r | |
86 | typedef struct {\r | |
87 | UINT8 ModeNumber : 3;\r | |
88 | UINT8 ModeCategory : 5;\r | |
89 | } EFI_ATA_TRANSFER_MODE;\r | |
90 | \r | |
91 | typedef struct {\r | |
92 | UINT8 Sector;\r | |
93 | UINT8 Heads;\r | |
94 | UINT8 MultipleSector;\r | |
95 | } EFI_ATA_DRIVE_PARMS;\r | |
96 | \r | |
97 | //\r | |
98 | // IDE registers set\r | |
99 | //\r | |
100 | typedef struct {\r | |
101 | UINT16 Data;\r | |
102 | UINT16 ErrOrFeature;\r | |
103 | UINT16 SectorCount;\r | |
104 | UINT16 SectorNumber;\r | |
105 | UINT16 CylinderLsb;\r | |
106 | UINT16 CylinderMsb;\r | |
107 | UINT16 Head;\r | |
108 | UINT16 CmdOrStatus;\r | |
109 | UINT16 AltOrDev;\r | |
110 | \r | |
111 | UINT16 BusMasterBaseAddr;\r | |
112 | } EFI_IDE_REGISTERS;\r | |
113 | \r | |
114 | //\r | |
115 | // Bit definitions in Programming Interface byte of the Class Code field\r | |
116 | // in PCI IDE controller's Configuration Space\r | |
117 | //\r | |
118 | #define IDE_PRIMARY_OPERATING_MODE BIT0\r | |
119 | #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1\r | |
120 | #define IDE_SECONDARY_OPERATING_MODE BIT2\r | |
121 | #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3\r | |
122 | \r | |
123 | /**\r | |
124 | Get IDE i/o port registers' base addresses by mode. \r | |
125 | \r | |
126 | In 'Compatibility' mode, use fixed addresses.\r | |
127 | In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's\r | |
128 | Configuration Space.\r | |
129 | \r | |
130 | The steps to get IDE i/o port registers' base addresses for each channel\r | |
131 | as follows:\r | |
132 | \r | |
133 | 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE\r | |
134 | controller's Configuration Space to determine the operating mode.\r | |
135 | \r | |
136 | 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.\r | |
137 | ___________________________________________\r | |
138 | | | Command Block | Control Block |\r | |
139 | | Channel | Registers | Registers |\r | |
140 | |___________|_______________|_______________|\r | |
141 | | Primary | 1F0h - 1F7h | 3F6h - 3F7h |\r | |
142 | |___________|_______________|_______________|\r | |
143 | | Secondary | 170h - 177h | 376h - 377h |\r | |
144 | |___________|_______________|_______________|\r | |
145 | \r | |
146 | Table 1. Compatibility resource mappings\r | |
147 | \r | |
148 | b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs\r | |
149 | in IDE controller's PCI Configuration Space, shown in the Table 2 below.\r | |
150 | ___________________________________________________\r | |
151 | | | Command Block | Control Block |\r | |
152 | | Channel | Registers | Registers |\r | |
153 | |___________|___________________|___________________|\r | |
154 | | Primary | BAR at offset 0x10| BAR at offset 0x14|\r | |
155 | |___________|___________________|___________________|\r | |
156 | | Secondary | BAR at offset 0x18| BAR at offset 0x1C|\r | |
157 | |___________|___________________|___________________|\r | |
158 | \r | |
159 | Table 2. BARs for Register Mapping\r | |
160 | \r | |
161 | @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r | |
162 | @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r | |
163 | store the IDE i/o port registers' base addresses\r | |
164 | \r | |
165 | @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type\r | |
166 | @retval EFI_SUCCESS Get the Base address successfully\r | |
167 | @retval Other Read the pci configureation data error\r | |
168 | \r | |
169 | **/\r | |
170 | EFI_STATUS\r | |
171 | EFIAPI\r | |
172 | GetIdeRegisterIoAddr (\r | |
173 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
174 | IN OUT EFI_IDE_REGISTERS *IdeRegisters\r | |
175 | );\r | |
176 | \r | |
177 | /**\r | |
178 | This function is used to send out ATAPI commands conforms to the Packet Command \r | |
179 | with PIO Data In Protocol.\r | |
180 | \r | |
181 | @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance\r | |
182 | @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to\r | |
183 | store the IDE i/o port registers' base addresses\r | |
184 | @param[in] Channel The channel number of device.\r | |
185 | @param[in] Device The device number of device.\r | |
186 | @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.\r | |
187 | \r | |
188 | @retval EFI_SUCCESS send out the ATAPI packet command successfully\r | |
189 | and device sends data successfully.\r | |
190 | @retval EFI_DEVICE_ERROR the device failed to send data.\r | |
191 | \r | |
192 | **/\r | |
193 | EFI_STATUS\r | |
194 | EFIAPI\r | |
195 | AtaPacketCommandExecute (\r | |
196 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
197 | IN EFI_IDE_REGISTERS *IdeRegisters,\r | |
198 | IN UINT8 Channel,\r | |
199 | IN UINT8 Device,\r | |
200 | IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet\r | |
201 | );\r | |
202 | \r | |
a41b5272 | 203 | #endif\r |
204 | \r |