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913cb9dc | 1 | /** @file\r |
2 | \r | |
78c2ffb5 | 3 | This file contains the definination for host controller register operation routines.\r |
4 | \r | |
09943f5e | 5 | Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r |
cd5ebaa0 | 6 | This program and the accompanying materials\r |
913cb9dc | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
16 | #ifndef _EFI_EHCI_REG_H_\r | |
17 | #define _EFI_EHCI_REG_H_\r | |
18 | \r | |
1ccdbf2a | 19 | //\r |
20 | // EHCI register offset\r | |
21 | //\r | |
22 | \r | |
23 | \r | |
24 | //\r | |
25 | // Capability register offset\r | |
26 | //\r | |
27 | #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset\r | |
28 | #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h\r | |
29 | #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset\r | |
30 | \r | |
31 | //\r | |
32 | // Capability register bit definition\r | |
33 | //\r | |
34 | #define HCSP_NPORTS 0x0F // Number of root hub port\r | |
f01219e8 | 35 | #define HCSP_PPC 0x10 // Port Power Control\r |
1ccdbf2a | 36 | #define HCCP_64BIT 0x01 // 64-bit addressing capability\r |
37 | \r | |
38 | //\r | |
39 | // Operational register offset\r | |
40 | //\r | |
41 | #define EHC_USBCMD_OFFSET 0x0 // USB command register offset\r | |
42 | #define EHC_USBSTS_OFFSET 0x04 // Statue register offset\r | |
43 | #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset\r | |
44 | #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset\r | |
45 | #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset\r | |
46 | #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset\r | |
47 | #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset\r | |
48 | #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset\r | |
49 | #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset\r | |
50 | \r | |
51 | #define EHC_FRAME_LEN 1024\r | |
913cb9dc | 52 | \r |
1ccdbf2a | 53 | //\r |
54 | // Register bit definition\r | |
55 | //\r | |
56 | #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC\r | |
57 | \r | |
58 | #define USBCMD_RUN 0x01 // Run/stop\r | |
59 | #define USBCMD_RESET 0x02 // Start the host controller reset\r | |
60 | #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule\r | |
61 | #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule\r | |
62 | #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell\r | |
63 | \r | |
64 | #define USBSTS_IAA 0x20 // Interrupt on async advance\r | |
65 | #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status\r | |
66 | #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status\r | |
67 | #define USBSTS_HALT 0x1000 // Host controller halted\r | |
68 | #define USBSTS_SYS_ERROR 0x10 // Host system error\r | |
69 | #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC\r | |
70 | // (write clean) bits in USBSTS register\r | |
71 | \r | |
72 | #define PORTSC_CONN 0x01 // Current Connect Status\r | |
73 | #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change\r | |
74 | #define PORTSC_ENABLED 0x04 // Port Enable / Disable\r | |
75 | #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change\r | |
76 | #define PORTSC_OVERCUR 0x10 // Over current Active\r | |
77 | #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change\r | |
78 | #define PORSTSC_RESUME 0x40 // Force Port Resume\r | |
79 | #define PORTSC_SUSPEND 0x80 // Port Suspend State\r | |
80 | #define PORTSC_RESET 0x100 // Port Reset\r | |
81 | #define PORTSC_LINESTATE_K 0x400 // Line Status K-state\r | |
82 | #define PORTSC_LINESTATE_J 0x800 // Line Status J-state\r | |
83 | #define PORTSC_POWER 0x1000 // Port Power\r | |
84 | #define PORTSC_OWNER 0x2000 // Port Owner\r | |
85 | #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits,\r | |
86 | // they are WC (write clean)\r | |
87 | //\r | |
88 | // PCI Configuration Registers\r | |
89 | //\r | |
90 | #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10\r | |
913cb9dc | 91 | \r |
09943f5e | 92 | //\r |
93 | // Debug port capability id\r | |
94 | //\r | |
95 | #define EHC_DEBUG_PORT_CAP_ID 0x0A\r | |
96 | \r | |
913cb9dc | 97 | #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r |
98 | \r | |
99 | #define EHC_ADDR(High, QhHw32) \\r | |
100 | ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))\r | |
101 | \r | |
102 | #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)\r | |
103 | \r | |
104 | //\r | |
105 | // Structure to map the hardware port states to the\r | |
106 | // UEFI's port states.\r | |
107 | //\r | |
108 | typedef struct {\r | |
109 | UINT16 HwState;\r | |
110 | UINT16 UefiState;\r | |
111 | } USB_PORT_STATE_MAP;\r | |
112 | \r | |
113 | //\r | |
114 | // Ehci Data and Ctrl Structures\r | |
115 | //\r | |
116 | #pragma pack(1)\r | |
117 | typedef struct {\r | |
1ccdbf2a | 118 | UINT8 ProgInterface;\r |
913cb9dc | 119 | UINT8 SubClassCode;\r |
120 | UINT8 BaseCode;\r | |
121 | } USB_CLASSC;\r | |
122 | #pragma pack()\r | |
123 | \r | |
78c2ffb5 | 124 | /**\r |
125 | Read EHCI capability register.\r | |
126 | \r | |
127 | @param Ehc The EHCI device.\r | |
128 | @param Offset Capability register address.\r | |
129 | \r | |
130 | @return The register content.\r | |
913cb9dc | 131 | \r |
78c2ffb5 | 132 | **/\r |
913cb9dc | 133 | UINT32\r |
134 | EhcReadCapRegister (\r | |
135 | IN USB2_HC_DEV *Ehc,\r | |
136 | IN UINT32 Offset\r | |
ed66e1bc | 137 | );\r |
913cb9dc | 138 | \r |
09943f5e | 139 | /**\r |
140 | Read EHCI debug port register.\r | |
141 | \r | |
142 | @param Ehc The EHCI device.\r | |
143 | @param Offset Debug port register address.\r | |
144 | \r | |
145 | @return The register content read.\r | |
146 | @retval If err, return 0xffff.\r | |
147 | \r | |
148 | **/\r | |
149 | UINT32\r | |
150 | EhcReadDbgRegister (\r | |
151 | IN USB2_HC_DEV *Ehc,\r | |
152 | IN UINT32 Offset\r | |
153 | );\r | |
913cb9dc | 154 | \r |
155 | /**\r | |
78c2ffb5 | 156 | Read EHCI Operation register.\r |
913cb9dc | 157 | \r |
78c2ffb5 | 158 | @param Ehc The EHCI device.\r |
159 | @param Offset The operation register offset.\r | |
913cb9dc | 160 | \r |
78c2ffb5 | 161 | @return The register content.\r |
913cb9dc | 162 | \r |
163 | **/\r | |
164 | UINT32\r | |
165 | EhcReadOpReg (\r | |
166 | IN USB2_HC_DEV *Ehc,\r | |
167 | IN UINT32 Offset\r | |
ed66e1bc | 168 | );\r |
913cb9dc | 169 | \r |
170 | \r | |
171 | /**\r | |
78c2ffb5 | 172 | Write the data to the EHCI operation register.\r |
913cb9dc | 173 | \r |
78c2ffb5 | 174 | @param Ehc The EHCI device.\r |
175 | @param Offset EHCI operation register offset.\r | |
176 | @param Data The data to write.\r | |
913cb9dc | 177 | \r |
913cb9dc | 178 | **/\r |
179 | VOID\r | |
180 | EhcWriteOpReg (\r | |
181 | IN USB2_HC_DEV *Ehc,\r | |
182 | IN UINT32 Offset,\r | |
183 | IN UINT32 Data\r | |
ed66e1bc | 184 | );\r |
913cb9dc | 185 | \r |
efe9186f | 186 | /**\r |
187 | Set one bit of the operational register while keeping other bits.\r | |
188 | \r | |
189 | @param Ehc The EHCI device.\r | |
190 | @param Offset The offset of the operational register.\r | |
191 | @param Bit The bit mask of the register to set.\r | |
192 | \r | |
193 | **/\r | |
194 | VOID\r | |
195 | EhcSetOpRegBit (\r | |
196 | IN USB2_HC_DEV *Ehc,\r | |
197 | IN UINT32 Offset,\r | |
198 | IN UINT32 Bit\r | |
199 | );\r | |
200 | \r | |
201 | /**\r | |
202 | Clear one bit of the operational register while keeping other bits.\r | |
203 | \r | |
204 | @param Ehc The EHCI device.\r | |
205 | @param Offset The offset of the operational register.\r | |
206 | @param Bit The bit mask of the register to clear.\r | |
207 | \r | |
208 | **/\r | |
209 | VOID\r | |
210 | EhcClearOpRegBit (\r | |
211 | IN USB2_HC_DEV *Ehc,\r | |
212 | IN UINT32 Offset,\r | |
213 | IN UINT32 Bit\r | |
214 | );\r | |
913cb9dc | 215 | \r |
216 | /**\r | |
217 | Add support for UEFI Over Legacy (UoL) feature, stop\r | |
78c2ffb5 | 218 | the legacy USB SMI support.\r |
913cb9dc | 219 | \r |
220 | @param Ehc The EHCI device.\r | |
221 | \r | |
913cb9dc | 222 | **/\r |
223 | VOID\r | |
224 | EhcClearLegacySupport (\r | |
225 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 226 | );\r |
913cb9dc | 227 | \r |
228 | \r | |
229 | \r | |
230 | /**\r | |
231 | Set door bell and wait it to be ACKed by host controller.\r | |
232 | This function is used to synchronize with the hardware.\r | |
233 | \r | |
78c2ffb5 | 234 | @param Ehc The EHCI device.\r |
235 | @param Timeout The time to wait before abort (in millisecond, ms).\r | |
913cb9dc | 236 | \r |
78c2ffb5 | 237 | @retval EFI_SUCCESS Synchronized with the hardware.\r |
238 | @retval EFI_TIMEOUT Time out happened while waiting door bell to set.\r | |
913cb9dc | 239 | \r |
240 | **/\r | |
241 | EFI_STATUS\r | |
242 | EhcSetAndWaitDoorBell (\r | |
243 | IN USB2_HC_DEV *Ehc,\r | |
244 | IN UINT32 Timeout\r | |
ed66e1bc | 245 | );\r |
913cb9dc | 246 | \r |
247 | \r | |
248 | /**\r | |
78c2ffb5 | 249 | Clear all the interrutp status bits, these bits are Write-Clean.\r |
913cb9dc | 250 | \r |
78c2ffb5 | 251 | @param Ehc The EHCI device.\r |
913cb9dc | 252 | \r |
913cb9dc | 253 | **/\r |
254 | VOID\r | |
255 | EhcAckAllInterrupt (\r | |
256 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 257 | );\r |
913cb9dc | 258 | \r |
259 | \r | |
260 | \r | |
261 | /**\r | |
78c2ffb5 | 262 | Whether Ehc is halted.\r |
913cb9dc | 263 | \r |
78c2ffb5 | 264 | @param Ehc The EHCI device.\r |
913cb9dc | 265 | \r |
78c2ffb5 | 266 | @retval TRUE The controller is halted.\r |
267 | @retval FALSE It isn't halted.\r | |
913cb9dc | 268 | \r |
269 | **/\r | |
270 | BOOLEAN\r | |
271 | EhcIsHalt (\r | |
272 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 273 | );\r |
913cb9dc | 274 | \r |
275 | \r | |
276 | /**\r | |
78c2ffb5 | 277 | Whether system error occurred.\r |
913cb9dc | 278 | \r |
78c2ffb5 | 279 | @param Ehc The EHCI device.\r |
913cb9dc | 280 | \r |
78c2ffb5 | 281 | @retval TRUE System error happened.\r |
282 | @retval FALSE No system error.\r | |
913cb9dc | 283 | \r |
284 | **/\r | |
285 | BOOLEAN\r | |
286 | EhcIsSysError (\r | |
287 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 288 | );\r |
913cb9dc | 289 | \r |
290 | \r | |
913cb9dc | 291 | /**\r |
78c2ffb5 | 292 | Reset the host controller.\r |
913cb9dc | 293 | \r |
78c2ffb5 | 294 | @param Ehc The EHCI device.\r |
295 | @param Timeout Time to wait before abort (in millisecond, ms).\r | |
913cb9dc | 296 | \r |
78c2ffb5 | 297 | @retval EFI_SUCCESS The host controller is reset.\r |
298 | @return Others Failed to reset the host.\r | |
913cb9dc | 299 | \r |
300 | **/\r | |
301 | EFI_STATUS\r | |
302 | EhcResetHC (\r | |
303 | IN USB2_HC_DEV *Ehc,\r | |
304 | IN UINT32 Timeout\r | |
ed66e1bc | 305 | );\r |
913cb9dc | 306 | \r |
307 | \r | |
913cb9dc | 308 | /**\r |
78c2ffb5 | 309 | Halt the host controller.\r |
913cb9dc | 310 | \r |
78c2ffb5 | 311 | @param Ehc The EHCI device.\r |
312 | @param Timeout Time to wait before abort.\r | |
913cb9dc | 313 | \r |
78c2ffb5 | 314 | @return EFI_SUCCESS The EHCI is halt.\r |
315 | @return EFI_TIMEOUT Failed to halt the controller before Timeout.\r | |
913cb9dc | 316 | \r |
317 | **/\r | |
318 | EFI_STATUS\r | |
319 | EhcHaltHC (\r | |
320 | IN USB2_HC_DEV *Ehc,\r | |
321 | IN UINT32 Timeout\r | |
ed66e1bc | 322 | );\r |
913cb9dc | 323 | \r |
324 | \r | |
913cb9dc | 325 | /**\r |
78c2ffb5 | 326 | Set the EHCI to run.\r |
913cb9dc | 327 | \r |
78c2ffb5 | 328 | @param Ehc The EHCI device.\r |
329 | @param Timeout Time to wait before abort.\r | |
913cb9dc | 330 | \r |
78c2ffb5 | 331 | @return EFI_SUCCESS The EHCI is running.\r |
332 | @return Others Failed to set the EHCI to run.\r | |
913cb9dc | 333 | \r |
334 | **/\r | |
335 | EFI_STATUS\r | |
336 | EhcRunHC (\r | |
337 | IN USB2_HC_DEV *Ehc,\r | |
338 | IN UINT32 Timeout\r | |
ed66e1bc | 339 | );\r |
913cb9dc | 340 | \r |
341 | \r | |
342 | \r | |
343 | /**\r | |
344 | Initialize the HC hardware.\r | |
78c2ffb5 | 345 | EHCI spec lists the five things to do to initialize the hardware:\r |
913cb9dc | 346 | 1. Program CTRLDSSEGMENT\r |
347 | 2. Set USBINTR to enable interrupts\r | |
348 | 3. Set periodic list base\r | |
349 | 4. Set USBCMD, interrupt threshold, frame list size etc\r | |
350 | 5. Write 1 to CONFIGFLAG to route all ports to EHCI\r | |
351 | \r | |
78c2ffb5 | 352 | @param Ehc The EHCI device.\r |
913cb9dc | 353 | \r |
78c2ffb5 | 354 | @return EFI_SUCCESS The EHCI has come out of halt state.\r |
355 | @return EFI_TIMEOUT Time out happened.\r | |
913cb9dc | 356 | \r |
357 | **/\r | |
358 | EFI_STATUS\r | |
359 | EhcInitHC (\r | |
360 | IN USB2_HC_DEV *Ehc\r | |
ed66e1bc | 361 | );\r |
913cb9dc | 362 | \r |
363 | #endif\r |