[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciSched.c

/** @file\r
\r
  EHCI transfer scheduling routines.\r
\r
Copyright (c) 2007 - 2010, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "Ehci.h"\r
\r
\r
/**\r
  Create helper QTD/QH for the EHCI device.\r
\r
  @param  Ehc                   The EHCI device.\r
\r
  @retval EFI_OUT_OF_RESOURCES  Failed to allocate resource for helper QTD/QH.\r
  @retval EFI_SUCCESS           Helper QH/QTD are created.\r
\r
**/\r
EFI_STATUS\r
EhcCreateHelpQ (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  USB_ENDPOINT            Ep;\r
  EHC_QH                  *Qh;\r
  QH_HW                   *QhHw;\r
  EHC_QTD                 *Qtd;\r
  EFI_PHYSICAL_ADDRESS    PciAddr;\r
\r
  //\r
  // Create an inactive Qtd to terminate the short packet read.\r
  //\r
  Qtd = EhcCreateQtd (Ehc, NULL, NULL, 0, QTD_PID_INPUT, 0, 64);\r
\r
  if (Qtd == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  Qtd->QtdHw.Status   = QTD_STAT_HALTED;\r
  Ehc->ShortReadStop  = Qtd;\r
\r
  //\r
  // Create a QH to act as the EHC reclamation header.\r
  // Set the header to loopback to itself.\r
  //\r
  Ep.DevAddr    = 0;\r
  Ep.EpAddr     = 1;\r
  Ep.Direction  = EfiUsbDataIn;\r
  Ep.DevSpeed   = EFI_USB_SPEED_HIGH;\r
  Ep.MaxPacket  = 64;\r
  Ep.HubAddr    = 0;\r
  Ep.HubPort    = 0;\r
  Ep.Toggle     = 0;\r
  Ep.Type       = EHC_BULK_TRANSFER;\r
  Ep.PollRate   = 1;\r
\r
  Qh            = EhcCreateQh (Ehc, &Ep);\r
\r
  if (Qh == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  PciAddr           = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
  QhHw              = &Qh->QhHw;\r
  QhHw->HorizonLink = QH_LINK (PciAddr + OFFSET_OF(EHC_QH, QhHw), EHC_TYPE_QH, FALSE);\r
  QhHw->Status      = QTD_STAT_HALTED;\r
  QhHw->ReclaimHead = 1;\r
  Ehc->ReclaimHead  = Qh;\r
\r
  //\r
  // Create a dummy QH to act as the terminator for periodical schedule\r
  //\r
  Ep.EpAddr   = 2;\r
  Ep.Type     = EHC_INT_TRANSFER_SYNC;\r
\r
  Qh          = EhcCreateQh (Ehc, &Ep);\r
\r
  if (Qh == NULL) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  Qh->QhHw.Status = QTD_STAT_HALTED;\r
  Ehc->PeriodOne  = Qh;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  Initialize the schedule data structure such as frame list.\r
\r
  @param  Ehc                   The EHCI device to init schedule data.\r
\r
  @retval EFI_OUT_OF_RESOURCES  Failed to allocate resource to init schedule data.\r
  @retval EFI_SUCCESS           The schedule data is initialized.\r
\r
**/\r
EFI_STATUS\r
EhcInitSched (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  EFI_PCI_IO_PROTOCOL   *PciIo;\r
  VOID                  *Buf;\r
  EFI_PHYSICAL_ADDRESS  PhyAddr;\r
  VOID                  *Map;\r
  UINTN                 Pages;\r
  UINTN                 Bytes;\r
  UINTN                 Index;\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  PciAddr;\r
\r
  //\r
  // First initialize the periodical schedule data:\r
  // 1. Allocate and map the memory for the frame list\r
  // 2. Create the help QTD/QH\r
  // 3. Initialize the frame entries\r
  // 4. Set the frame list register\r
  //\r
  PciIo = Ehc->PciIo;\r
\r
  Bytes = 4096;\r
  Pages = EFI_SIZE_TO_PAGES (Bytes);\r
\r
  Status = PciIo->AllocateBuffer (\r
                    PciIo,\r
                    AllocateAnyPages,\r
                    EfiBootServicesData,\r
                    Pages,\r
                    &Buf,\r
                    0\r
                    );\r
\r
  if (EFI_ERROR (Status)) {\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  Status = PciIo->Map (\r
                    PciIo,\r
                    EfiPciIoOperationBusMasterCommonBuffer,\r
                    Buf,\r
                    &Bytes,\r
                    &PhyAddr,\r
                    &Map\r
                    );\r
\r
  if (EFI_ERROR (Status) || (Bytes != 4096)) {\r
    PciIo->FreeBuffer (PciIo, Pages, Buf);\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  Ehc->PeriodFrame      = Buf;\r
  Ehc->PeriodFrameMap   = Map;\r
\r
  //\r
  // Program the FRAMELISTBASE register with the low 32 bit addr\r
  //\r
  EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, EHC_LOW_32BIT (PhyAddr));\r
  //\r
  // Program the CTRLDSSEGMENT register with the high 32 bit addr\r
  //\r
  EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, EHC_HIGH_32BIT (PhyAddr));\r
\r
  //\r
  // Init memory pool management then create the helper\r
  // QTD/QH. If failed, previously allocated resources\r
  // will be freed by EhcFreeSched\r
  //\r
  Ehc->MemPool = UsbHcInitMemPool (\r
                   PciIo,\r
                   EHC_BIT_IS_SET (Ehc->HcCapParams, HCCP_64BIT),\r
                   EHC_HIGH_32BIT (PhyAddr)\r
                   );\r
\r
  if (Ehc->MemPool == NULL) {\r
    goto ErrorExit;\r
  }\r
\r
  Status = EhcCreateHelpQ (Ehc);\r
\r
  if (EFI_ERROR (Status)) {\r
    goto ErrorExit;\r
  }\r
\r
  //\r
  // Initialize the frame list entries then set the registers\r
  //\r
  Ehc->PeriodFrameHost      = AllocateZeroPool (EHC_FRAME_LEN * sizeof (UINTN));\r
  if (Ehc->PeriodFrameHost == NULL) {\r
    Status = EFI_OUT_OF_RESOURCES;\r
    goto ErrorExit;\r
  }\r
\r
  PciAddr  = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
\r
  for (Index = 0; Index < EHC_FRAME_LEN; Index++) {\r
    //\r
    // Store the pci bus address of the QH in period frame list which will be accessed by pci bus master.\r
    //\r
    ((UINT32 *)(Ehc->PeriodFrame))[Index] = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
    //\r
    // Store the host address of the QH in period frame list which will be accessed by host.\r
    //\r
    ((UINTN *)(Ehc->PeriodFrameHost))[Index] = (UINTN)Ehc->PeriodOne;\r
  }\r
\r
  //\r
  // Second initialize the asynchronous schedule:\r
  // Only need to set the AsynListAddr register to\r
  // the reclamation header\r
  //\r
  PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (EHC_QH));\r
  EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (PciAddr));\r
  return EFI_SUCCESS;\r
\r
ErrorExit:\r
  PciIo->FreeBuffer (PciIo, Pages, Buf);\r
  PciIo->Unmap (PciIo, Map);\r
\r
  if (Ehc->PeriodOne != NULL) {\r
    UsbHcFreeMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
    Ehc->PeriodOne = NULL;\r
  }\r
\r
  if (Ehc->ReclaimHead != NULL) {\r
    UsbHcFreeMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (EHC_QH));\r
    Ehc->ReclaimHead = NULL;\r
  }\r
\r
  if (Ehc->ShortReadStop != NULL) {\r
    UsbHcFreeMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));\r
    Ehc->ShortReadStop = NULL;\r
  }\r
  return Status;\r
}\r
\r
\r
/**\r
  Free the schedule data. It may be partially initialized.\r
\r
  @param  Ehc                   The EHCI device.\r
\r
**/\r
VOID\r
EhcFreeSched (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  EFI_PCI_IO_PROTOCOL     *PciIo;\r
\r
  EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);\r
  EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);\r
\r
  if (Ehc->PeriodOne != NULL) {\r
    UsbHcFreeMem (Ehc->MemPool, Ehc->PeriodOne, sizeof (EHC_QH));\r
    Ehc->PeriodOne = NULL;\r
  }\r
\r
  if (Ehc->ReclaimHead != NULL) {\r
    UsbHcFreeMem (Ehc->MemPool, Ehc->ReclaimHead, sizeof (EHC_QH));\r
    Ehc->ReclaimHead = NULL;\r
  }\r
\r
  if (Ehc->ShortReadStop != NULL) {\r
    UsbHcFreeMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));\r
    Ehc->ShortReadStop = NULL;\r
  }\r
\r
  if (Ehc->MemPool != NULL) {\r
    UsbHcFreeMemPool (Ehc->MemPool);\r
    Ehc->MemPool = NULL;\r
  }\r
\r
  if (Ehc->PeriodFrame != NULL) {\r
    PciIo = Ehc->PciIo;\r
    ASSERT (PciIo != NULL);\r
\r
    PciIo->Unmap (PciIo, Ehc->PeriodFrameMap);\r
\r
    PciIo->FreeBuffer (\r
             PciIo,\r
             EFI_SIZE_TO_PAGES (EFI_PAGE_SIZE),\r
             Ehc->PeriodFrame\r
             );\r
\r
    Ehc->PeriodFrame = NULL;\r
  }\r
\r
  if (Ehc->PeriodFrameHost != NULL) {\r
    FreePool (Ehc->PeriodFrameHost);\r
    Ehc->PeriodFrameHost = NULL;\r
  }\r
}\r
\r
\r
/**\r
  Link the queue head to the asynchronous schedule list.\r
  UEFI only supports one CTRL/BULK transfer at a time\r
  due to its interfaces. This simplifies the AsynList\r
  management: A reclamation header is always linked to\r
  the AsyncListAddr, the only active QH is appended to it.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Qh                    The queue head to link.\r
\r
**/\r
VOID\r
EhcLinkQhToAsync (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN EHC_QH               *Qh\r
  )\r
{\r
  EHC_QH                  *Head;\r
  EFI_PHYSICAL_ADDRESS    PciAddr;\r
\r
  //\r
  // Append the queue head after the reclaim header, then\r
  // fix the hardware visiable parts (EHCI R1.0 page 72).\r
  // ReclaimHead is always linked to the EHCI's AsynListAddr.\r
  //\r
  Head                    = Ehc->ReclaimHead;\r
\r
  Qh->NextQh              = Head->NextQh;\r
  Head->NextQh            = Qh;\r
\r
  PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head, sizeof (EHC_QH));\r
  Qh->QhHw.HorizonLink    = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
  PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
  Head->QhHw.HorizonLink  = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
}\r
\r
\r
/**\r
  Unlink a queue head from the asynchronous schedule list.\r
  Need to synchronize with hardware.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Qh                    The queue head to unlink.\r
\r
**/\r
VOID\r
EhcUnlinkQhFromAsync (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN EHC_QH               *Qh\r
  )\r
{\r
  EHC_QH                  *Head;\r
  EFI_STATUS              Status;\r
  EFI_PHYSICAL_ADDRESS    PciAddr;\r
\r
  ASSERT (Ehc->ReclaimHead->NextQh == Qh);\r
\r
  //\r
  // Remove the QH from reclamation head, then update the hardware\r
  // visiable part: Only need to loopback the ReclaimHead. The Qh\r
  // is pointing to ReclaimHead (which is staill in the list).\r
  //\r
  Head                    = Ehc->ReclaimHead;\r
\r
  Head->NextQh            = Qh->NextQh;\r
  Qh->NextQh              = NULL;\r
\r
  PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Head, sizeof (EHC_QH));\r
  Head->QhHw.HorizonLink  = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
\r
  //\r
  // Set and wait the door bell to synchronize with the hardware\r
  //\r
  Status = EhcSetAndWaitDoorBell (Ehc, EHC_GENERIC_TIMEOUT);\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((EFI_D_ERROR, "EhcUnlinkQhFromAsync: Failed to synchronize with doorbell\n"));\r
  }\r
}\r
\r
\r
/**\r
  Link a queue head for interrupt transfer to the periodic\r
  schedule frame list. This code is very much the same as\r
  that in UHCI.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Qh                    The queue head to link.\r
\r
**/\r
VOID\r
EhcLinkQhToPeriod (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN EHC_QH               *Qh\r
  )\r
{\r
  UINTN                   Index;\r
  EHC_QH                  *Prev;\r
  EHC_QH                  *Next;\r
  EFI_PHYSICAL_ADDRESS    PciAddr;\r
\r
  for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {\r
    //\r
    // First QH can't be NULL because we always keep PeriodOne\r
    // heads on the frame list\r
    //\r
    ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));\r
    Next  = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];\r
    Prev  = NULL;\r
\r
    //\r
    // Now, insert the queue head (Qh) into this frame:\r
    // 1. Find a queue head with the same poll interval, just insert\r
    //    Qh after this queue head, then we are done.\r
    //\r
    // 2. Find the position to insert the queue head into:\r
    //      Previous head's interval is bigger than Qh's\r
    //      Next head's interval is less than Qh's\r
    //    Then, insert the Qh between then\r
    //\r
    while (Next->Interval > Qh->Interval) {\r
      Prev  = Next;\r
      Next  = Next->NextQh;\r
    }\r
\r
    ASSERT (Next != NULL);\r
\r
    //\r
    // The entry may have been linked into the frame by early insertation.\r
    // For example: if insert a Qh with Qh.Interval == 4, and there is a Qh\r
    // with Qh.Interval == 8 on the frame. If so, we are done with this frame.\r
    // It isn't necessary to compare all the QH with the same interval to\r
    // Qh. This is because if there is other QH with the same interval, Qh\r
    // should has been inserted after that at Frames[0] and at Frames[0] it is\r
    // impossible for (Next == Qh)\r
    //\r
    if (Next == Qh) {\r
      continue;\r
    }\r
\r
    if (Next->Interval == Qh->Interval) {\r
      //\r
      // If there is a QH with the same interval, it locates at\r
      // Frames[0], and we can simply insert it after this QH. We\r
      // are all done.\r
      //\r
      ASSERT ((Index == 0) && (Qh->NextQh == NULL));\r
\r
      Prev                    = Next;\r
      Next                    = Next->NextQh;\r
\r
      Qh->NextQh              = Next;\r
      Prev->NextQh            = Qh;\r
\r
      Qh->QhHw.HorizonLink    = Prev->QhHw.HorizonLink;\r
      PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
      Prev->QhHw.HorizonLink  = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
      break;\r
    }\r
\r
    //\r
    // OK, find the right position, insert it in. If Qh's next\r
    // link has already been set, it is in position. This is\r
    // guarranted by 2^n polling interval.\r
    //\r
    if (Qh->NextQh == NULL) {\r
      Qh->NextQh              = Next;\r
      PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Next, sizeof (EHC_QH));\r
      Qh->QhHw.HorizonLink    = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
    }\r
\r
    PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Qh, sizeof (EHC_QH));\r
\r
    if (Prev == NULL) {\r
      ((UINT32*)Ehc->PeriodFrame)[Index]     = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
      ((UINTN*)Ehc->PeriodFrameHost)[Index]  = (UINTN)Qh;\r
    } else {\r
      Prev->NextQh            = Qh;\r
      Prev->QhHw.HorizonLink  = QH_LINK (PciAddr, EHC_TYPE_QH, FALSE);\r
    }\r
  }\r
}\r
\r
\r
/**\r
  Unlink an interrupt queue head from the periodic\r
  schedule frame list.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Qh                    The queue head to unlink.\r
\r
**/\r
VOID\r
EhcUnlinkQhFromPeriod (\r
  IN USB2_HC_DEV          *Ehc,\r
  IN EHC_QH               *Qh\r
  )\r
{\r
  UINTN                   Index;\r
  EHC_QH                  *Prev;\r
  EHC_QH                  *This;\r
\r
  for (Index = 0; Index < EHC_FRAME_LEN; Index += Qh->Interval) {\r
    //\r
    // Frame link can't be NULL because we always keep PeroidOne\r
    // on the frame list\r
    //\r
    ASSERT (!EHC_LINK_TERMINATED (((UINT32*)Ehc->PeriodFrame)[Index]));\r
    This  = (EHC_QH*)((UINTN*)Ehc->PeriodFrameHost)[Index];\r
    Prev  = NULL;\r
\r
    //\r
    // Walk through the frame's QH list to find the\r
    // queue head to remove\r
    //\r
    while ((This != NULL) && (This != Qh)) {\r
      Prev  = This;\r
      This  = This->NextQh;\r
    }\r
\r
    //\r
    // Qh may have already been unlinked from this frame\r
    // by early action. See the comments in EhcLinkQhToPeriod.\r
    //\r
    if (This == NULL) {\r
      continue;\r
    }\r
\r
    if (Prev == NULL) {\r
      //\r
      // Qh is the first entry in the frame\r
      //\r
      ((UINT32*)Ehc->PeriodFrame)[Index] = Qh->QhHw.HorizonLink;\r
      ((UINTN*)Ehc->PeriodFrameHost)[Index] = (UINTN)Qh->NextQh;\r
    } else {\r
      Prev->NextQh            = Qh->NextQh;\r
      Prev->QhHw.HorizonLink  = Qh->QhHw.HorizonLink;\r
    }\r
  }\r
}\r
\r
\r
/**\r
  Check the URB's execution result and update the URB's\r
  result accordingly.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Urb                   The URB to check result.\r
\r
  @return Whether the result of URB transfer is finialized.\r
\r
**/\r
BOOLEAN\r
EhcCheckUrbResult (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  URB                 *Urb\r
  )\r
{\r
  LIST_ENTRY              *Entry;\r
  EHC_QTD                 *Qtd;\r
  QTD_HW                  *QtdHw;\r
  UINT8                   State;\r
  BOOLEAN                 Finished;\r
  EFI_PHYSICAL_ADDRESS    PciAddr;\r
\r
  ASSERT ((Ehc != NULL) && (Urb != NULL) && (Urb->Qh != NULL));\r
\r
  Finished        = TRUE;\r
  Urb->Completed  = 0;\r
\r
  Urb->Result     = EFI_USB_NOERROR;\r
\r
  if (EhcIsHalt (Ehc) || EhcIsSysError (Ehc)) {\r
    Urb->Result |= EFI_USB_ERR_SYSTEM;\r
    goto ON_EXIT;\r
  }\r
\r
  EFI_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {\r
    Qtd   = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);\r
    QtdHw = &Qtd->QtdHw;\r
    State = (UINT8) QtdHw->Status;\r
\r
    if (EHC_BIT_IS_SET (State, QTD_STAT_HALTED)) {\r
      //\r
      // EHCI will halt the queue head when met some error.\r
      // If it is halted, the result of URB is finialized.\r
      //\r
      if ((State & QTD_STAT_ERR_MASK) == 0) {\r
        Urb->Result |= EFI_USB_ERR_STALL;\r
      }\r
\r
      if (EHC_BIT_IS_SET (State, QTD_STAT_BABBLE_ERR)) {\r
        Urb->Result |= EFI_USB_ERR_BABBLE;\r
      }\r
\r
      if (EHC_BIT_IS_SET (State, QTD_STAT_BUFF_ERR)) {\r
        Urb->Result |= EFI_USB_ERR_BUFFER;\r
      }\r
\r
      if (EHC_BIT_IS_SET (State, QTD_STAT_TRANS_ERR) && (QtdHw->ErrCnt == 0)) {\r
        Urb->Result |= EFI_USB_ERR_TIMEOUT;\r
      }\r
\r
      Finished = TRUE;\r
      goto ON_EXIT;\r
\r
    } else if (EHC_BIT_IS_SET (State, QTD_STAT_ACTIVE)) {\r
      //\r
      // The QTD is still active, no need to check furthur.\r
      //\r
      Urb->Result |= EFI_USB_ERR_NOTEXECUTE;\r
\r
      Finished = FALSE;\r
      goto ON_EXIT;\r
\r
    } else {\r
      //\r
      // This QTD is finished OK or met short packet read. Update the\r
      // transfer length if it isn't a setup.\r
      //\r
      if (QtdHw->Pid != QTD_PID_SETUP) {\r
        Urb->Completed += Qtd->DataLen - QtdHw->TotalBytes;\r
      }\r
\r
      if ((QtdHw->TotalBytes != 0) && (QtdHw->Pid == QTD_PID_INPUT)) {\r
        EhcDumpQh (Urb->Qh, "Short packet read", FALSE);\r
\r
        //\r
        // Short packet read condition. If it isn't a setup transfer,\r
        // no need to check furthur: the queue head will halt at the\r
        // ShortReadStop. If it is a setup transfer, need to check the\r
        // Status Stage of the setup transfer to get the finial result\r
        //\r
        PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, Ehc->ShortReadStop, sizeof (EHC_QTD));\r
        if (QtdHw->AltNext == QTD_LINK (PciAddr, FALSE)) {\r
          DEBUG ((EFI_D_INFO, "EhcCheckUrbResult: Short packet read, break\n"));\r
\r
          Finished = TRUE;\r
          goto ON_EXIT;\r
        }\r
\r
        DEBUG ((EFI_D_INFO, "EhcCheckUrbResult: Short packet read, continue\n"));\r
      }\r
    }\r
  }\r
\r
ON_EXIT:\r
  //\r
  // Return the data toggle set by EHCI hardware, bulk and interrupt\r
  // transfer will use this to initialize the next transaction. For\r
  // Control transfer, it always start a new data toggle sequence for\r
  // new transfer.\r
  //\r
  // NOTICE: don't move DT update before the loop, otherwise there is\r
  // a race condition that DT is wrong.\r
  //\r
  Urb->DataToggle = (UINT8) Urb->Qh->QhHw.DataToggle;\r
\r
  return Finished;\r
}\r
\r
\r
/**\r
  Execute the transfer by polling the URB. This is a synchronous operation.\r
\r
  @param  Ehc               The EHCI device.\r
  @param  Urb               The URB to execute.\r
  @param  TimeOut           The time to wait before abort, in millisecond.\r
\r
  @return EFI_DEVICE_ERROR  The transfer failed due to transfer error.\r
  @return EFI_TIMEOUT       The transfer failed due to time out.\r
  @return EFI_SUCCESS       The transfer finished OK.\r
\r
**/\r
EFI_STATUS\r
EhcExecTransfer (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  URB                 *Urb,\r
  IN  UINTN               TimeOut\r
  )\r
{\r
  EFI_STATUS              Status;\r
  UINTN                   Index;\r
  UINTN                   Loop;\r
  BOOLEAN                 Finished;\r
\r
  Status    = EFI_SUCCESS;\r
  Loop      = (TimeOut * EHC_1_MILLISECOND / EHC_SYNC_POLL_INTERVAL) + 1;\r
  Finished  = FALSE;\r
\r
  for (Index = 0; Index < Loop; Index++) {\r
    Finished = EhcCheckUrbResult (Ehc, Urb);\r
\r
    if (Finished) {\r
      break;\r
    }\r
\r
    gBS->Stall (EHC_SYNC_POLL_INTERVAL);\r
  }\r
\r
  if (!Finished) {\r
    DEBUG ((EFI_D_ERROR, "EhcExecTransfer: transfer not finished in %dms\n", (UINT32)TimeOut));\r
    EhcDumpQh (Urb->Qh, NULL, FALSE);\r
\r
    Status = EFI_TIMEOUT;\r
\r
  } else if (Urb->Result != EFI_USB_NOERROR) {\r
    DEBUG ((EFI_D_ERROR, "EhcExecTransfer: transfer failed with %x\n", Urb->Result));\r
    EhcDumpQh (Urb->Qh, NULL, FALSE);\r
\r
    Status = EFI_DEVICE_ERROR;\r
  }\r
\r
  return Status;\r
}\r
\r
\r
/**\r
  Delete a single asynchronous interrupt transfer for\r
  the device and endpoint.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  DevAddr               The address of the target device.\r
  @param  EpNum                 The endpoint of the target.\r
  @param  DataToggle            Return the next data toggle to use.\r
\r
  @retval EFI_SUCCESS           An asynchronous transfer is removed.\r
  @retval EFI_NOT_FOUND         No transfer for the device is found.\r
\r
**/\r
EFI_STATUS\r
EhciDelAsyncIntTransfer (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  UINT8               DevAddr,\r
  IN  UINT8               EpNum,\r
  OUT UINT8               *DataToggle\r
  )\r
{\r
  LIST_ENTRY              *Entry;\r
  LIST_ENTRY              *Next;\r
  URB                     *Urb;\r
  EFI_USB_DATA_DIRECTION  Direction;\r
\r
  Direction = (((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut);\r
  EpNum    &= 0x0F;\r
\r
  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
    Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
\r
    if ((Urb->Ep.DevAddr == DevAddr) && (Urb->Ep.EpAddr == EpNum) &&\r
        (Urb->Ep.Direction == Direction)) {\r
      //\r
      // Check the URB status to retrieve the next data toggle\r
      // from the associated queue head.\r
      //\r
      EhcCheckUrbResult (Ehc, Urb);\r
      *DataToggle = Urb->DataToggle;\r
\r
      EhcUnlinkQhFromPeriod (Ehc, Urb->Qh);\r
      RemoveEntryList (&Urb->UrbList);\r
\r
      gBS->FreePool (Urb->Data);\r
      EhcFreeUrb (Ehc, Urb);\r
      return EFI_SUCCESS;\r
    }\r
  }\r
\r
  return EFI_NOT_FOUND;\r
}\r
\r
\r
/**\r
  Remove all the asynchronous interrutp transfers.\r
\r
  @param  Ehc                   The EHCI device.\r
\r
**/\r
VOID\r
EhciDelAllAsyncIntTransfers (\r
  IN USB2_HC_DEV          *Ehc\r
  )\r
{\r
  LIST_ENTRY              *Entry;\r
  LIST_ENTRY              *Next;\r
  URB                     *Urb;\r
\r
  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
    Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
\r
    EhcUnlinkQhFromPeriod (Ehc, Urb->Qh);\r
    RemoveEntryList (&Urb->UrbList);\r
\r
    gBS->FreePool (Urb->Data);\r
    EhcFreeUrb (Ehc, Urb);\r
  }\r
}\r
\r
\r
/**\r
  Flush data from PCI controller specific address to mapped system\r
  memory address.\r
\r
  @param  Ehc                The EHCI device.\r
  @param  Urb                The URB to unmap.\r
\r
  @retval EFI_SUCCESS        Success to flush data to mapped system memory.\r
  @retval EFI_DEVICE_ERROR   Fail to flush data to mapped system memory.\r
\r
**/\r
EFI_STATUS\r
EhcFlushAsyncIntMap (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN  URB                 *Urb\r
  )\r
{\r
  EFI_STATUS                    Status;\r
  EFI_PHYSICAL_ADDRESS          PhyAddr;\r
  EFI_PCI_IO_PROTOCOL_OPERATION MapOp;\r
  EFI_PCI_IO_PROTOCOL           *PciIo;\r
  UINTN                         Len;\r
  VOID                          *Map;\r
\r
  PciIo = Ehc->PciIo;\r
  Len   = Urb->DataLen;\r
\r
  if (Urb->Ep.Direction == EfiUsbDataIn) {\r
    MapOp = EfiPciIoOperationBusMasterWrite;\r
  } else {\r
    MapOp = EfiPciIoOperationBusMasterRead;\r
  }\r
\r
  Status = PciIo->Unmap (PciIo, Urb->DataMap);\r
  if (EFI_ERROR (Status)) {\r
    goto ON_ERROR;\r
  }\r
\r
  Urb->DataMap = NULL;\r
\r
  Status = PciIo->Map (PciIo, MapOp, Urb->Data, &Len, &PhyAddr, &Map);\r
  if (EFI_ERROR (Status) || (Len != Urb->DataLen)) {\r
    goto ON_ERROR;\r
  }\r
\r
  Urb->DataPhy  = (VOID *) ((UINTN) PhyAddr);\r
  Urb->DataMap  = Map;\r
  return EFI_SUCCESS;\r
\r
ON_ERROR:\r
  return EFI_DEVICE_ERROR;\r
}\r
\r
\r
/**\r
  Update the queue head for next round of asynchronous transfer.\r
\r
  @param  Ehc                   The EHCI device.\r
  @param  Urb                   The URB to update.\r
\r
**/\r
VOID\r
EhcUpdateAsyncRequest (\r
  IN  USB2_HC_DEV         *Ehc,\r
  IN URB                  *Urb\r
  )\r
{\r
  LIST_ENTRY              *Entry;\r
  EHC_QTD                 *FirstQtd;\r
  QH_HW                   *QhHw;\r
  EHC_QTD                 *Qtd;\r
  QTD_HW                  *QtdHw;\r
  UINTN                   Index;\r
  EFI_PHYSICAL_ADDRESS    PciAddr;\r
\r
  Qtd = NULL;\r
\r
  if (Urb->Result == EFI_USB_NOERROR) {\r
    FirstQtd = NULL;\r
\r
    EFI_LIST_FOR_EACH (Entry, &Urb->Qh->Qtds) {\r
      Qtd = EFI_LIST_CONTAINER (Entry, EHC_QTD, QtdList);\r
\r
      if (FirstQtd == NULL) {\r
        FirstQtd = Qtd;\r
      }\r
\r
      //\r
      // Update the QTD for next round of transfer. Host control\r
      // may change dt/Total Bytes to Transfer/C_Page/Cerr/Status/\r
      // Current Offset. These fields need to be updated. DT isn't\r
      // used by interrupt transfer. It uses DT in queue head.\r
      // Current Offset is in Page[0], only need to reset Page[0]\r
      // to initial data buffer.\r
      //\r
      QtdHw             = &Qtd->QtdHw;\r
      QtdHw->Status     = QTD_STAT_ACTIVE;\r
      QtdHw->ErrCnt     = QTD_MAX_ERR;\r
      QtdHw->CurPage    = 0;\r
      QtdHw->TotalBytes = (UINT32) Qtd->DataLen;\r
      QtdHw->Page[0]    = EHC_LOW_32BIT (Qtd->Data);\r
    }\r
\r
    //\r
    // Update QH for next round of transfer. Host control only\r
    // touch the fields in transfer overlay area. Only need to\r
    // zero out the overlay area and set NextQtd to the first\r
    // QTD. DateToggle bit is left untouched.\r
    //\r
    QhHw              = &Urb->Qh->QhHw;\r
    QhHw->CurQtd      = QTD_LINK (0, TRUE);\r
    QhHw->AltQtd      = 0;\r
\r
    QhHw->Status      = 0;\r
    QhHw->Pid         = 0;\r
    QhHw->ErrCnt      = 0;\r
    QhHw->CurPage     = 0;\r
    QhHw->Ioc         = 0;\r
    QhHw->TotalBytes  = 0;\r
\r
    for (Index = 0; Index < 5; Index++) {\r
      QhHw->Page[Index]     = 0;\r
      QhHw->PageHigh[Index] = 0;\r
    }\r
\r
    PciAddr = UsbHcGetPciAddressForHostMem (Ehc->MemPool, FirstQtd, sizeof (EHC_QTD));\r
    QhHw->NextQtd = QTD_LINK (PciAddr, FALSE);\r
  }\r
\r
  return ;\r
}\r
\r
\r
/**\r
  Interrupt transfer periodic check handler.\r
\r
  @param  Event                 Interrupt event.\r
  @param  Context               Pointer to USB2_HC_DEV.\r
\r
**/\r
VOID\r
EFIAPI\r
EhcMonitorAsyncRequests (\r
  IN EFI_EVENT            Event,\r
  IN VOID                 *Context\r
  )\r
{\r
  USB2_HC_DEV             *Ehc;\r
  EFI_TPL                 OldTpl;\r
  LIST_ENTRY              *Entry;\r
  LIST_ENTRY              *Next;\r
  BOOLEAN                 Finished;\r
  UINT8                   *ProcBuf;\r
  URB                     *Urb;\r
  EFI_STATUS              Status;\r
\r
  OldTpl  = gBS->RaiseTPL (EHC_TPL);\r
  Ehc     = (USB2_HC_DEV *) Context;\r
\r
  EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Ehc->AsyncIntTransfers) {\r
    Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r
\r
    //\r
    // Check the result of URB execution. If it is still\r
    // active, check the next one.\r
    //\r
    Finished = EhcCheckUrbResult (Ehc, Urb);\r
\r
    if (!Finished) {\r
      continue;\r
    }\r
\r
    //\r
    // Flush any PCI posted write transactions from a PCI host\r
    // bridge to system memory.\r
    //\r
    Status = EhcFlushAsyncIntMap (Ehc, Urb);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((EFI_D_ERROR, "EhcMonitorAsyncRequests: Fail to Flush AsyncInt Mapped Memeory\n"));\r
    }\r
\r
    //\r
    // Allocate a buffer then copy the transferred data for user.\r
    // If failed to allocate the buffer, update the URB for next\r
    // round of transfer. Ignore the data of this round.\r
    //\r
    ProcBuf = NULL;\r
\r
    if (Urb->Result == EFI_USB_NOERROR) {\r
      ASSERT (Urb->Completed <= Urb->DataLen);\r
\r
      ProcBuf = AllocatePool (Urb->Completed);\r
\r
      if (ProcBuf == NULL) {\r
        EhcUpdateAsyncRequest (Ehc, Urb);\r
        continue;\r
      }\r
\r
      CopyMem (ProcBuf, Urb->Data, Urb->Completed);\r
    }\r
\r
    EhcUpdateAsyncRequest (Ehc, Urb);\r
\r
    //\r
    // Leave error recovery to its related device driver. A\r
    // common case of the error recovery is to re-submit the\r
    // interrupt transfer which is linked to the head of the\r
    // list. This function scans from head to tail. So the\r
    // re-submitted interrupt transfer's callback function\r
    // will not be called again in this round. Don't touch this\r
    // URB after the callback, it may have been removed by the\r
    // callback.\r
    //\r
    if (Urb->Callback != NULL) {\r
      //\r
      // Restore the old TPL, USB bus maybe connect device in\r
      // his callback. Some drivers may has a lower TPL restriction.\r
      //\r
      gBS->RestoreTPL (OldTpl);\r
      (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r
      OldTpl = gBS->RaiseTPL (EHC_TPL);\r
    }\r
\r
    if (ProcBuf != NULL) {\r
      FreePool (ProcBuf);\r
    }\r
  }\r
\r
  gBS->RestoreTPL (OldTpl);\r
}\r