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913cb9dc | 1 | /** @file\r |
2 | \r | |
78c2ffb5 | 3 | This file contains the definination for host controller memory management routines.\r |
4 | \r | |
cd5ebaa0 HT |
5 | Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r |
6 | This program and the accompanying materials\r | |
913cb9dc | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
16 | #ifndef _EFI_EHCI_MEM_H_\r | |
17 | #define _EFI_EHCI_MEM_H_\r | |
18 | \r | |
913cb9dc | 19 | #define USB_HC_BIT(a) ((UINTN)(1 << (a)))\r |
20 | \r | |
21 | #define USB_HC_BIT_IS_SET(Data, Bit) \\r | |
22 | ((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit)))\r | |
23 | \r | |
24 | #define USB_HC_HIGH_32BIT(Addr64) \\r | |
25 | ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r | |
26 | \r | |
1ccdbf2a | 27 | typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK;\r |
28 | struct _USBHC_MEM_BLOCK {\r | |
913cb9dc | 29 | UINT8 *Bits; // Bit array to record which unit is allocated\r |
30 | UINTN BitsLen;\r | |
31 | UINT8 *Buf;\r | |
32 | UINT8 *BufHost;\r | |
33 | UINTN BufLen; // Memory size in bytes\r | |
34 | VOID *Mapping;\r | |
1ccdbf2a | 35 | USBHC_MEM_BLOCK *Next;\r |
36 | };\r | |
913cb9dc | 37 | \r |
38 | //\r | |
39 | // USBHC_MEM_POOL is used to manage the memory used by USB\r | |
40 | // host controller. EHCI requires the control memory and transfer\r | |
41 | // data to be on the same 4G memory.\r | |
42 | //\r | |
43 | typedef struct _USBHC_MEM_POOL {\r | |
44 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
45 | BOOLEAN Check4G;\r | |
46 | UINT32 Which4G;\r | |
47 | USBHC_MEM_BLOCK *Head;\r | |
48 | } USBHC_MEM_POOL;\r | |
49 | \r | |
1ccdbf2a | 50 | //\r |
51 | // Memory allocation unit, must be 2^n, n>4\r | |
52 | //\r | |
53 | #define USBHC_MEM_UNIT 64\r | |
913cb9dc | 54 | \r |
1ccdbf2a | 55 | #define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1)\r |
56 | #define USBHC_MEM_DEFAULT_PAGES 16\r | |
913cb9dc | 57 | \r |
58 | #define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK))\r | |
59 | \r | |
60 | //\r | |
61 | // Advance the byte and bit to the next bit, adjust byte accordingly.\r | |
62 | //\r | |
63 | #define NEXT_BIT(Byte, Bit) \\r | |
64 | do { \\r | |
65 | (Bit)++; \\r | |
66 | if ((Bit) > 7) { \\r | |
67 | (Byte)++; \\r | |
68 | (Bit) = 0; \\r | |
69 | } \\r | |
70 | } while (0)\r | |
71 | \r | |
72 | \r | |
73 | \r | |
78c2ffb5 | 74 | /**\r |
75 | Initialize the memory management pool for the host controller.\r | |
76 | \r | |
77 | @param PciIo The PciIo that can be used to access the host controller.\r | |
78 | @param Check4G Whether the host controller requires allocated memory\r | |
79 | from one 4G address space.\r | |
80 | @param Which4G The 4G memory area each memory allocated should be from.\r | |
81 | \r | |
82 | @retval EFI_SUCCESS The memory pool is initialized.\r | |
83 | @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool.\r | |
84 | \r | |
85 | **/\r | |
913cb9dc | 86 | USBHC_MEM_POOL *\r |
87 | UsbHcInitMemPool (\r | |
88 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
89 | IN BOOLEAN Check4G,\r | |
90 | IN UINT32 Which4G\r | |
ed66e1bc | 91 | );\r |
913cb9dc | 92 | \r |
93 | \r | |
913cb9dc | 94 | /**\r |
78c2ffb5 | 95 | Release the memory management pool.\r |
913cb9dc | 96 | \r |
78c2ffb5 | 97 | @param Pool The USB memory pool to free.\r |
913cb9dc | 98 | \r |
78c2ffb5 | 99 | @retval EFI_SUCCESS The memory pool is freed.\r |
100 | @retval EFI_DEVICE_ERROR Failed to free the memory pool.\r | |
913cb9dc | 101 | \r |
102 | **/\r | |
103 | EFI_STATUS\r | |
104 | UsbHcFreeMemPool (\r | |
105 | IN USBHC_MEM_POOL *Pool\r | |
ed66e1bc | 106 | );\r |
913cb9dc | 107 | \r |
108 | \r | |
913cb9dc | 109 | /**\r |
110 | Allocate some memory from the host controller's memory pool\r | |
111 | which can be used to communicate with host controller.\r | |
112 | \r | |
78c2ffb5 | 113 | @param Pool The host controller's memory pool.\r |
114 | @param Size Size of the memory to allocate.\r | |
913cb9dc | 115 | \r |
78c2ffb5 | 116 | @return The allocated memory or NULL.\r |
913cb9dc | 117 | \r |
118 | **/\r | |
119 | VOID *\r | |
120 | UsbHcAllocateMem (\r | |
121 | IN USBHC_MEM_POOL *Pool,\r | |
122 | IN UINTN Size\r | |
ed66e1bc | 123 | );\r |
913cb9dc | 124 | \r |
125 | \r | |
913cb9dc | 126 | /**\r |
78c2ffb5 | 127 | Free the allocated memory back to the memory pool.\r |
913cb9dc | 128 | \r |
78c2ffb5 | 129 | @param Pool The memory pool of the host controller.\r |
130 | @param Mem The memory to free.\r | |
131 | @param Size The size of the memory to free.\r | |
913cb9dc | 132 | \r |
913cb9dc | 133 | **/\r |
134 | VOID\r | |
135 | UsbHcFreeMem (\r | |
136 | IN USBHC_MEM_POOL *Pool,\r | |
137 | IN VOID *Mem,\r | |
138 | IN UINTN Size\r | |
ed66e1bc | 139 | );\r |
739802e4 | 140 | \r |
141 | /**\r | |
592b87a4 | 142 | Calculate the corresponding pci bus address according to the Mem parameter.\r |
739802e4 | 143 | \r |
144 | @param Pool The memory pool of the host controller.\r | |
592b87a4 | 145 | @param Mem The pointer to host memory.\r |
146 | @param Size The size of the memory region.\r | |
739802e4 | 147 | \r |
148 | @return the pci memory address\r | |
149 | **/\r | |
150 | EFI_PHYSICAL_ADDRESS\r | |
151 | UsbHcGetPciAddressForHostMem (\r | |
152 | IN USBHC_MEM_POOL *Pool,\r | |
153 | IN VOID *Mem,\r | |
154 | IN UINTN Size\r | |
155 | );\r | |
156 | \r | |
913cb9dc | 157 | #endif\r |