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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressPassthru.c
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eb290d02
FT		 1/** @file\r
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r
3 NVM Express specification.\r
4\r
5 Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
6 This program and the accompanying materials\r
7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include "NvmExpress.h"\r
17\r
18//\r
19// Page size should be set in the Controller Configuration register\r
20// during controller init, and the controller configuration save in\r
21// the controller's private data. The Max and Min supported page sizes\r
22// for the controller are specified in the Controller Capabilities register.\r
23//\r
24\r
25GLOBAL_REMOVE_IF_UNREFERENCED NVM_EXPRESS_PASS_THRU_MODE gNvmExpressPassThruMode = {\r
26 0,\r
27 NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL | NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVME,\r
28 sizeof (UINTN),\r
29 0x10000,\r
30 0,\r
31 0\r
32};\r
33\r
34\r
35/**\r
36 Dump the execution status from a given completion queue entry.\r
37\r
38 @param[in] Cq A pointer to the NVME_CQ item.\r
39\r
40**/\r
41VOID\r
42NvmeDumpStatus (\r
43 IN NVME_CQ *Cq\r
44 )\r
45{\r
46 DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r
47\r
48 DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r
49\r
50 DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r
51\r
52 switch (Cq->Sct) {\r
53 case 0x0:\r
54 switch (Cq->Sc) {\r
55 case 0x0:\r
56 DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r
57 break;\r
58 case 0x1:\r
59 DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r
60 break;\r
61 case 0x2:\r
62 DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r
63 break;\r
64 case 0x3:\r
65 DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r
66 break;\r
67 case 0x4:\r
68 DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r
69 break;\r
70 case 0x5:\r
71 DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r
72 break;\r
73 case 0x6:\r
74 DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r
75 break;\r
76 case 0x7:\r
77 DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r
78 break;\r
79 case 0x8:\r
80 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r
81 break;\r
82 case 0x9:\r
83 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r
84 break;\r
85 case 0xA:\r
86 DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r
87 break;\r
88 case 0xB:\r
89 DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r
90 break;\r
91 case 0xC:\r
92 DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r
93 break;\r
94 case 0xD:\r
95 DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r
96 break;\r
97 case 0xE:\r
98 DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r
99 break;\r
100 case 0xF:\r
101 DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r
102 break;\r
103 case 0x10:\r
104 DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r
105 break;\r
106 case 0x11:\r
107 DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r
108 break;\r
109 case 0x80:\r
110 DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r
111 break;\r
112 case 0x81:\r
113 DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r
114 break;\r
115 case 0x82:\r
116 DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r
117 break;\r
118 case 0x83:\r
119 DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r
120 break;\r
121 }\r
122 break;\r
123\r
124 case 0x1:\r
125 switch (Cq->Sc) {\r
126 case 0x0:\r
127 DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r
128 break;\r
129 case 0x1:\r
130 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r
131 break;\r
132 case 0x2:\r
133 DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r
134 break;\r
135 case 0x3:\r
136 DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r
137 break;\r
138 case 0x5:\r
139 DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r
140 break;\r
141 case 0x6:\r
142 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r
143 break;\r
144 case 0x7:\r
145 DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r
146 break;\r
147 case 0x8:\r
148 DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r
149 break;\r
150 case 0x9:\r
151 DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r
152 break;\r
153 case 0xA:\r
154 DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r
155 break;\r
156 case 0xB:\r
157 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r
158 break;\r
159 case 0xC:\r
160 DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r
161 break;\r
162 case 0xD:\r
163 DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r
164 break;\r
165 case 0xE:\r
166 DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r
167 break;\r
168 case 0xF:\r
169 DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r
170 break;\r
171 case 0x10:\r
172 DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r
173 break;\r
174 case 0x80:\r
175 DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r
176 break;\r
177 case 0x81:\r
178 DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r
179 break;\r
180 case 0x82:\r
181 DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r
182 break;\r
183 }\r
184 break;\r
185\r
186 case 0x2:\r
187 switch (Cq->Sc) {\r
188 case 0x80:\r
189 DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r
190 break;\r
191 case 0x81:\r
192 DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r
193 break;\r
194 case 0x82:\r
195 DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r
196 break;\r
197 case 0x83:\r
198 DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r
199 break;\r
200 case 0x84:\r
201 DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r
202 break;\r
203 case 0x85:\r
204 DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r
205 break;\r
206 case 0x86:\r
207 DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r
208 break;\r
209 }\r
210 break;\r
211\r
212 default:\r
213 break;\r
214 }\r
215}\r
216\r
217/**\r
218 Create PRP lists for data transfer which is larger than 2 memory pages.\r
219 Note here we calcuate the number of required PRP lists and allocate them at one time.\r
220\r
221 @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
222 @param[in] PhysicalAddr The physical base address of data buffer.\r
223 @param[in] Pages The number of pages to be transfered.\r
224 @param[out] PrpListHost The host base address of PRP lists.\r
225 @param[in,out] PrpListNo The number of PRP List.\r
226 @param[out] Mapping The mapping value returned from PciIo.Map().\r
227\r
228 @retval The pointer to the first PRP List of the PRP lists.\r
229\r
230**/\r
231VOID*\r
232NvmeCreatePrpList (\r
233 IN EFI_PCI_IO_PROTOCOL *PciIo,\r
234 IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r
235 IN UINTN Pages,\r
236 OUT VOID **PrpListHost,\r
237 IN OUT UINTN *PrpListNo,\r
238 OUT VOID **Mapping\r
239 )\r
240{\r
241 UINTN PrpEntryNo;\r
242 UINT64 PrpListBase;\r
243 UINTN PrpListIndex;\r
244 UINTN PrpEntryIndex;\r
245 UINT64 Remainder;\r
246 EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r
247 UINTN Bytes;\r
248 EFI_STATUS Status;\r
249\r
250 //\r
251 // The number of Prp Entry in a memory page.\r
252 //\r
253 PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r
254\r
255 //\r
256 // Calculate total PrpList number.\r
257 //\r
258 *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo, &Remainder);\r
259 if (Remainder != 0) {\r
260 *PrpListNo += 1;\r
261 }\r
262\r
263 Status = PciIo->AllocateBuffer (\r
264 PciIo,\r
265 AllocateAnyPages,\r
266 EfiBootServicesData,\r
267 *PrpListNo,\r
268 PrpListHost,\r
269 0\r
270 );\r
271\r
272 if (EFI_ERROR (Status)) {\r
273 return NULL;\r
274 }\r
275\r
276 Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r
277 Status = PciIo->Map (\r
278 PciIo,\r
279 EfiPciIoOperationBusMasterCommonBuffer,\r
280 *PrpListHost,\r
281 &Bytes,\r
282 &PrpListPhyAddr,\r
283 Mapping\r
284 );\r
285\r
286 if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r
287 DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r
288 goto EXIT;\r
289 }\r
290 //\r
291 // Fill all PRP lists except of last one.\r
292 //\r
293 ZeroMem (*PrpListHost, Bytes);\r
294 for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r
295 PrpListBase = *(UINT8*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
296\r
297 for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r
298 if (PrpEntryIndex != PrpEntryNo - 1) {\r
299 //\r
300 // Fill all PRP entries except of last one.\r
301 //\r
302 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
303 PhysicalAddr += EFI_PAGE_SIZE;\r
304 } else {\r
305 //\r
306 // Fill last PRP entries with next PRP List pointer.\r
307 //\r
308 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r
309 }\r
310 }\r
311 }\r
312 //\r
313 // Fill last PRP list.\r
314 //\r
315 PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r
316 for (PrpEntryIndex = 0; PrpEntryIndex < ((Remainder != 0) ? Remainder : PrpEntryNo); ++PrpEntryIndex) {\r
317 *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r
318 PhysicalAddr += EFI_PAGE_SIZE;\r
319 }\r
320\r
321 return (VOID*)(UINTN)PrpListPhyAddr;\r
322\r
323EXIT:\r
324 PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r
325 return NULL;\r
326}\r
327\r
328\r
329/**\r
330 Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
331 both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking\r
332 I/O functionality is optional.\r
333\r
334 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
335 @param[in] NamespaceId Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.\r
336 A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace\r
337 ID specifies that the command packet should be sent to all valid namespaces.\r
338 @param[in] NamespaceUuid Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.\r
339 A value of 0 denotes the NVM Express controller, a value of all 0FFh in the namespace\r
340 UUID specifies that the command packet should be sent to all valid namespaces.\r
341 @param[in,out] Packet A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified\r
342 by NamespaceId.\r
343 @param[in] Event If nonblocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r
344 If Event is NULL, then blocking I/O is performed. If Event is not NULL and non blocking I/O\r
345 is supported, then nonblocking I/O is performed, and Event will be signaled when the NVM\r
346 Express Command Packet completes.\r
347\r
348 @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r
349 to, or from DataBuffer.\r
350 @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r
351 is returned in TransferLength.\r
352 @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r
353 may retry again later.\r
354 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r
355 @retval EFI_INVALID_PARAMETER Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r
356 Express Command Packet was not sent, so no additional status information is available.\r
357 @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the host adapter.\r
358 The NVM Express Command Packet was not sent, so no additional status information is available.\r
359 @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r
360\r
361**/\r
362EFI_STATUS\r
363EFIAPI\r
364NvmExpressPassThru (\r
365 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
366 IN UINT32 NamespaceId,\r
367 IN UINT64 NamespaceUuid,\r
368 IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r
369 IN EFI_EVENT Event OPTIONAL\r
370 )\r
371{\r
372 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
373 EFI_STATUS Status;\r
374 EFI_PCI_IO_PROTOCOL *PciIo;\r
375 NVME_SQ *Sq;\r
376 NVME_CQ *Cq;\r
377 UINT8 Qid;\r
378 UINT32 Bytes;\r
379 UINT16 Offset;\r
380 EFI_EVENT TimerEvent;\r
381 EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r
382 EFI_PHYSICAL_ADDRESS PhyAddr;\r
383 VOID *MapData;\r
384 VOID *MapMeta;\r
385 VOID *MapPrpList;\r
386 UINTN MapLength;\r
387 UINT64 *Prp;\r
388 VOID *PrpListHost;\r
389 UINTN PrpListNo;\r
7b8883c6 390 UINT32 Data;\r
eb290d02
FT		 391\r
392 //\r
393 // check the data fields in Packet parameter.\r
394 //\r
395 if ((This == NULL) || (Packet == NULL)) {\r
396 return EFI_INVALID_PARAMETER;\r
397 }\r
398\r
399 if ((Packet->NvmeCmd == NULL) || (Packet->NvmeResponse == NULL)) {\r
400 return EFI_INVALID_PARAMETER;\r
401 }\r
402\r
403 if (Packet->QueueId != NVME_ADMIN_QUEUE && Packet->QueueId != NVME_IO_QUEUE) {\r
404 return EFI_INVALID_PARAMETER;\r
405 }\r
406\r
407 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
408 PciIo = Private->PciIo;\r
409 MapData = NULL;\r
410 MapMeta = NULL;\r
411 MapPrpList = NULL;\r
412 PrpListHost = NULL;\r
413 PrpListNo = 0;\r
414 Prp = NULL;\r
415 TimerEvent = NULL;\r
416 Status = EFI_SUCCESS;\r
417\r
418 Qid = Packet->QueueId;\r
419 Sq = Private->SqBuffer[Qid] + Private->SqTdbl[Qid].Sqt;\r
420 Cq = Private->CqBuffer[Qid] + Private->CqHdbl[Qid].Cqh;\r
421\r
422 if (Packet->NvmeCmd->Nsid != NamespaceId) {\r
423 return EFI_INVALID_PARAMETER;\r
424 }\r
425\r
426 ZeroMem (Sq, sizeof (NVME_SQ));\r
427 Sq->Opc = Packet->NvmeCmd->Cdw0.Opcode;\r
428 Sq->Fuse = Packet->NvmeCmd->Cdw0.FusedOperation;\r
429 Sq->Cid = Packet->NvmeCmd->Cdw0.Cid;\r
430 Sq->Nsid = Packet->NvmeCmd->Nsid;\r
431\r
432 //\r
433 // Currently we only support PRP for data transfer, SGL is NOT supported.\r
434 //\r
7b8883c6
FT		 435 ASSERT (Sq->Psdt == 0);\r
436 if (Sq->Psdt != 0) {\r
eb290d02
FT		 437 DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r
438 return EFI_UNSUPPORTED;\r
439 }\r
440\r
441 Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r
442 //\r
443 // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r
444 // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r
445 // these two cmds are special which requires their data buffer must support simultaneous access by both the\r
446 // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r
447 //\r
448 if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {\r
449 if ((Sq->Opc & BIT0) != 0) {\r
450 Flag = EfiPciIoOperationBusMasterRead;\r
451 } else {\r
452 Flag = EfiPciIoOperationBusMasterWrite;\r
453 }\r
454\r
455 MapLength = Packet->TransferLength;\r
456 Status = PciIo->Map (\r
457 PciIo,\r
458 Flag,\r
459 Packet->TransferBuffer,\r
460 &MapLength,\r
461 &PhyAddr,\r
462 &MapData\r
463 );\r
464 if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r
465 return EFI_OUT_OF_RESOURCES;\r
466 }\r
467\r
468 Sq->Prp[0] = PhyAddr;\r
469 Sq->Prp[1] = 0;\r
470\r
471 MapLength = Packet->MetadataLength;\r
472 if(Packet->MetadataBuffer != NULL) {\r
473 MapLength = Packet->MetadataLength;\r
474 Status = PciIo->Map (\r
475 PciIo,\r
476 Flag,\r
477 Packet->MetadataBuffer,\r
478 &MapLength,\r
479 &PhyAddr,\r
480 &MapMeta\r
481 );\r
482 if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r
483 PciIo->Unmap (\r
484 PciIo,\r
485 MapData\r
486 );\r
487\r
488 return EFI_OUT_OF_RESOURCES;\r
489 }\r
490 Sq->Mptr = PhyAddr;\r
491 }\r
492 }\r
493 //\r
494 // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r
495 // then build a PRP list in the second PRP submission queue entry.\r
496 //\r
497 Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r
498 Bytes = Packet->TransferLength;\r
499\r
500 if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r
501 //\r
502 // Create PrpList for remaining data buffer.\r
503 //\r
504 PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
505 Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r
506 if (Prp == NULL) {\r
507 goto EXIT;\r
508 }\r
509\r
510 Sq->Prp[1] = (UINT64)(UINTN)Prp;\r
511 } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r
512 Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r
513 }\r
514\r
515 if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r
516 Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r
517 }\r
518 if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r
519 Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r
520 }\r
521 if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r
522 Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r
523 }\r
524 if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r
525 Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r
526 }\r
527 if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r
528 Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r
529 }\r
530 if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r
531 Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r
532 }\r
533\r
534 //\r
535 // Ring the submission queue doorbell.\r
536 //\r
537 Private->SqTdbl[Qid].Sqt ^= 1;\r
7b8883c6 538 Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[Qid]);\r
eb290d02
FT		 539 PciIo->Mem.Write (\r
540 PciIo,\r
541 EfiPciIoWidthUint32,\r
542 NVME_BAR,\r
543 NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd),\r
544 1,\r
7b8883c6 545 &Data\r
eb290d02
FT		 546 );\r
547\r
548 Status = gBS->CreateEvent (\r
549 EVT_TIMER,\r
550 TPL_CALLBACK,\r
551 NULL,\r
552 NULL,\r
553 &TimerEvent\r
554 );\r
555 if (EFI_ERROR (Status)) {\r
556 goto EXIT;\r
557 }\r
558\r
559 Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r
560\r
561 if (EFI_ERROR(Status)) {\r
562 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_DEVICE_ERROR;\r
563 goto EXIT;\r
564 }\r
565\r
566 //\r
567 // Wait for completion queue to get filled in.\r
568 //\r
569 Status = EFI_TIMEOUT;\r
570 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_TIMEOUT_COMMAND;\r
571 while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r
572 if (Cq->Pt != Private->Pt[Qid]) {\r
573 Status = EFI_SUCCESS;\r
574 Packet->ControllerStatus = NVM_EXPRESS_STATUS_CONTROLLER_READY;\r
575 break;\r
576 }\r
577 }\r
578\r
579 if ((Private->CqHdbl[Qid].Cqh ^= 1) == 0) {\r
580 Private->Pt[Qid] ^= 1;\r
581 }\r
582\r
583 //\r
584 // Copy the Respose Queue entry for this command to the callers response buffer\r
585 //\r
586 CopyMem(Packet->NvmeResponse, Cq, sizeof(NVM_EXPRESS_RESPONSE));\r
587\r
588 //\r
589 // Dump every completion entry status for debugging.\r
590 //\r
591 DEBUG_CODE_BEGIN();\r
592 NvmeDumpStatus(Cq);\r
593 DEBUG_CODE_END();\r
594\r
7b8883c6 595 Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[Qid]);\r
eb290d02
FT		 596 PciIo->Mem.Write (\r
597 PciIo,\r
598 EfiPciIoWidthUint32,\r
599 NVME_BAR,\r
600 NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd),\r
601 1,\r
7b8883c6 602 &Data\r
eb290d02
FT		 603 );\r
604\r
605EXIT:\r
606 if (MapData != NULL) {\r
607 PciIo->Unmap (\r
608 PciIo,\r
609 MapData\r
610 );\r
611 }\r
612\r
613 if (MapMeta != NULL) {\r
614 PciIo->Unmap (\r
615 PciIo,\r
616 MapMeta\r
617 );\r
618 }\r
619\r
620 if (MapPrpList != NULL) {\r
621 PciIo->Unmap (\r
622 PciIo,\r
623 MapPrpList\r
624 );\r
625 }\r
626\r
627 if (Prp != NULL) {\r
628 PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r
629 }\r
630\r
631 if (TimerEvent != NULL) {\r
632 gBS->CloseEvent (TimerEvent);\r
633 }\r
634 return Status;\r
635}\r
636\r
637/**\r
638 Used to retrieve the list of namespaces defined on an NVM Express controller.\r
639\r
640 The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves a list of namespaces\r
641 defined on an NVM Express controller. If on input a NamespaceID is specified by all 0xFF in the\r
642 namespace buffer, then the first namespace defined on the NVM Express controller is returned in\r
643 NamespaceID, and a status of EFI_SUCCESS is returned.\r
644\r
645 If NamespaceId is a Namespace value that was returned on a previous call to GetNextNamespace(),\r
646 then the next valid NamespaceId for an NVM Express SSD namespace on the NVM Express controller\r
647 is returned in NamespaceId, and EFI_SUCCESS is returned.\r
648\r
649 If Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned on a previous call to\r
650 GetNextNamespace(), then EFI_INVALID_PARAMETER is returned.\r
651\r
652 If NamespaceId is the NamespaceId of the last SSD namespace on the NVM Express controller, then\r
653 EFI_NOT_FOUND is returned\r
654\r
655 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
656 @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r
657 namespace present on the NVM Express controller. On output, a\r
658 pointer to the next NamespaceId of an NVM Express namespace on\r
659 an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r
660 the first NamespaceId for an NVM Express namespace present on an\r
661 NVM Express controller.\r
662 @param[out] NamespaceUuid On output, the UUID associated with the next namespace, if a UUID\r
663 is defined for that NamespaceId, otherwise, zero is returned in\r
664 this parameter. If the caller does not require a UUID, then a NULL\r
665 pointer may be passed.\r
666\r
667 @retval EFI_SUCCESS The NamespaceId of the next Namespace was returned.\r
668 @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r
669 @retval EFI_INVALID_PARAMETER Namespace array is not a 0xFFFFFFFF and NamespaceId was not returned\r
670 on a previous call to GetNextNamespace().\r
671\r
672**/\r
673EFI_STATUS\r
674EFIAPI\r
675NvmExpressGetNextNamespace (\r
676 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
677 IN OUT UINT32 *NamespaceId,\r
678 OUT UINT64 *NamespaceUuid OPTIONAL\r
679 )\r
680{\r
681 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
682 NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r
683 UINT32 NextNamespaceId;\r
684 EFI_STATUS Status;\r
685\r
686 if ((This == NULL) || (NamespaceId == NULL)) {\r
687 return EFI_INVALID_PARAMETER;\r
688 }\r
689\r
690 NamespaceData = NULL;\r
691 Status = EFI_NOT_FOUND;\r
692\r
693 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
694 //\r
695 // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r
696 //\r
697 if (*NamespaceId == 0xFFFFFFFF) {\r
698 //\r
699 // Start with the first namespace ID\r
700 //\r
701 NextNamespaceId = 1;\r
702 //\r
703 // Allocate buffer for Identify Namespace data.\r
704 //\r
705 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
706\r
707 if (NamespaceData == NULL) {\r
708 return EFI_NOT_FOUND;\r
709 }\r
710\r
711 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
712 if (EFI_ERROR(Status)) {\r
713 goto Done;\r
714 }\r
715\r
716 *NamespaceId = NextNamespaceId;\r
717 if (NamespaceUuid != NULL) {\r
718 *NamespaceUuid = NamespaceData->Eui64;\r
719 }\r
720 } else {\r
721 if (*NamespaceId >= Private->ControllerData->Nn) {\r
722 return EFI_INVALID_PARAMETER;\r
723 }\r
724\r
725 NextNamespaceId = *NamespaceId + 1;\r
726 //\r
727 // Allocate buffer for Identify Namespace data.\r
728 //\r
729 NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r
730 if (NamespaceData == NULL) {\r
731 return EFI_NOT_FOUND;\r
732 }\r
733\r
734 Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r
735 if (EFI_ERROR(Status)) {\r
736 goto Done;\r
737 }\r
738\r
739 *NamespaceId = NextNamespaceId;\r
740 if (NamespaceUuid != NULL) {\r
741 *NamespaceUuid = NamespaceData->Eui64;\r
742 }\r
743 }\r
744\r
745Done:\r
746 if (NamespaceData != NULL) {\r
747 FreePool(NamespaceData);\r
748 }\r
749\r
750 return Status;\r
751}\r
752\r
753/**\r
754 Used to translate a device path node to a Namespace ID and Namespace UUID.\r
755\r
756 The NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamwspace() function determines the Namespace ID and Namespace UUID\r
757 associated with the NVM Express SSD namespace described by DevicePath. If DevicePath is a device path node type\r
758 that the NVM Express Pass Thru driver supports, then the NVM Express Pass Thru driver will attempt to translate\r
759 the contents DevicePath into a Namespace ID and UUID. If this translation is successful, then that Namespace ID\r
760 and UUID are returned in NamespaceID and NamespaceUUID, and EFI_SUCCESS is returned.\r
761\r
762 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
763 @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r
764 the NVM Express controller.\r
765 @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r
766 @param[out] NamespaceUuid The NVM Express namespace contained in the device path node.\r
767\r
768 @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId and NamespaceUuid.\r
769 @retval EFI_INVALID_PARAMETER If DevicePath, NamespaceId, or NamespaceUuid are NULL, then EFI_INVALID_PARAMETER\r
770 is returned.\r
771 @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r
772 supports, then EFI_UNSUPPORTED is returned.\r
773 @retval EFI_NOT_FOUND If DevicePath is a device path node type that the Nvm Express Pass Thru driver\r
774 supports, but there is not a valid translation from DevicePath to a NamespaceID\r
775 and NamespaceUuid, then EFI_NOT_FOUND is returned.\r
776**/\r
777EFI_STATUS\r
778EFIAPI\r
779NvmExpressGetNamespace (\r
780 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
781 IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
782 OUT UINT32 *NamespaceId,\r
783 OUT UINT64 *NamespaceUuid\r
784 )\r
785{\r
786 NVME_NAMESPACE_DEVICE_PATH *Node;\r
787\r
788 if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL) || (NamespaceUuid == NULL)) {\r
789 return EFI_INVALID_PARAMETER;\r
790 }\r
791\r
792 if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r
793 return EFI_UNSUPPORTED;\r
794 }\r
795\r
796 Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r
797\r
798 if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r
799 if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r
800 return EFI_NOT_FOUND;\r
801 }\r
802\r
803 *NamespaceId = Node->NamespaceId;\r
804 *NamespaceUuid = Node->NamespaceUuid;\r
805\r
806 return EFI_SUCCESS;\r
807 } else {\r
808 return EFI_UNSUPPORTED;\r
809 }\r
810}\r
811\r
812/**\r
813 Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r
814\r
815 The NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r
816 path node for the NVM Express namespace specified by NamespaceId.\r
817\r
818 If the namespace device specified by NamespaceId is not valid , then EFI_NOT_FOUND is returned.\r
819\r
820 If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r
821\r
822 If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r
823\r
824 Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r
825 initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r
826\r
827 @param[in] This A pointer to the NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r
828 @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r
829 allocated and built. Caller must set the NamespaceId to zero if the\r
830 device path node will contain a valid UUID.\r
831 @param[in] NamespaceUuid The NVM Express namespace UUID for which a device path node is to be\r
832 allocated and built. UUID will only be valid of the Namespace ID is zero.\r
833 @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r
834 namespace specified by NamespaceId. This function is responsible for\r
835 allocating the buffer DevicePath with the boot service AllocatePool().\r
836 It is the caller's responsibility to free DevicePath when the caller\r
837 is finished with DevicePath.\r
838 @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r
839 by NamespaceId was allocated and returned in DevicePath.\r
840 @retval EFI_NOT_FOUND The NVM Express namespace specified by NamespaceId does not exist on the\r
841 NVM Express controller.\r
842 @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r
843 @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r
844\r
845**/\r
846EFI_STATUS\r
847EFIAPI\r
848NvmExpressBuildDevicePath (\r
849 IN NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
850 IN UINT32 NamespaceId,\r
851 IN UINT64 NamespaceUuid,\r
852 IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
853 )\r
854{\r
855 NVME_CONTROLLER_PRIVATE_DATA *Private;\r
856 NVME_NAMESPACE_DEVICE_PATH *Node;\r
857\r
858 //\r
859 // Validate parameters\r
860 //\r
861 if ((This == NULL) || (DevicePath == NULL)) {\r
862 return EFI_INVALID_PARAMETER;\r
863 }\r
864\r
865 Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r
866\r
867 if (NamespaceId == 0) {\r
868 return EFI_NOT_FOUND;\r
869 }\r
870\r
871 Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
872\r
873 if (Node == NULL) {\r
874 return EFI_OUT_OF_RESOURCES;\r
875 }\r
876\r
877 Node->Header.Type = MESSAGING_DEVICE_PATH;\r
878 Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r
879 SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r
880 Node->NamespaceId = NamespaceId;\r
881 Node->NamespaceUuid = NamespaceUuid;\r
882\r
883 *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r
884 return EFI_SUCCESS;\r
885}\r
886\r
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