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9060e3ec | 1 | /** @file\r |
2 | PCI command register operations supporting functions declaration for PCI Bus module.\r | |
3 | \r | |
fcdfcdbf | 4 | Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9060e3ec | 6 | \r |
7 | **/\r | |
8 | \r | |
9060e3ec | 9 | #ifndef _EFI_PCI_COMMAND_H_\r |
10 | #define _EFI_PCI_COMMAND_H_\r | |
11 | \r | |
12 | //\r | |
13 | // The PCI Command register bits owned by PCI Bus driver.\r | |
14 | //\r | |
15 | // They should be cleared at the beginning. The other registers\r | |
16 | // are owned by chipset, we should not touch them.\r | |
17 | //\r | |
1436aea4 | 18 | #define EFI_PCI_COMMAND_BITS_OWNED ( \\r |
9060e3ec | 19 | EFI_PCI_COMMAND_IO_SPACE | \\r |
20 | EFI_PCI_COMMAND_MEMORY_SPACE | \\r | |
21 | EFI_PCI_COMMAND_BUS_MASTER | \\r | |
22 | EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \\r | |
23 | EFI_PCI_COMMAND_VGA_PALETTE_SNOOP | \\r | |
24 | EFI_PCI_COMMAND_FAST_BACK_TO_BACK \\r | |
25 | )\r | |
26 | \r | |
27 | //\r | |
28 | // The PCI Bridge Control register bits owned by PCI Bus driver.\r | |
29 | //\r | |
30 | // They should be cleared at the beginning. The other registers\r | |
31 | // are owned by chipset, we should not touch them.\r | |
32 | //\r | |
1436aea4 | 33 | #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED ( \\r |
9060e3ec | 34 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r |
35 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r | |
36 | EFI_PCI_BRIDGE_CONTROL_VGA_16 | \\r | |
37 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r | |
38 | )\r | |
39 | \r | |
40 | //\r | |
41 | // The PCCard Bridge Control register bits owned by PCI Bus driver.\r | |
42 | //\r | |
43 | // They should be cleared at the beginning. The other registers\r | |
44 | // are owned by chipset, we should not touch them.\r | |
45 | //\r | |
1436aea4 | 46 | #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED ( \\r |
9060e3ec | 47 | EFI_PCI_BRIDGE_CONTROL_ISA | \\r |
48 | EFI_PCI_BRIDGE_CONTROL_VGA | \\r | |
49 | EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK \\r | |
50 | )\r | |
51 | \r | |
9060e3ec | 52 | #define EFI_GET_REGISTER 1\r |
53 | #define EFI_SET_REGISTER 2\r | |
54 | #define EFI_ENABLE_REGISTER 3\r | |
55 | #define EFI_DISABLE_REGISTER 4\r | |
56 | \r | |
57 | /**\r | |
58 | Operate the PCI register via PciIo function interface.\r | |
59 | \r | |
60 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r | |
61 | @param Command Operator command.\r | |
62 | @param Offset The address within the PCI configuration space for the PCI controller.\r | |
63 | @param Operation Type of Operation.\r | |
64 | @param PtrCommand Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.\r | |
65 | \r | |
66 | @return Status of PciIo operation.\r | |
67 | \r | |
68 | **/\r | |
69 | EFI_STATUS\r | |
70 | PciOperateRegister (\r | |
1436aea4 MK |
71 | IN PCI_IO_DEVICE *PciIoDevice,\r |
72 | IN UINT16 Command,\r | |
73 | IN UINT8 Offset,\r | |
74 | IN UINT8 Operation,\r | |
75 | OUT UINT16 *PtrCommand\r | |
9060e3ec | 76 | );\r |
77 | \r | |
78 | /**\r | |
fcdfcdbf | 79 | Check the capability supporting by given device.\r |
9060e3ec | 80 | \r |
81 | @param PciIoDevice Pointer to instance of PCI_IO_DEVICE.\r | |
82 | \r | |
fcdfcdbf RN |
83 | @retval TRUE Capability supported.\r |
84 | @retval FALSE Capability not supported.\r | |
9060e3ec | 85 | \r |
86 | **/\r | |
87 | BOOLEAN\r | |
88 | PciCapabilitySupport (\r | |
89 | IN PCI_IO_DEVICE *PciIoDevice\r | |
90 | );\r | |
91 | \r | |
92 | /**\r | |
93 | Locate capability register block per capability ID.\r | |
94 | \r | |
95 | @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r | |
96 | @param CapId The capability ID.\r | |
97 | @param Offset A pointer to the offset returned.\r | |
98 | @param NextRegBlock A pointer to the next block returned.\r | |
99 | \r | |
fcdfcdbf | 100 | @retval EFI_SUCCESS Successfully located capability register block.\r |
9060e3ec | 101 | @retval EFI_UNSUPPORTED Pci device does not support capability.\r |
102 | @retval EFI_NOT_FOUND Pci device support but can not find register block.\r | |
103 | \r | |
104 | **/\r | |
105 | EFI_STATUS\r | |
106 | LocateCapabilityRegBlock (\r | |
107 | IN PCI_IO_DEVICE *PciIoDevice,\r | |
108 | IN UINT8 CapId,\r | |
109 | IN OUT UINT8 *Offset,\r | |
110 | OUT UINT8 *NextRegBlock OPTIONAL\r | |
111 | );\r | |
112 | \r | |
113 | /**\r | |
114 | Locate PciExpress capability register block per capability ID.\r | |
115 | \r | |
116 | @param PciIoDevice A pointer to the PCI_IO_DEVICE.\r | |
117 | @param CapId The capability ID.\r | |
118 | @param Offset A pointer to the offset returned.\r | |
119 | @param NextRegBlock A pointer to the next block returned.\r | |
120 | \r | |
fcdfcdbf | 121 | @retval EFI_SUCCESS Successfully located capability register block.\r |
9060e3ec | 122 | @retval EFI_UNSUPPORTED Pci device does not support capability.\r |
123 | @retval EFI_NOT_FOUND Pci device support but can not find register block.\r | |
124 | \r | |
125 | **/\r | |
126 | EFI_STATUS\r | |
127 | LocatePciExpressCapabilityRegBlock (\r | |
1436aea4 MK |
128 | IN PCI_IO_DEVICE *PciIoDevice,\r |
129 | IN UINT16 CapId,\r | |
130 | IN OUT UINT32 *Offset,\r | |
131 | OUT UINT32 *NextRegBlock OPTIONAL\r | |
9060e3ec | 132 | );\r |
133 | \r | |
134 | /**\r | |
135 | Macro that reads command register.\r | |
136 | \r | |
137 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
138 | @param b[out] Pointer to the 16-bit value read from command register.\r | |
139 | \r | |
140 | @return status of PciIo operation\r | |
141 | \r | |
142 | **/\r | |
1436aea4 | 143 | #define PCI_READ_COMMAND_REGISTER(a, b) \\r |
9060e3ec | 144 | PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)\r |
145 | \r | |
146 | /**\r | |
147 | Macro that writes command register.\r | |
148 | \r | |
149 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
150 | @param b[in] The 16-bit value written into command register.\r | |
151 | \r | |
152 | @return status of PciIo operation\r | |
153 | \r | |
154 | **/\r | |
1436aea4 | 155 | #define PCI_SET_COMMAND_REGISTER(a, b) \\r |
9060e3ec | 156 | PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)\r |
157 | \r | |
158 | /**\r | |
159 | Macro that enables command register.\r | |
160 | \r | |
161 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
162 | @param b[in] The enabled value written into command register.\r | |
163 | \r | |
164 | @return status of PciIo operation\r | |
165 | \r | |
166 | **/\r | |
1436aea4 | 167 | #define PCI_ENABLE_COMMAND_REGISTER(a, b) \\r |
9060e3ec | 168 | PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)\r |
169 | \r | |
170 | /**\r | |
fcdfcdbf | 171 | Macro that disables command register.\r |
9060e3ec | 172 | \r |
173 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
174 | @param b[in] The disabled value written into command register.\r | |
175 | \r | |
176 | @return status of PciIo operation\r | |
177 | \r | |
178 | **/\r | |
1436aea4 | 179 | #define PCI_DISABLE_COMMAND_REGISTER(a, b) \\r |
9060e3ec | 180 | PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)\r |
181 | \r | |
182 | /**\r | |
183 | Macro that reads PCI bridge control register.\r | |
184 | \r | |
185 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
186 | @param b[out] The 16-bit value read from control register.\r | |
187 | \r | |
188 | @return status of PciIo operation\r | |
189 | \r | |
190 | **/\r | |
1436aea4 | 191 | #define PCI_READ_BRIDGE_CONTROL_REGISTER(a, b) \\r |
9060e3ec | 192 | PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)\r |
193 | \r | |
194 | /**\r | |
195 | Macro that writes PCI bridge control register.\r | |
196 | \r | |
197 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
198 | @param b[in] The 16-bit value written into control register.\r | |
199 | \r | |
200 | @return status of PciIo operation\r | |
201 | \r | |
202 | **/\r | |
1436aea4 | 203 | #define PCI_SET_BRIDGE_CONTROL_REGISTER(a, b) \\r |
9060e3ec | 204 | PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)\r |
205 | \r | |
206 | /**\r | |
207 | Macro that enables PCI bridge control register.\r | |
208 | \r | |
209 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
210 | @param b[in] The enabled value written into command register.\r | |
211 | \r | |
212 | @return status of PciIo operation\r | |
213 | \r | |
214 | **/\r | |
1436aea4 | 215 | #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a, b) \\r |
9060e3ec | 216 | PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)\r |
217 | \r | |
218 | /**\r | |
fcdfcdbf | 219 | Macro that disables PCI bridge control register.\r |
9060e3ec | 220 | \r |
221 | @param a[in] Pointer to instance of PCI_IO_DEVICE.\r | |
222 | @param b[in] The disabled value written into command register.\r | |
223 | \r | |
224 | @return status of PciIo operation\r | |
225 | \r | |
226 | **/\r | |
1436aea4 | 227 | #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a, b) \\r |
9060e3ec | 228 | PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)\r |
229 | \r | |
230 | #endif\r |