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913cb9dc | 1 | /** @file\r |
2 | \r | |
ab6495ea | 3 | The definition for UHCI register operation routines.\r |
4 | \r | |
cd5ebaa0 | 5 | Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
913cb9dc | 7 | \r |
913cb9dc | 8 | **/\r |
9 | \r | |
10 | #ifndef _EFI_UHCI_QUEUE_H_\r | |
11 | #define _EFI_UHCI_QUEUE_H_\r | |
12 | \r | |
13 | //\r | |
14 | // Macroes used to set various links in UHCI's driver.\r | |
15 | // In this UHCI driver, QH's horizontal link always pointers to other QH,\r | |
16 | // and its vertical link always pointers to TD. TD's next pointer always\r | |
17 | // pointers to other sibling TD. Frame link always pointers to QH because\r | |
18 | // ISO transfer isn't supported.\r | |
19 | //\r | |
20 | // We should use UINT32 to access these pointers to void race conditions\r | |
21 | // with hardware.\r | |
22 | //\r | |
23 | #define QH_HLINK(Pointer, Terminate) \\r | |
24 | (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | 0x02 | ((Terminate) ? 0x01 : 0))\r | |
25 | \r | |
26 | #define QH_VLINK(Pointer, Terminate) \\r | |
27 | (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | ((Terminate) ? 0x01 : 0))\r | |
28 | \r | |
29 | #define TD_LINK(Pointer, VertFirst, Terminate) \\r | |
30 | (((UINT32) ((UINTN) (Pointer)) & 0xFFFFFFF0) | \\r | |
31 | ((VertFirst) ? 0x04 : 0) | ((Terminate) ? 0x01 : 0))\r | |
32 | \r | |
1436aea4 | 33 | #define LINK_TERMINATED(Link) (((Link) & 0x01) != 0)\r |
913cb9dc | 34 | \r |
1436aea4 | 35 | #define UHCI_ADDR(QhOrTd) ((VOID *) (UINTN) ((QhOrTd) & 0xFFFFFFF0))\r |
913cb9dc | 36 | \r |
37 | #pragma pack(1)\r | |
38 | //\r | |
39 | // Both links in QH has this internal structure:\r | |
40 | // Next pointer: 28, Reserved: 2, NextIsQh: 1, Terminate: 1\r | |
41 | // This is the same as frame list entry.\r | |
42 | //\r | |
43 | typedef struct {\r | |
1436aea4 MK |
44 | UINT32 HorizonLink;\r |
45 | UINT32 VerticalLink;\r | |
913cb9dc | 46 | } UHCI_QH_HW;\r |
47 | \r | |
48 | //\r | |
49 | // Next link in TD has this internal structure:\r | |
50 | // Next pointer: 28, Reserved: 1, Vertical First: 1, NextIsQh: 1, Terminate: 1\r | |
51 | //\r | |
52 | typedef struct {\r | |
1436aea4 MK |
53 | UINT32 NextLink;\r |
54 | UINT32 ActualLen : 11;\r | |
55 | UINT32 Reserved1 : 5;\r | |
56 | UINT32 Status : 8;\r | |
57 | UINT32 IntOnCpl : 1;\r | |
58 | UINT32 IsIsoch : 1;\r | |
59 | UINT32 LowSpeed : 1;\r | |
60 | UINT32 ErrorCount : 2;\r | |
61 | UINT32 ShortPacket : 1;\r | |
62 | UINT32 Reserved2 : 2;\r | |
63 | UINT32 PidCode : 8;\r | |
64 | UINT32 DeviceAddr : 7;\r | |
65 | UINT32 EndPoint : 4;\r | |
66 | UINT32 DataToggle : 1;\r | |
67 | UINT32 Reserved3 : 1;\r | |
68 | UINT32 MaxPacketLen : 11;\r | |
69 | UINT32 DataBuffer;\r | |
913cb9dc | 70 | } UHCI_TD_HW;\r |
71 | #pragma pack()\r | |
72 | \r | |
73 | typedef struct _UHCI_TD_SW UHCI_TD_SW;\r | |
74 | typedef struct _UHCI_QH_SW UHCI_QH_SW;\r | |
75 | \r | |
c52fa98c | 76 | struct _UHCI_QH_SW {\r |
1436aea4 MK |
77 | UHCI_QH_HW QhHw;\r |
78 | UHCI_QH_SW *NextQh;\r | |
79 | UHCI_TD_SW *TDs;\r | |
80 | UINTN Interval;\r | |
c52fa98c | 81 | };\r |
913cb9dc | 82 | \r |
c52fa98c | 83 | struct _UHCI_TD_SW {\r |
1436aea4 MK |
84 | UHCI_TD_HW TdHw;\r |
85 | UHCI_TD_SW *NextTd;\r | |
86 | UINT8 *Data;\r | |
87 | UINT16 DataLen;\r | |
c52fa98c | 88 | };\r |
913cb9dc | 89 | \r |
913cb9dc | 90 | /**\r |
ab6495ea | 91 | Link the TD To QH.\r |
913cb9dc | 92 | \r |
3af875e2 | 93 | @param Uhc The UHCI device.\r |
ab6495ea | 94 | @param Qh The queue head for the TD to link to.\r |
95 | @param Td The TD to link.\r | |
913cb9dc | 96 | \r |
913cb9dc | 97 | **/\r |
98 | VOID\r | |
99 | UhciLinkTdToQh (\r | |
1436aea4 MK |
100 | IN USB_HC_DEV *Uhc,\r |
101 | IN UHCI_QH_SW *Qh,\r | |
102 | IN UHCI_TD_SW *Td\r | |
ed66e1bc | 103 | );\r |
913cb9dc | 104 | \r |
913cb9dc | 105 | /**\r |
ab6495ea | 106 | Unlink TD from the QH.\r |
913cb9dc | 107 | \r |
ab6495ea | 108 | @param Qh The queue head to unlink from.\r |
109 | @param Td The TD to unlink.\r | |
913cb9dc | 110 | \r |
ab6495ea | 111 | @return None.\r |
913cb9dc | 112 | \r |
113 | **/\r | |
114 | VOID\r | |
115 | UhciUnlinkTdFromQh (\r | |
1436aea4 MK |
116 | IN UHCI_QH_SW *Qh,\r |
117 | IN UHCI_TD_SW *Td\r | |
ed66e1bc | 118 | );\r |
913cb9dc | 119 | \r |
913cb9dc | 120 | /**\r |
ab6495ea | 121 | Map address of request structure buffer.\r |
913cb9dc | 122 | \r |
ab6495ea | 123 | @param Uhc The UHCI device.\r |
124 | @param Request The user request buffer.\r | |
125 | @param MappedAddr Mapped address of request.\r | |
126 | @param Map Identificaion of this mapping to return.\r | |
913cb9dc | 127 | \r |
ab6495ea | 128 | @return EFI_SUCCESS Success.\r |
129 | @return EFI_DEVICE_ERROR Fail to map the user request.\r | |
913cb9dc | 130 | \r |
131 | **/\r | |
132 | EFI_STATUS\r | |
133 | UhciMapUserRequest (\r | |
1436aea4 MK |
134 | IN USB_HC_DEV *Uhc,\r |
135 | IN OUT VOID *Request,\r | |
136 | OUT UINT8 **MappedAddr,\r | |
137 | OUT VOID **Map\r | |
ed66e1bc | 138 | );\r |
913cb9dc | 139 | \r |
913cb9dc | 140 | /**\r |
ab6495ea | 141 | Map address of user data buffer.\r |
913cb9dc | 142 | \r |
ab6495ea | 143 | @param Uhc The UHCI device.\r |
144 | @param Direction Direction of the data transfer.\r | |
145 | @param Data The user data buffer.\r | |
146 | @param Len Length of the user data.\r | |
147 | @param PktId Packet identificaion.\r | |
148 | @param MappedAddr Mapped address to return.\r | |
149 | @param Map Identificaion of this mapping to return.\r | |
913cb9dc | 150 | \r |
ab6495ea | 151 | @return EFI_SUCCESS Success.\r |
152 | @return EFI_DEVICE_ERROR Fail to map the user data.\r | |
913cb9dc | 153 | \r |
154 | **/\r | |
155 | EFI_STATUS\r | |
156 | UhciMapUserData (\r | |
157 | IN USB_HC_DEV *Uhc,\r | |
158 | IN EFI_USB_DATA_DIRECTION Direction,\r | |
159 | IN VOID *Data,\r | |
160 | IN OUT UINTN *Len,\r | |
161 | OUT UINT8 *PktId,\r | |
162 | OUT UINT8 **MappedAddr,\r | |
163 | OUT VOID **Map\r | |
ed66e1bc | 164 | );\r |
913cb9dc | 165 | \r |
913cb9dc | 166 | /**\r |
ab6495ea | 167 | Delete a list of TDs.\r |
913cb9dc | 168 | \r |
ab6495ea | 169 | @param Uhc The UHCI device.\r |
170 | @param FirstTd TD link list head.\r | |
913cb9dc | 171 | \r |
ab6495ea | 172 | @return None.\r |
913cb9dc | 173 | \r |
174 | **/\r | |
175 | VOID\r | |
176 | UhciDestoryTds (\r | |
1436aea4 MK |
177 | IN USB_HC_DEV *Uhc,\r |
178 | IN UHCI_TD_SW *FirstTd\r | |
ed66e1bc | 179 | );\r |
913cb9dc | 180 | \r |
913cb9dc | 181 | /**\r |
ab6495ea | 182 | Create an initialize a new queue head.\r |
913cb9dc | 183 | \r |
ab6495ea | 184 | @param Uhc The UHCI device.\r |
185 | @param Interval The polling interval for the queue.\r | |
913cb9dc | 186 | \r |
ab6495ea | 187 | @return The newly created queue header.\r |
913cb9dc | 188 | \r |
189 | **/\r | |
190 | UHCI_QH_SW *\r | |
191 | UhciCreateQh (\r | |
1436aea4 MK |
192 | IN USB_HC_DEV *Uhc,\r |
193 | IN UINTN Interval\r | |
ed66e1bc | 194 | );\r |
913cb9dc | 195 | \r |
913cb9dc | 196 | /**\r |
ab6495ea | 197 | Create Tds list for Control Transfer.\r |
913cb9dc | 198 | \r |
ab6495ea | 199 | @param Uhc The UHCI device.\r |
200 | @param DeviceAddr The device address.\r | |
201 | @param DataPktId Packet Identification of Data Tds.\r | |
3af875e2 | 202 | @param Request A pointer to cpu memory address of request structure buffer to transfer.\r |
203 | @param RequestPhy A pointer to pci memory address of request structure buffer to transfer.\r | |
204 | @param Data A pointer to cpu memory address of user data buffer to transfer.\r | |
205 | @param DataPhy A pointer to pci memory address of user data buffer to transfer.\r | |
ab6495ea | 206 | @param DataLen Length of user data to transfer.\r |
207 | @param MaxPacket Maximum packet size for control transfer.\r | |
208 | @param IsLow Full speed or low speed.\r | |
913cb9dc | 209 | \r |
ab6495ea | 210 | @return The Td list head for the control transfer.\r |
913cb9dc | 211 | \r |
212 | **/\r | |
213 | UHCI_TD_SW *\r | |
214 | UhciCreateCtrlTds (\r | |
1436aea4 MK |
215 | IN USB_HC_DEV *Uhc,\r |
216 | IN UINT8 DeviceAddr,\r | |
217 | IN UINT8 DataPktId,\r | |
218 | IN UINT8 *Request,\r | |
219 | IN UINT8 *RequestPhy,\r | |
220 | IN UINT8 *Data,\r | |
221 | IN UINT8 *DataPhy,\r | |
222 | IN UINTN DataLen,\r | |
223 | IN UINT8 MaxPacket,\r | |
224 | IN BOOLEAN IsLow\r | |
ed66e1bc | 225 | );\r |
913cb9dc | 226 | \r |
913cb9dc | 227 | /**\r |
ab6495ea | 228 | Create Tds list for Bulk/Interrupt Transfer.\r |
229 | \r | |
230 | @param Uhc USB_HC_DEV.\r | |
231 | @param DevAddr Address of Device.\r | |
232 | @param EndPoint Endpoint Number.\r | |
233 | @param PktId Packet Identification of Data Tds.\r | |
3af875e2 | 234 | @param Data A pointer to cpu memory address of user data buffer to transfer.\r |
235 | @param DataPhy A pointer to pci memory address of user data buffer to transfer.\r | |
ab6495ea | 236 | @param DataLen Length of user data to transfer.\r |
237 | @param DataToggle Data Toggle Pointer.\r | |
238 | @param MaxPacket Maximum packet size for Bulk/Interrupt transfer.\r | |
239 | @param IsLow Is Low Speed Device.\r | |
240 | \r | |
241 | @return The Tds list head for the bulk transfer.\r | |
913cb9dc | 242 | \r |
243 | **/\r | |
244 | UHCI_TD_SW *\r | |
245 | UhciCreateBulkOrIntTds (\r | |
1436aea4 MK |
246 | IN USB_HC_DEV *Uhc,\r |
247 | IN UINT8 DevAddr,\r | |
248 | IN UINT8 EndPoint,\r | |
249 | IN UINT8 PktId,\r | |
250 | IN UINT8 *Data,\r | |
251 | IN UINT8 *DataPhy,\r | |
252 | IN UINTN DataLen,\r | |
253 | IN OUT UINT8 *DataToggle,\r | |
254 | IN UINT8 MaxPacket,\r | |
255 | IN BOOLEAN IsLow\r | |
ed66e1bc | 256 | );\r |
913cb9dc | 257 | \r |
258 | #endif\r |