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MdeModulePkg: Add PEI USB drivers and related PPIs
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciPei / UhcPeim.h
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4b1bf81c 1/** @file\r
2Private Header file for Usb Host Controller PEIM\r
3\r
4Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r
5 \r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions\r
8of the BSD License which accompanies this distribution. The\r
9full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _RECOVERY_UHC_H_\r
18#define _RECOVERY_UHC_H_\r
19\r
20\r
21#include <PiPei.h>\r
22\r
23#include <Ppi/UsbController.h>\r
24#include <Ppi/UsbHostController.h>\r
25\r
26#include <Library/DebugLib.h>\r
27#include <Library/PeimEntryPoint.h>\r
28#include <Library/PeiServicesLib.h>\r
29#include <Library/BaseMemoryLib.h>\r
30#include <Library/TimerLib.h>\r
31#include <Library/IoLib.h>\r
32#include <Library/PeiServicesLib.h>\r
33\r
34#define USB_SLOW_SPEED_DEVICE 0x01\r
35#define USB_FULL_SPEED_DEVICE 0x02\r
36\r
37//\r
38// One memory block uses 16 page\r
39//\r
40#define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16\r
41\r
42#define USBCMD 0 /* Command Register Offset 00-01h */\r
43#define USBCMD_RS BIT0 /* Run/Stop */\r
44#define USBCMD_HCRESET BIT1 /* Host reset */\r
45#define USBCMD_GRESET BIT2 /* Global reset */\r
46#define USBCMD_EGSM BIT3 /* Global Suspend Mode */\r
47#define USBCMD_FGR BIT4 /* Force Global Resume */\r
48#define USBCMD_SWDBG BIT5 /* SW Debug mode */\r
49#define USBCMD_CF BIT6 /* Config Flag (sw only) */\r
50#define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */\r
51\r
52/* Status register */\r
53#define USBSTS 2 /* Status Register Offset 02-03h */\r
54#define USBSTS_USBINT BIT0 /* Interrupt due to IOC */\r
55#define USBSTS_ERROR BIT1 /* Interrupt due to error */\r
56#define USBSTS_RD BIT2 /* Resume Detect */\r
57#define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */\r
58#define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */\r
59#define USBSTS_HCH BIT5 /* HC Halted */\r
60\r
61/* Interrupt enable register */\r
62#define USBINTR 4 /* Interrupt Enable Register 04-05h */\r
63#define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */\r
64#define USBINTR_RESUME BIT1 /* Resume interrupt enable */\r
65#define USBINTR_IOC BIT2 /* Interrupt On Complete enable */\r
66#define USBINTR_SP BIT3 /* Short packet interrupt enable */\r
67\r
68/* Frame Number Register Offset 06-08h */\r
69#define USBFRNUM 6\r
70\r
71/* Frame List Base Address Register Offset 08-0Bh */\r
72#define USBFLBASEADD 8\r
73\r
74/* Start of Frame Modify Register Offset 0Ch */\r
75#define USBSOF 0x0c\r
76\r
77/* USB port status and control registers */\r
78#define USBPORTSC1 0x10 /*Port 1 offset 10-11h */\r
79#define USBPORTSC2 0x12 /*Port 2 offset 12-13h */\r
80\r
81#define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */\r
82#define USBPORTSC_CSC BIT1 /* Connect Status Change */\r
83#define USBPORTSC_PED BIT2 /* Port Enable / Disable */\r
84#define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */\r
85#define USBPORTSC_LSL BIT4 /* Line Status Low bit*/\r
86#define USBPORTSC_LSH BIT5 /* Line Status High bit*/\r
87#define USBPORTSC_RD BIT6 /* Resume Detect */\r
88#define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */\r
89#define USBPORTSC_PR BIT9 /* Port Reset */\r
90#define USBPORTSC_SUSP BIT12 /* Suspend */\r
91\r
92#define SETUP_PACKET_ID 0x2D\r
93#define INPUT_PACKET_ID 0x69\r
94#define OUTPUT_PACKET_ID 0xE1\r
95#define ERROR_PACKET_ID 0x55\r
96\r
97#define STALL_1_MILLI_SECOND 1000\r
98\r
99\r
100#pragma pack(1)\r
101\r
102typedef struct {\r
103 UINT32 FrameListPtrTerminate : 1;\r
104 UINT32 FrameListPtrQSelect : 1;\r
105 UINT32 FrameListRsvd : 2;\r
106 UINT32 FrameListPtr : 28;\r
107} FRAMELIST_ENTRY;\r
108\r
109typedef struct {\r
110 UINT32 QHHorizontalTerminate : 1;\r
111 UINT32 QHHorizontalQSelect : 1;\r
112 UINT32 QHHorizontalRsvd : 2;\r
113 UINT32 QHHorizontalPtr : 28;\r
114 UINT32 QHVerticalTerminate : 1;\r
115 UINT32 QHVerticalQSelect : 1;\r
116 UINT32 QHVerticalRsvd : 2;\r
117 UINT32 QHVerticalPtr : 28;\r
118} QUEUE_HEAD;\r
119\r
120typedef struct {\r
121 QUEUE_HEAD QueueHead;\r
122 UINT32 Reserved1;\r
123 UINT32 Reserved2;\r
124 VOID *PtrNext;\r
125 VOID *PtrDown;\r
126 VOID *Reserved3;\r
127 UINT32 Reserved4;\r
128} QH_STRUCT;\r
129\r
130typedef struct {\r
131 UINT32 TDLinkPtrTerminate : 1;\r
132 UINT32 TDLinkPtrQSelect : 1;\r
133 UINT32 TDLinkPtrDepthSelect : 1;\r
134 UINT32 TDLinkPtrRsvd : 1;\r
135 UINT32 TDLinkPtr : 28;\r
136 UINT32 TDStatusActualLength : 11;\r
137 UINT32 TDStatusRsvd : 5;\r
138 UINT32 TDStatus : 8;\r
139 UINT32 TDStatusIOC : 1;\r
140 UINT32 TDStatusIOS : 1;\r
141 UINT32 TDStatusLS : 1;\r
142 UINT32 TDStatusErr : 2;\r
143 UINT32 TDStatusSPD : 1;\r
144 UINT32 TDStatusRsvd2 : 2;\r
145 UINT32 TDTokenPID : 8;\r
146 UINT32 TDTokenDevAddr : 7;\r
147 UINT32 TDTokenEndPt : 4;\r
148 UINT32 TDTokenDataToggle : 1;\r
149 UINT32 TDTokenRsvd : 1;\r
150 UINT32 TDTokenMaxLen : 11;\r
151 UINT32 TDBufferPtr;\r
152} TD;\r
153\r
154typedef struct {\r
155 TD TDData;\r
156 UINT8 *PtrTDBuffer;\r
157 VOID *PtrNextTD;\r
158 VOID *PtrNextQH;\r
159 UINT16 TDBufferLength;\r
160 UINT16 Reserved;\r
161} TD_STRUCT;\r
162\r
163#pragma pack()\r
164\r
165typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;\r
166\r
167struct _MEMORY_MANAGE_HEADER {\r
168 UINT8 *BitArrayPtr;\r
169 UINTN BitArraySizeInBytes;\r
170 UINT8 *MemoryBlockPtr;\r
171 UINTN MemoryBlockSizeInBytes;\r
172 MEMORY_MANAGE_HEADER *Next;\r
173};\r
174\r
175#define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')\r
176typedef struct {\r
177 UINTN Signature;\r
178 PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;\r
179 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
180\r
181 UINT32 UsbHostControllerBaseAddress;\r
182 FRAMELIST_ENTRY *FrameListEntry;\r
183 QH_STRUCT *ConfigQH;\r
184 QH_STRUCT *BulkQH;\r
185 //\r
186 // Header1 used for QH,TD memory blocks management\r
187 //\r
188 MEMORY_MANAGE_HEADER *Header1;\r
189\r
190} USB_UHC_DEV;\r
191\r
192#define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)\r
193\r
194/**\r
195 Submits control transfer to a target USB device.\r
196 \r
197 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
198 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
199 @param DeviceAddress The target device address.\r
200 @param DeviceSpeed Target device speed.\r
201 @param MaximumPacketLength Maximum packet size the default control transfer \r
202 endpoint is capable of sending or receiving.\r
203 @param Request USB device request to send.\r
204 @param TransferDirection Specifies the data direction for the data stage.\r
205 @param Data Data buffer to be transmitted or received from USB device.\r
206 @param DataLength The size (in bytes) of the data buffer.\r
207 @param TimeOut Indicates the maximum timeout, in millisecond.\r
208 @param TransferResult Return the result of this control transfer.\r
209\r
210 @retval EFI_SUCCESS Transfer was completed successfully.\r
211 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.\r
212 @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r
213 @retval EFI_TIMEOUT Transfer failed due to timeout.\r
214 @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.\r
215\r
216**/\r
217EFI_STATUS\r
218EFIAPI\r
219UhcControlTransfer (\r
220 IN EFI_PEI_SERVICES **PeiServices,\r
221 IN PEI_USB_HOST_CONTROLLER_PPI * This,\r
222 IN UINT8 DeviceAddress,\r
223 IN UINT8 DeviceSpeed,\r
224 IN UINT8 MaximumPacketLength,\r
225 IN EFI_USB_DEVICE_REQUEST * Request,\r
226 IN EFI_USB_DATA_DIRECTION TransferDirection,\r
227 IN OUT VOID *Data OPTIONAL,\r
228 IN OUT UINTN *DataLength OPTIONAL,\r
229 IN UINTN TimeOut,\r
230 OUT UINT32 *TransferResult\r
231 );\r
232\r
233/**\r
234 Submits bulk transfer to a bulk endpoint of a USB device.\r
235 \r
236 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
237 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
238 @param DeviceAddress Target device address.\r
239 @param EndPointAddress Endpoint number and its direction in bit 7.\r
240 @param MaximumPacketLength Maximum packet size the endpoint is capable of \r
241 sending or receiving.\r
242 @param Data Array of pointers to the buffers of data to transmit \r
243 from or receive into.\r
244 @param DataLength The lenght of the data buffer.\r
245 @param DataToggle On input, the initial data toggle for the transfer;\r
246 On output, it is updated to to next data toggle to use of \r
247 the subsequent bulk transfer.\r
248 @param TimeOut Indicates the maximum time, in millisecond, which the\r
249 transfer is allowed to complete.\r
250 @param TransferResult A pointer to the detailed result information of the\r
251 bulk transfer.\r
252\r
253 @retval EFI_SUCCESS The transfer was completed successfully.\r
254 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r
255 @retval EFI_INVALID_PARAMETER Parameters are invalid.\r
256 @retval EFI_TIMEOUT The transfer failed due to timeout.\r
257 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r
258\r
259**/\r
260EFI_STATUS\r
261EFIAPI\r
262UhcBulkTransfer (\r
263 IN EFI_PEI_SERVICES **PeiServices,\r
264 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
265 IN UINT8 DeviceAddress,\r
266 IN UINT8 EndPointAddress,\r
267 IN UINT8 MaximumPacketLength,\r
268 IN OUT VOID *Data,\r
269 IN OUT UINTN *DataLength,\r
270 IN OUT UINT8 *DataToggle,\r
271 IN UINTN TimeOut,\r
272 OUT UINT32 *TransferResult\r
273 );\r
274\r
275/**\r
276 Retrieves the number of root hub ports.\r
277\r
278 @param[in] PeiServices The pointer to the PEI Services Table.\r
279 @param[in] This The pointer to this instance of the \r
280 PEI_USB_HOST_CONTROLLER_PPI.\r
281 @param[out] PortNumber The pointer to the number of the root hub ports. \r
282 \r
283 @retval EFI_SUCCESS The port number was retrieved successfully.\r
284 @retval EFI_INVALID_PARAMETER PortNumber is NULL.\r
285\r
286**/\r
287EFI_STATUS\r
288EFIAPI\r
289UhcGetRootHubPortNumber (\r
290 IN EFI_PEI_SERVICES **PeiServices,\r
291 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
292 OUT UINT8 *PortNumber\r
293 );\r
294\r
295/**\r
296 Retrieves the current status of a USB root hub port.\r
297 \r
298 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
299 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
300 @param PortNumber The root hub port to retrieve the state from. \r
301 @param PortStatus Variable to receive the port state.\r
302\r
303 @retval EFI_SUCCESS The status of the USB root hub port specified.\r
304 by PortNumber was returned in PortStatus.\r
305 @retval EFI_INVALID_PARAMETER PortNumber is invalid.\r
306\r
307**/\r
308EFI_STATUS\r
309EFIAPI\r
310UhcGetRootHubPortStatus (\r
311 IN EFI_PEI_SERVICES **PeiServices,\r
312 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
313 IN UINT8 PortNumber,\r
314 OUT EFI_USB_PORT_STATUS *PortStatus\r
315 );\r
316\r
317/**\r
318 Sets a feature for the specified root hub port.\r
319 \r
320 @param PeiServices The pointer of EFI_PEI_SERVICES\r
321 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI\r
322 @param PortNumber Root hub port to set.\r
323 @param PortFeature Feature to set.\r
324\r
325 @retval EFI_SUCCESS The feature specified by PortFeature was set.\r
326 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r
327 @retval EFI_TIMEOUT The time out occurred.\r
328\r
329**/\r
330EFI_STATUS\r
331EFIAPI\r
332UhcSetRootHubPortFeature (\r
333 IN EFI_PEI_SERVICES **PeiServices,\r
334 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
335 IN UINT8 PortNumber,\r
336 IN EFI_USB_PORT_FEATURE PortFeature\r
337 );\r
338\r
339/**\r
340 Clears a feature for the specified root hub port.\r
341 \r
342 @param PeiServices The pointer of EFI_PEI_SERVICES.\r
343 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.\r
344 @param PortNumber Specifies the root hub port whose feature\r
345 is requested to be cleared.\r
346 @param PortFeature Indicates the feature selector associated with the\r
347 feature clear request.\r
348\r
349 @retval EFI_SUCCESS The feature specified by PortFeature was cleared \r
350 for the USB root hub port specified by PortNumber.\r
351 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r
352\r
353**/\r
354EFI_STATUS\r
355EFIAPI\r
356UhcClearRootHubPortFeature (\r
357 IN EFI_PEI_SERVICES **PeiServices,\r
358 IN PEI_USB_HOST_CONTROLLER_PPI *This,\r
359 IN UINT8 PortNumber,\r
360 IN EFI_USB_PORT_FEATURE PortFeature\r
361 );\r
362\r
363/**\r
364 Initialize UHCI.\r
365\r
366 @param UhcDev UHCI Device.\r
367\r
368 @retval EFI_SUCCESS UHCI successfully initialized.\r
369 @retval EFI_OUT_OF_RESOURCES Resource can not be allocated.\r
370\r
371**/\r
372EFI_STATUS\r
373InitializeUsbHC (\r
374 IN USB_UHC_DEV *UhcDev\r
375 );\r
376\r
377/**\r
378 Create Frame List Structure.\r
379\r
380 @param UhcDev UHCI device.\r
381\r
382 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
383 @retval EFI_SUCCESS Success.\r
384\r
385**/\r
386EFI_STATUS\r
387CreateFrameList (\r
388 USB_UHC_DEV *UhcDev\r
389 );\r
390\r
391/**\r
392 Read a 16bit width data from Uhc HC IO space register.\r
393 \r
394 @param UhcDev The UHCI device.\r
395 @param Port The IO space address of the register.\r
396\r
397 @retval the register content read.\r
398\r
399**/\r
400UINT16\r
401USBReadPortW (\r
402 IN USB_UHC_DEV *UhcDev,\r
403 IN UINT32 Port\r
404 );\r
405\r
406/**\r
407 Write a 16bit width data into Uhc HC IO space register.\r
408 \r
409 @param UhcDev The UHCI device.\r
410 @param Port The IO space address of the register.\r
411 @param Data The data written into the register.\r
412\r
413**/\r
414VOID\r
415USBWritePortW (\r
416 IN USB_UHC_DEV *UhcDev,\r
417 IN UINT32 Port,\r
418 IN UINT16 Data\r
419 );\r
420\r
421/**\r
422 Write a 32bit width data into Uhc HC IO space register.\r
423 \r
424 @param UhcDev The UHCI device.\r
425 @param Port The IO space address of the register.\r
426 @param Data The data written into the register.\r
427\r
428**/\r
429VOID\r
430USBWritePortDW (\r
431 IN USB_UHC_DEV *UhcDev,\r
432 IN UINT32 Port,\r
433 IN UINT32 Data\r
434 );\r
435\r
436/**\r
437 Clear the content of UHCI's Status Register.\r
438 \r
439 @param UhcDev The UHCI device.\r
440 @param StatusAddr The IO space address of the register.\r
441\r
442**/\r
443VOID\r
444ClearStatusReg (\r
445 IN USB_UHC_DEV *UhcDev,\r
446 IN UINT32 StatusAddr\r
447 );\r
448\r
449/**\r
450 Check whether the host controller operates well.\r
451\r
452 @param UhcDev The UHCI device.\r
453 @param StatusRegAddr The io address of status register.\r
454\r
455 @retval TRUE Host controller is working.\r
456 @retval FALSE Host controller is halted or system error.\r
457\r
458**/\r
459BOOLEAN\r
460IsStatusOK (\r
461 IN USB_UHC_DEV *UhcDev,\r
462 IN UINT32 StatusRegAddr\r
463 );\r
464\r
465/**\r
466 Get Current Frame Number.\r
467\r
468 @param UhcDev The UHCI device.\r
469 @param FrameNumberAddr The address of frame list register.\r
470\r
471 @retval The content of the frame list register.\r
472\r
473**/\r
474UINT16\r
475GetCurrentFrameNumber (\r
476 IN USB_UHC_DEV *UhcDev,\r
477 IN UINT32 FrameNumberAddr\r
478 );\r
479\r
480/**\r
481 Set Frame List Base Address.\r
482\r
483 @param UhcDev The UHCI device.\r
484 @param FrameListRegAddr The address of frame list register.\r
485 @param Addr The address of frame list table.\r
486\r
487**/\r
488VOID\r
489SetFrameListBaseAddress (\r
490 IN USB_UHC_DEV *UhcDev,\r
491 IN UINT32 FrameListRegAddr,\r
492 IN UINT32 Addr\r
493 );\r
494\r
495/**\r
496 Create QH and initialize.\r
497\r
498 @param UhcDev The UHCI device.\r
499 @param PtrQH Place to store QH_STRUCT pointer.\r
500\r
501 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
502 @retval EFI_SUCCESS Success.\r
503\r
504**/\r
505EFI_STATUS\r
506CreateQH (\r
507 IN USB_UHC_DEV *UhcDev,\r
508 OUT QH_STRUCT **PtrQH\r
509 );\r
510\r
511/**\r
512 Set the horizontal link pointer in QH.\r
513\r
514 @param PtrQH Place to store QH_STRUCT pointer.\r
515 @param PtrNext Place to the next QH_STRUCT.\r
516\r
517**/\r
518VOID\r
519SetQHHorizontalLinkPtr (\r
520 IN QH_STRUCT *PtrQH,\r
521 IN VOID *PtrNext\r
522 );\r
523\r
524/**\r
525 Get the horizontal link pointer in QH.\r
526\r
527 @param PtrQH Place to store QH_STRUCT pointer.\r
528\r
529 @retval The horizontal link pointer in QH.\r
530\r
531**/\r
532VOID *\r
533GetQHHorizontalLinkPtr (\r
534 IN QH_STRUCT *PtrQH\r
535 );\r
536\r
537/**\r
538 Set a QH or TD horizontally to be connected with a specific QH.\r
539\r
540 @param PtrQH Place to store QH_STRUCT pointer.\r
541 @param IsQH Specify QH or TD is connected.\r
542\r
543**/\r
544VOID\r
545SetQHHorizontalQHorTDSelect (\r
546 IN QH_STRUCT *PtrQH,\r
547 IN BOOLEAN IsQH\r
548 );\r
549\r
550/**\r
551 Set the horizontal validor bit in QH.\r
552\r
553 @param PtrQH Place to store QH_STRUCT pointer.\r
554 @param IsValid Specify the horizontal linker is valid or not.\r
555\r
556**/\r
557VOID\r
558SetQHHorizontalValidorInvalid (\r
559 IN QH_STRUCT *PtrQH,\r
560 IN BOOLEAN IsValid\r
561 );\r
562\r
563/**\r
564 Set the vertical link pointer in QH.\r
565\r
566 @param PtrQH Place to store QH_STRUCT pointer.\r
567 @param PtrNext Place to the next QH_STRUCT.\r
568\r
569**/\r
570VOID\r
571SetQHVerticalLinkPtr (\r
572 IN QH_STRUCT *PtrQH,\r
573 IN VOID *PtrNext\r
574 );\r
575\r
576/**\r
577 Set a QH or TD vertically to be connected with a specific QH.\r
578\r
579 @param PtrQH Place to store QH_STRUCT pointer.\r
580 @param IsQH Specify QH or TD is connected.\r
581\r
582**/\r
583VOID\r
584SetQHVerticalQHorTDSelect (\r
585 IN QH_STRUCT *PtrQH,\r
586 IN BOOLEAN IsQH\r
587 );\r
588\r
589/**\r
590 Set the vertical validor bit in QH.\r
591\r
592 @param PtrQH Place to store QH_STRUCT pointer.\r
593 @param IsValid Specify the vertical linker is valid or not.\r
594\r
595**/\r
596VOID\r
597SetQHVerticalValidorInvalid (\r
598 IN QH_STRUCT *PtrQH,\r
599 IN BOOLEAN IsValid\r
600 );\r
601\r
602/**\r
603 Get the vertical validor bit in QH.\r
604\r
605 @param PtrQH Place to store QH_STRUCT pointer.\r
606\r
607 @retval The vertical linker is valid or not.\r
608\r
609**/\r
610BOOLEAN\r
611GetQHHorizontalValidorInvalid (\r
612 IN QH_STRUCT *PtrQH\r
613 );\r
614\r
615/**\r
616 Allocate TD or QH Struct.\r
617\r
618 @param UhcDev The UHCI device.\r
619 @param Size The size of allocation.\r
620 @param PtrStruct Place to store TD_STRUCT pointer.\r
621\r
622 @return EFI_SUCCESS Allocate successfully.\r
623 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
624\r
625**/\r
626EFI_STATUS\r
627AllocateTDorQHStruct (\r
628 IN USB_UHC_DEV *UhcDev,\r
629 IN UINT32 Size,\r
630 OUT VOID **PtrStruct\r
631 );\r
632\r
633/**\r
634 Create a TD Struct.\r
635\r
636 @param UhcDev The UHCI device.\r
637 @param PtrTD Place to store TD_STRUCT pointer.\r
638\r
639 @return EFI_SUCCESS Allocate successfully.\r
640 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
641\r
642**/\r
643EFI_STATUS\r
644CreateTD (\r
645 IN USB_UHC_DEV *UhcDev,\r
646 OUT TD_STRUCT **PtrTD\r
647 );\r
648\r
649/**\r
650 Generate Setup Stage TD.\r
651\r
652 @param UhcDev The UHCI device.\r
653 @param DevAddr Device address.\r
654 @param Endpoint Endpoint number.\r
655 @param DeviceSpeed Device Speed.\r
656 @param DevRequest Device reuquest.\r
657 @param RequestLen Request length.\r
658 @param PtrTD TD_STRUCT generated.\r
659\r
660 @return EFI_SUCCESS Generate setup stage TD successfully.\r
661 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
662\r
663**/\r
664EFI_STATUS\r
665GenSetupStageTD (\r
666 IN USB_UHC_DEV *UhcDev,\r
667 IN UINT8 DevAddr,\r
668 IN UINT8 Endpoint,\r
669 IN UINT8 DeviceSpeed,\r
670 IN UINT8 *DevRequest,\r
671 IN UINT8 RequestLen,\r
672 OUT TD_STRUCT **PtrTD\r
673 );\r
674\r
675/**\r
676 Generate Data Stage TD.\r
677\r
678 @param UhcDev The UHCI device.\r
679 @param DevAddr Device address.\r
680 @param Endpoint Endpoint number.\r
681 @param PtrData Data buffer.\r
682 @param Len Data length.\r
683 @param PktID PacketID.\r
684 @param Toggle Data toggle value.\r
685 @param DeviceSpeed Device Speed.\r
686 @param PtrTD TD_STRUCT generated.\r
687\r
688 @return EFI_SUCCESS Generate data stage TD successfully.\r
689 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
690\r
691**/\r
692EFI_STATUS\r
693GenDataTD (\r
694 IN USB_UHC_DEV *UhcDev,\r
695 IN UINT8 DevAddr,\r
696 IN UINT8 Endpoint,\r
697 IN UINT8 *PtrData,\r
698 IN UINT8 Len,\r
699 IN UINT8 PktID,\r
700 IN UINT8 Toggle,\r
701 IN UINT8 DeviceSpeed,\r
702 OUT TD_STRUCT **PtrTD\r
703 );\r
704\r
705/**\r
706 Generate Status Stage TD.\r
707\r
708 @param UhcDev The UHCI device.\r
709 @param DevAddr Device address.\r
710 @param Endpoint Endpoint number.\r
711 @param PktID PacketID.\r
712 @param DeviceSpeed Device Speed.\r
713 @param PtrTD TD_STRUCT generated.\r
714\r
715 @return EFI_SUCCESS Generate status stage TD successfully.\r
716 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.\r
717\r
718**/\r
719EFI_STATUS\r
720CreateStatusTD (\r
721 IN USB_UHC_DEV *UhcDev,\r
722 IN UINT8 DevAddr,\r
723 IN UINT8 Endpoint,\r
724 IN UINT8 PktID,\r
725 IN UINT8 DeviceSpeed,\r
726 OUT TD_STRUCT **PtrTD\r
727 );\r
728\r
729/**\r
730 Set the link pointer validor bit in TD.\r
731\r
732 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
733 @param IsValid Specify the linker pointer is valid or not.\r
734\r
735**/\r
736VOID\r
737SetTDLinkPtrValidorInvalid (\r
738 IN TD_STRUCT *PtrTDStruct,\r
739 IN BOOLEAN IsValid\r
740 );\r
741\r
742/**\r
743 Set the Link Pointer pointing to a QH or TD.\r
744\r
745 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
746 @param IsQH Specify QH or TD is connected.\r
747\r
748**/\r
749VOID\r
750SetTDLinkPtrQHorTDSelect (\r
751 IN TD_STRUCT *PtrTDStruct,\r
752 IN BOOLEAN IsQH\r
753 );\r
754\r
755/**\r
756 Set the traverse is depth-first or breadth-first.\r
757\r
758 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
759 @param IsDepth Specify the traverse is depth-first or breadth-first.\r
760\r
761**/\r
762VOID\r
763SetTDLinkPtrDepthorBreadth (\r
764 IN TD_STRUCT *PtrTDStruct,\r
765 IN BOOLEAN IsDepth\r
766 );\r
767\r
768/**\r
769 Set TD Link Pointer in TD.\r
770\r
771 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
772 @param PtrNext Place to the next TD_STRUCT.\r
773\r
774**/\r
775VOID\r
776SetTDLinkPtr (\r
777 IN TD_STRUCT *PtrTDStruct,\r
778 IN VOID *PtrNext\r
779 );\r
780\r
781/**\r
782 Get TD Link Pointer.\r
783\r
784 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
785\r
786 @retval Get TD Link Pointer in TD.\r
787\r
788**/\r
789VOID*\r
790GetTDLinkPtr (\r
791 IN TD_STRUCT *PtrTDStruct\r
792 );\r
793\r
794/**\r
795 Get the information about whether the Link Pointer field pointing to\r
796 a QH or a TD.\r
797\r
798 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
799\r
800 @retval whether the Link Pointer field pointing to a QH or a TD.\r
801\r
802**/\r
803BOOLEAN\r
804IsTDLinkPtrQHOrTD (\r
805 IN TD_STRUCT *PtrTDStruct\r
806 );\r
807\r
808/**\r
809 Enable/Disable short packet detection mechanism.\r
810\r
811 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
812 @param IsEnable Enable or disable short packet detection mechanism.\r
813\r
814**/\r
815VOID\r
816EnableorDisableTDShortPacket (\r
817 IN TD_STRUCT *PtrTDStruct,\r
818 IN BOOLEAN IsEnable\r
819 );\r
820\r
821/**\r
822 Set the max error counter in TD.\r
823\r
824 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
825 @param MaxErrors The number of allowable error.\r
826\r
827**/\r
828VOID\r
829SetTDControlErrorCounter (\r
830 IN TD_STRUCT *PtrTDStruct,\r
831 IN UINT8 MaxErrors\r
832 );\r
833\r
834/**\r
835 Set the TD is targeting a low-speed device or not.\r
836\r
837 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
838 @param IsLowSpeedDevice Whether The device is low-speed.\r
839\r
840**/\r
841VOID\r
842SetTDLoworFullSpeedDevice (\r
843 IN TD_STRUCT *PtrTDStruct,\r
844 IN BOOLEAN IsLowSpeedDevice\r
845 );\r
846\r
847/**\r
848 Set the TD is isochronous transfer type or not.\r
849\r
850 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
851 @param IsIsochronous Whether the transaction isochronous transfer type.\r
852\r
853**/\r
854VOID\r
855SetTDControlIsochronousorNot (\r
856 IN TD_STRUCT *PtrTDStruct,\r
857 IN BOOLEAN IsIsochronous\r
858 );\r
859\r
860/**\r
861 Set if UCHI should issue an interrupt on completion of the frame\r
862 in which this TD is executed\r
863\r
864 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
865 @param IsSet Whether HC should issue an interrupt on completion.\r
866\r
867**/\r
868VOID\r
869SetorClearTDControlIOC (\r
870 IN TD_STRUCT *PtrTDStruct,\r
871 IN BOOLEAN IsSet\r
872 );\r
873\r
874/**\r
875 Set if the TD is active and can be executed.\r
876\r
877 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
878 @param IsActive Whether the TD is active and can be executed.\r
879\r
880**/\r
881VOID\r
882SetTDStatusActiveorInactive (\r
883 IN TD_STRUCT *PtrTDStruct,\r
884 IN BOOLEAN IsActive\r
885 );\r
886\r
887/**\r
888 Specifies the maximum number of data bytes allowed for the transfer.\r
889\r
890 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
891 @param MaxLen The maximum number of data bytes allowed.\r
892\r
893 @retval The allowed maximum number of data.\r
894**/\r
895UINT16\r
896SetTDTokenMaxLength (\r
897 IN TD_STRUCT *PtrTDStruct,\r
898 IN UINT16 MaxLen\r
899 );\r
900\r
901/**\r
902 Set the data toggle bit to DATA1.\r
903\r
904 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
905\r
906**/\r
907VOID\r
908SetTDTokenDataToggle1 (\r
909 IN TD_STRUCT *PtrTDStruct\r
910 );\r
911\r
912/**\r
913 Set the data toggle bit to DATA0.\r
914\r
915 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
916\r
917**/\r
918VOID\r
919SetTDTokenDataToggle0 (\r
920 IN TD_STRUCT *PtrTDStruct\r
921 );\r
922\r
923/**\r
924 Set EndPoint Number the TD is targeting at.\r
925\r
926 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
927 @param EndPoint The Endport number of the target.\r
928\r
929**/\r
930VOID\r
931SetTDTokenEndPoint (\r
932 IN TD_STRUCT *PtrTDStruct,\r
933 IN UINTN EndPoint\r
934 );\r
935\r
936/**\r
937 Set Device Address the TD is targeting at.\r
938\r
939 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
940 @param DevAddr The Device Address of the target.\r
941\r
942**/\r
943VOID\r
944SetTDTokenDeviceAddress (\r
945 IN TD_STRUCT *PtrTDStruct,\r
946 IN UINTN DevAddr\r
947 );\r
948\r
949/**\r
950 Set Packet Identification the TD is targeting at.\r
951\r
952 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
953 @param PacketID The Packet Identification of the target.\r
954\r
955**/\r
956VOID\r
957SetTDTokenPacketID (\r
958 IN TD_STRUCT *PtrTDStruct,\r
959 IN UINT8 PacketID\r
960 );\r
961\r
962/**\r
963 Set the beginning address of the data buffer that will be used\r
964 during the transaction.\r
965\r
966 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
967\r
968**/\r
969VOID\r
970SetTDDataBuffer (\r
971 IN TD_STRUCT *PtrTDStruct\r
972 );\r
973\r
974/**\r
975 Detect whether the TD is active.\r
976\r
977 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
978\r
979 @retval The TD is active or not.\r
980\r
981**/\r
982BOOLEAN\r
983IsTDStatusActive (\r
984 IN TD_STRUCT *PtrTDStruct\r
985 );\r
986\r
987/**\r
988 Detect whether the TD is stalled.\r
989\r
990 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
991\r
992 @retval The TD is stalled or not.\r
993\r
994**/\r
995BOOLEAN\r
996IsTDStatusStalled (\r
997 IN TD_STRUCT *PtrTDStruct\r
998 );\r
999\r
1000/**\r
1001 Detect whether Data Buffer Error is happened.\r
1002\r
1003 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1004\r
1005 @retval The Data Buffer Error is happened or not.\r
1006\r
1007**/\r
1008BOOLEAN\r
1009IsTDStatusBufferError (\r
1010 IN TD_STRUCT *PtrTDStruct\r
1011 );\r
1012\r
1013/**\r
1014 Detect whether Babble Error is happened.\r
1015\r
1016 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1017\r
1018 @retval The Babble Error is happened or not.\r
1019\r
1020**/\r
1021BOOLEAN\r
1022IsTDStatusBabbleError (\r
1023 IN TD_STRUCT *PtrTDStruct\r
1024 );\r
1025\r
1026/**\r
1027 Detect whether NAK is received.\r
1028\r
1029 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1030\r
1031 @retval The NAK is received or not.\r
1032\r
1033**/\r
1034BOOLEAN\r
1035IsTDStatusNAKReceived (\r
1036 IN TD_STRUCT *PtrTDStruct\r
1037 );\r
1038\r
1039/**\r
1040 Detect whether CRC/Time Out Error is encountered.\r
1041\r
1042 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1043\r
1044 @retval The CRC/Time Out Error is encountered or not.\r
1045\r
1046**/\r
1047BOOLEAN\r
1048IsTDStatusCRCTimeOutError (\r
1049 IN TD_STRUCT *PtrTDStruct\r
1050 );\r
1051\r
1052/**\r
1053 Detect whether Bitstuff Error is received.\r
1054\r
1055 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1056\r
1057 @retval The Bitstuff Error is received or not.\r
1058\r
1059**/\r
1060BOOLEAN\r
1061IsTDStatusBitStuffError (\r
1062 IN TD_STRUCT *PtrTDStruct\r
1063 );\r
1064\r
1065/**\r
1066 Retrieve the actual number of bytes that were tansferred.\r
1067\r
1068 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1069\r
1070 @retval The actual number of bytes that were tansferred.\r
1071\r
1072**/\r
1073UINT16\r
1074GetTDStatusActualLength (\r
1075 IN TD_STRUCT *PtrTDStruct\r
1076 );\r
1077\r
1078/**\r
1079 Retrieve the information of whether the Link Pointer field is valid or not.\r
1080\r
1081 @param PtrTDStruct Place to store TD_STRUCT pointer.\r
1082\r
1083 @retval The linker pointer field is valid or not.\r
1084\r
1085**/\r
1086BOOLEAN\r
1087GetTDLinkPtrValidorInvalid (\r
1088 IN TD_STRUCT *PtrTDStruct\r
1089 );\r
1090\r
1091/**\r
1092 Count TD Number from PtrFirstTD.\r
1093\r
1094 @param PtrFirstTD Place to store TD_STRUCT pointer.\r
1095\r
1096 @retval The queued TDs number.\r
1097\r
1098**/\r
1099UINTN\r
1100CountTDsNumber (\r
1101 IN TD_STRUCT *PtrFirstTD\r
1102 );\r
1103\r
1104/**\r
1105 Link TD To QH.\r
1106\r
1107 @param PtrQH Place to store QH_STRUCT pointer.\r
1108 @param PtrTD Place to store TD_STRUCT pointer.\r
1109\r
1110**/\r
1111VOID\r
1112LinkTDToQH (\r
1113 IN QH_STRUCT *PtrQH,\r
1114 IN TD_STRUCT *PtrTD\r
1115 );\r
1116\r
1117/**\r
1118 Link TD To TD.\r
1119\r
1120 @param PtrPreTD Place to store TD_STRUCT pointer.\r
1121 @param PtrTD Place to store TD_STRUCT pointer.\r
1122\r
1123**/\r
1124VOID\r
1125LinkTDToTD (\r
1126 IN TD_STRUCT *PtrPreTD,\r
1127 IN TD_STRUCT *PtrTD\r
1128 );\r
1129\r
1130/**\r
1131 Execute Control Transfer.\r
1132\r
1133 @param UhcDev The UCHI device.\r
1134 @param PtrTD A pointer to TD_STRUCT data.\r
1135 @param ActualLen Actual transfer Length.\r
1136 @param TimeOut TimeOut value.\r
1137 @param TransferResult Transfer Result.\r
1138\r
1139 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
1140 @return EFI_TIMEOUT The transfer failed due to time out.\r
1141 @return EFI_SUCCESS The transfer finished OK.\r
1142\r
1143**/\r
1144EFI_STATUS\r
1145ExecuteControlTransfer (\r
1146 IN USB_UHC_DEV *UhcDev,\r
1147 IN TD_STRUCT *PtrTD,\r
1148 OUT UINTN *ActualLen,\r
1149 IN UINTN TimeOut,\r
1150 OUT UINT32 *TransferResult\r
1151 );\r
1152\r
1153/**\r
1154 Execute Bulk Transfer.\r
1155\r
1156 @param UhcDev The UCHI device.\r
1157 @param PtrTD A pointer to TD_STRUCT data.\r
1158 @param ActualLen Actual transfer Length.\r
1159 @param DataToggle DataToggle value.\r
1160 @param TimeOut TimeOut value.\r
1161 @param TransferResult Transfer Result.\r
1162\r
1163 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
1164 @return EFI_TIMEOUT The transfer failed due to time out.\r
1165 @return EFI_SUCCESS The transfer finished OK.\r
1166\r
1167**/\r
1168EFI_STATUS\r
1169ExecBulkTransfer (\r
1170 IN USB_UHC_DEV *UhcDev,\r
1171 IN TD_STRUCT *PtrTD,\r
1172 IN OUT UINTN *ActualLen,\r
1173 IN UINT8 *DataToggle,\r
1174 IN UINTN TimeOut,\r
1175 OUT UINT32 *TransferResult\r
1176 );\r
1177\r
1178/**\r
1179 Delete Queued TDs.\r
1180\r
1181 @param UhcDev The UCHI device.\r
1182 @param PtrFirstTD Place to store TD_STRUCT pointer.\r
1183\r
1184**/\r
1185VOID\r
1186DeleteQueuedTDs (\r
1187 IN USB_UHC_DEV *UhcDev,\r
1188 IN TD_STRUCT *PtrFirstTD\r
1189 );\r
1190\r
1191/**\r
1192 Check TDs Results.\r
1193\r
1194 @param PtrTD A pointer to TD_STRUCT data.\r
1195 @param Result The result to return.\r
1196 @param ErrTDPos The Error TD position.\r
1197 @param ActualTransferSize Actual transfer size.\r
1198\r
1199 @retval The TD is executed successfully or not.\r
1200\r
1201**/\r
1202BOOLEAN\r
1203CheckTDsResults (\r
1204 IN TD_STRUCT *PtrTD,\r
1205 OUT UINT32 *Result,\r
1206 OUT UINTN *ErrTDPos,\r
1207 OUT UINTN *ActualTransferSize\r
1208 );\r
1209\r
1210/**\r
1211 Create Memory Block.\r
1212\r
1213 @param UhcDev The UCHI device.\r
1214 @param MemoryHeader The Pointer to allocated memory block.\r
1215 @param MemoryBlockSizeInPages The page size of memory block to be allocated.\r
1216\r
1217 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1218 @retval EFI_SUCCESS Success.\r
1219\r
1220**/\r
1221EFI_STATUS\r
1222CreateMemoryBlock (\r
1223 IN USB_UHC_DEV *UhcDev,\r
1224 OUT MEMORY_MANAGE_HEADER **MemoryHeader,\r
1225 IN UINTN MemoryBlockSizeInPages\r
1226 );\r
1227\r
1228/**\r
1229 Initialize UHCI memory management.\r
1230\r
1231 @param UhcDev The UCHI device.\r
1232\r
1233 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1234 @retval EFI_SUCCESS Success.\r
1235\r
1236**/\r
1237EFI_STATUS\r
1238InitializeMemoryManagement (\r
1239 IN USB_UHC_DEV *UhcDev\r
1240 );\r
1241\r
1242/**\r
1243 Initialize UHCI memory management.\r
1244\r
1245 @param UhcDev The UCHI device.\r
1246 @param Pool Buffer pointer to store the buffer pointer.\r
1247 @param AllocSize The size of the pool to be allocated.\r
1248\r
1249 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1250 @retval EFI_SUCCESS Success.\r
1251\r
1252**/\r
1253EFI_STATUS\r
1254UhcAllocatePool (\r
1255 IN USB_UHC_DEV *UhcDev,\r
1256 OUT UINT8 **Pool,\r
1257 IN UINTN AllocSize\r
1258 );\r
1259\r
1260/**\r
1261 Alloc Memory In MemoryBlock.\r
1262\r
1263 @param MemoryHeader The pointer to memory manage header.\r
1264 @param Pool Buffer pointer to store the buffer pointer.\r
1265 @param NumberOfMemoryUnit The size of the pool to be allocated.\r
1266\r
1267 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.\r
1268 @retval EFI_SUCCESS Success.\r
1269\r
1270**/\r
1271EFI_STATUS\r
1272AllocMemInMemoryBlock (\r
1273 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
1274 OUT VOID **Pool,\r
1275 IN UINTN NumberOfMemoryUnit\r
1276 );\r
1277\r
1278/**\r
1279 Uhci Free Pool.\r
1280\r
1281 @param UhcDev The UHCI device.\r
1282 @param Pool A pointer to store the buffer address.\r
1283 @param AllocSize The size of the pool to be freed.\r
1284\r
1285**/\r
1286VOID\r
1287UhcFreePool (\r
1288 IN USB_UHC_DEV *UhcDev,\r
1289 IN UINT8 *Pool,\r
1290 IN UINTN AllocSize\r
1291 );\r
1292\r
1293/**\r
1294 Insert a new memory header into list.\r
1295\r
1296 @param MemoryHeader A pointer to the memory header list.\r
1297 @param NewMemoryHeader A new memory header to be inserted into the list.\r
1298\r
1299**/\r
1300VOID\r
1301InsertMemoryHeaderToList (\r
1302 IN MEMORY_MANAGE_HEADER *MemoryHeader,\r
1303 IN MEMORY_MANAGE_HEADER *NewMemoryHeader\r
1304 );\r
1305\r
1306/**\r
1307 Judge the memory block in the memory header is empty or not.\r
1308\r
1309 @param MemoryHeaderPtr A pointer to the memory header list.\r
1310\r
1311 @retval Whether the memory block in the memory header is empty or not.\r
1312\r
1313**/\r
1314BOOLEAN\r
1315IsMemoryBlockEmptied (\r
1316 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr\r
1317 );\r
1318\r
1319/**\r
1320 remove a memory header from list.\r
1321\r
1322 @param FirstMemoryHeader A pointer to the memory header list.\r
1323 @param FreeMemoryHeader A memory header to be removed into the list.\r
1324\r
1325**/\r
1326VOID\r
1327DelinkMemoryBlock (\r
1328 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,\r
1329 IN MEMORY_MANAGE_HEADER *FreeMemoryHeader\r
1330 );\r
1331\r
1332#endif\r
EFI Development Kit II mirror for PVE