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MdeModulePkg/Sd: Fix wrong response type of SD Deselect cmd
[mirror_edk2.git] / MdeModulePkg / Bus / Sd / SdBlockIoPei / SdHci.c
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48555339
FT		 1/** @file\r
2\r
3 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
4 This program and the accompanying materials\r
5 are licensed and made available under the terms and conditions of the BSD License\r
6 which accompanies this distribution. The full text of the license may be found at\r
7 http://opensource.org/licenses/bsd-license.php.\r
8\r
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12**/\r
13\r
14#include "SdBlockIoPei.h"\r
15\r
16/**\r
17 Read/Write specified SD host controller mmio register.\r
18\r
19 @param[in] Address The address of the mmio register to be read/written.\r
20 @param[in] Read A boolean to indicate it's read or write operation.\r
21 @param[in] Count The width of the mmio register in bytes.\r
22 Must be 1, 2 , 4 or 8 bytes.\r
23 @param[in, out] Data For read operations, the destination buffer to store\r
24 the results. For write operations, the source buffer\r
25 to write data from. The caller is responsible for\r
26 having ownership of the data buffer and ensuring its\r
27 size not less than Count bytes.\r
28\r
29 @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.\r
30 @retval EFI_SUCCESS The read/write operation succeeds.\r
31 @retval Others The read/write operation fails.\r
32\r
33**/\r
34EFI_STATUS\r
35EFIAPI\r
36SdPeimHcRwMmio (\r
37 IN UINTN Address,\r
38 IN BOOLEAN Read,\r
39 IN UINT8 Count,\r
40 IN OUT VOID *Data\r
41 )\r
42{\r
43 if ((Address == 0) || (Data == NULL)) {\r
44 return EFI_INVALID_PARAMETER;\r
45 }\r
46\r
47 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {\r
48 return EFI_INVALID_PARAMETER;\r
49 }\r
50\r
51 switch (Count) {\r
52 case 1:\r
53 if (Read) {\r
54 *(UINT8*)Data = MmioRead8 (Address);\r
55 } else {\r
56 MmioWrite8 (Address, *(UINT8*)Data);\r
57 }\r
58 break;\r
59 case 2:\r
60 if (Read) {\r
61 *(UINT16*)Data = MmioRead16 (Address);\r
62 } else {\r
63 MmioWrite16 (Address, *(UINT16*)Data);\r
64 }\r
65 break;\r
66 case 4:\r
67 if (Read) {\r
68 *(UINT32*)Data = MmioRead32 (Address);\r
69 } else {\r
70 MmioWrite32 (Address, *(UINT32*)Data);\r
71 }\r
72 break;\r
73 case 8:\r
74 if (Read) {\r
75 *(UINT64*)Data = MmioRead64 (Address);\r
76 } else {\r
77 MmioWrite64 (Address, *(UINT64*)Data);\r
78 }\r
79 break;\r
80 default:\r
81 ASSERT (FALSE);\r
82 return EFI_INVALID_PARAMETER;\r
83 }\r
84\r
85 return EFI_SUCCESS;\r
86}\r
87\r
88/**\r
89 Do OR operation with the value of the specified SD host controller mmio register.\r
90\r
91 @param[in] Address The address of the mmio register to be read/written.\r
92 @param[in] Count The width of the mmio register in bytes.\r
93 Must be 1, 2 , 4 or 8 bytes.\r
94 @param[in] OrData The pointer to the data used to do OR operation.\r
95 The caller is responsible for having ownership of\r
96 the data buffer and ensuring its size not less than\r
97 Count bytes.\r
98\r
99 @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.\r
100 @retval EFI_SUCCESS The OR operation succeeds.\r
101 @retval Others The OR operation fails.\r
102\r
103**/\r
104EFI_STATUS\r
105EFIAPI\r
106SdPeimHcOrMmio (\r
107 IN UINTN Address,\r
108 IN UINT8 Count,\r
109 IN VOID *OrData\r
110 )\r
111{\r
112 EFI_STATUS Status;\r
113 UINT64 Data;\r
114 UINT64 Or;\r
115\r
116 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);\r
117 if (EFI_ERROR (Status)) {\r
118 return Status;\r
119 }\r
120\r
121 if (Count == 1) {\r
122 Or = *(UINT8*) OrData;\r
123 } else if (Count == 2) {\r
124 Or = *(UINT16*) OrData;\r
125 } else if (Count == 4) {\r
126 Or = *(UINT32*) OrData;\r
127 } else if (Count == 8) {\r
128 Or = *(UINT64*) OrData;\r
129 } else {\r
130 return EFI_INVALID_PARAMETER;\r
131 }\r
132\r
133 Data |= Or;\r
134 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);\r
135\r
136 return Status;\r
137}\r
138\r
139/**\r
140 Do AND operation with the value of the specified SD host controller mmio register.\r
141\r
142 @param[in] Address The address of the mmio register to be read/written.\r
143 @param[in] Count The width of the mmio register in bytes.\r
144 Must be 1, 2 , 4 or 8 bytes.\r
145 @param[in] AndData The pointer to the data used to do AND operation.\r
146 The caller is responsible for having ownership of\r
147 the data buffer and ensuring its size not less than\r
148 Count bytes.\r
149\r
150 @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.\r
151 @retval EFI_SUCCESS The AND operation succeeds.\r
152 @retval Others The AND operation fails.\r
153\r
154**/\r
155EFI_STATUS\r
156EFIAPI\r
157SdPeimHcAndMmio (\r
158 IN UINTN Address,\r
159 IN UINT8 Count,\r
160 IN VOID *AndData\r
161 )\r
162{\r
163 EFI_STATUS Status;\r
164 UINT64 Data;\r
165 UINT64 And;\r
166\r
167 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);\r
168 if (EFI_ERROR (Status)) {\r
169 return Status;\r
170 }\r
171\r
172 if (Count == 1) {\r
173 And = *(UINT8*) AndData;\r
174 } else if (Count == 2) {\r
175 And = *(UINT16*) AndData;\r
176 } else if (Count == 4) {\r
177 And = *(UINT32*) AndData;\r
178 } else if (Count == 8) {\r
179 And = *(UINT64*) AndData;\r
180 } else {\r
181 return EFI_INVALID_PARAMETER;\r
182 }\r
183\r
184 Data &= And;\r
185 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);\r
186\r
187 return Status;\r
188}\r
189\r
190/**\r
191 Wait for the value of the specified MMIO register set to the test value.\r
192\r
193 @param[in] Address The address of the mmio register to be checked.\r
194 @param[in] Count The width of the mmio register in bytes.\r
195 Must be 1, 2, 4 or 8 bytes.\r
196 @param[in] MaskValue The mask value of memory.\r
197 @param[in] TestValue The test value of memory.\r
198\r
199 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r
200 @retval EFI_SUCCESS The MMIO register has expected value.\r
201 @retval Others The MMIO operation fails.\r
202\r
203**/\r
204EFI_STATUS\r
205EFIAPI\r
206SdPeimHcCheckMmioSet (\r
207 IN UINTN Address,\r
208 IN UINT8 Count,\r
209 IN UINT64 MaskValue,\r
210 IN UINT64 TestValue\r
211 )\r
212{\r
213 EFI_STATUS Status;\r
214 UINT64 Value;\r
215\r
216 //\r
217 // Access PCI MMIO space to see if the value is the tested one.\r
218 //\r
219 Value = 0;\r
220 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Value);\r
221 if (EFI_ERROR (Status)) {\r
222 return Status;\r
223 }\r
224\r
225 Value &= MaskValue;\r
226\r
227 if (Value == TestValue) {\r
228 return EFI_SUCCESS;\r
229 }\r
230\r
231 return EFI_NOT_READY;\r
232}\r
233\r
234/**\r
235 Wait for the value of the specified MMIO register set to the test value.\r
236\r
237 @param[in] Address The address of the mmio register to wait.\r
238 @param[in] Count The width of the mmio register in bytes.\r
239 Must be 1, 2, 4 or 8 bytes.\r
240 @param[in] MaskValue The mask value of memory.\r
241 @param[in] TestValue The test value of memory.\r
242 @param[in] Timeout The time out value for wait memory set, uses 1\r
243 microsecond as a unit.\r
244\r
245 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
246 range.\r
247 @retval EFI_SUCCESS The MMIO register has expected value.\r
248 @retval Others The MMIO operation fails.\r
249\r
250**/\r
251EFI_STATUS\r
252EFIAPI\r
253SdPeimHcWaitMmioSet (\r
254 IN UINTN Address,\r
255 IN UINT8 Count,\r
256 IN UINT64 MaskValue,\r
257 IN UINT64 TestValue,\r
258 IN UINT64 Timeout\r
259 )\r
260{\r
261 EFI_STATUS Status;\r
262 BOOLEAN InfiniteWait;\r
263\r
264 if (Timeout == 0) {\r
265 InfiniteWait = TRUE;\r
266 } else {\r
267 InfiniteWait = FALSE;\r
268 }\r
269\r
270 while (InfiniteWait || (Timeout > 0)) {\r
271 Status = SdPeimHcCheckMmioSet (\r
272 Address,\r
273 Count,\r
274 MaskValue,\r
275 TestValue\r
276 );\r
277 if (Status != EFI_NOT_READY) {\r
278 return Status;\r
279 }\r
280\r
281 //\r
282 // Stall for 1 microsecond.\r
283 //\r
284 MicroSecondDelay (1);\r
285\r
286 Timeout--;\r
287 }\r
288\r
289 return EFI_TIMEOUT;\r
290}\r
291\r
292/**\r
293 Software reset the specified SD host controller and enable all interrupts.\r
294\r
295 @param[in] Bar The mmio base address of the slot to be accessed.\r
296\r
297 @retval EFI_SUCCESS The software reset executes successfully.\r
298 @retval Others The software reset fails.\r
299\r
300**/\r
301EFI_STATUS\r
302SdPeimHcReset (\r
303 IN UINTN Bar\r
304 )\r
305{\r
306 EFI_STATUS Status;\r
307 UINT8 SwReset;\r
308\r
309 SwReset = 0xFF;\r
310 Status = SdPeimHcRwMmio (Bar + SD_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);\r
311\r
312 if (EFI_ERROR (Status)) {\r
313 DEBUG ((EFI_D_ERROR, "SdPeimHcReset: write full 1 fails: %r\n", Status));\r
314 return Status;\r
315 }\r
316\r
317 Status = SdPeimHcWaitMmioSet (\r
318 Bar + SD_HC_SW_RST,\r
319 sizeof (SwReset),\r
320 0xFF,\r
321 0x00,\r
322 SD_TIMEOUT\r
323 );\r
324 if (EFI_ERROR (Status)) {\r
325 DEBUG ((EFI_D_INFO, "SdPeimHcReset: reset done with %r\n", Status));\r
326 return Status;\r
327 }\r
328 //\r
329 // Enable all interrupt after reset all.\r
330 //\r
331 Status = SdPeimHcEnableInterrupt (Bar);\r
332\r
333 return Status;\r
334}\r
335\r
336/**\r
337 Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
338 register.\r
339\r
340 @param[in] Bar The mmio base address of the slot to be accessed.\r
341\r
342 @retval EFI_SUCCESS The operation executes successfully.\r
343 @retval Others The operation fails.\r
344\r
345**/\r
346EFI_STATUS\r
347SdPeimHcEnableInterrupt (\r
348 IN UINTN Bar\r
349 )\r
350{\r
351 EFI_STATUS Status;\r
352 UINT16 IntStatus;\r
353\r
354 //\r
355 // Enable all bits in Error Interrupt Status Enable Register\r
356 //\r
357 IntStatus = 0xFFFF;\r
358 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
359 if (EFI_ERROR (Status)) {\r
360 return Status;\r
361 }\r
362 //\r
363 // Enable all bits in Normal Interrupt Status Enable Register\r
364 //\r
365 IntStatus = 0xFFFF;\r
366 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
367\r
368 return Status;\r
369}\r
370\r
371/**\r
372 Get the capability data from the specified slot.\r
373\r
374 @param[in] Bar The mmio base address of the slot to be accessed.\r
375 @param[out] Capability The buffer to store the capability data.\r
376\r
377 @retval EFI_SUCCESS The operation executes successfully.\r
378 @retval Others The operation fails.\r
379\r
380**/\r
381EFI_STATUS\r
382SdPeimHcGetCapability (\r
383 IN UINTN Bar,\r
384 OUT SD_HC_SLOT_CAP *Capability\r
385 )\r
386{\r
387 EFI_STATUS Status;\r
388 UINT64 Cap;\r
389\r
390 Status = SdPeimHcRwMmio (Bar + SD_HC_CAP, TRUE, sizeof (Cap), &Cap);\r
391 if (EFI_ERROR (Status)) {\r
392 return Status;\r
393 }\r
394\r
395 CopyMem (Capability, &Cap, sizeof (Cap));\r
396\r
397 return EFI_SUCCESS;\r
398}\r
399\r
400/**\r
401 Detect whether there is a SD card attached at the specified SD host controller\r
402 slot.\r
403\r
404 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
405\r
406 @param[in] Bar The mmio base address of the slot to be accessed.\r
407\r
408 @retval EFI_SUCCESS There is a SD card attached.\r
409 @retval EFI_NO_MEDIA There is not a SD card attached.\r
410 @retval Others The detection fails.\r
411\r
412**/\r
413EFI_STATUS\r
414SdPeimHcCardDetect (\r
415 IN UINTN Bar\r
416 )\r
417{\r
418 EFI_STATUS Status;\r
419 UINT16 Data;\r
420 UINT32 PresentState;\r
421\r
422 //\r
423 // Check Normal Interrupt Status Register\r
424 //\r
425 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r
426 if (EFI_ERROR (Status)) {\r
427 return Status;\r
428 }\r
429\r
430 if ((Data & (BIT6 | BIT7)) != 0) {\r
431 //\r
432 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r
433 //\r
434 Data &= BIT6 | BIT7;\r
435 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r
436 if (EFI_ERROR (Status)) {\r
437 return Status;\r
438 }\r
439 }\r
440\r
441 //\r
442 // Check Present State Register to see if there is a card presented.\r
443 //\r
444 Status = SdPeimHcRwMmio (Bar + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
445 if (EFI_ERROR (Status)) {\r
446 return Status;\r
447 }\r
448\r
449 if ((PresentState & BIT16) != 0) {\r
450 return EFI_SUCCESS;\r
451 } else {\r
452 return EFI_NO_MEDIA;\r
453 }\r
454}\r
455\r
456/**\r
457 Stop SD card clock.\r
458\r
459 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
460\r
461 @param[in] Bar The mmio base address of the slot to be accessed.\r
462\r
463 @retval EFI_SUCCESS Succeed to stop SD clock.\r
464 @retval Others Fail to stop SD clock.\r
465\r
466**/\r
467EFI_STATUS\r
468SdPeimHcStopClock (\r
469 IN UINTN Bar\r
470 )\r
471{\r
472 EFI_STATUS Status;\r
473 UINT32 PresentState;\r
474 UINT16 ClockCtrl;\r
475\r
476 //\r
477 // Ensure no SD transactions are occurring on the SD Bus by\r
478 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r
479 // in the Present State register to be 0.\r
480 //\r
481 Status = SdPeimHcWaitMmioSet (\r
482 Bar + SD_HC_PRESENT_STATE,\r
483 sizeof (PresentState),\r
484 BIT0 | BIT1,\r
485 0,\r
486 SD_TIMEOUT\r
487 );\r
488 if (EFI_ERROR (Status)) {\r
489 return Status;\r
490 }\r
491\r
492 //\r
493 // Set SD Clock Enable in the Clock Control register to 0\r
494 //\r
495 ClockCtrl = (UINT16)~BIT2;\r
496 Status = SdPeimHcAndMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
497\r
498 return Status;\r
499}\r
500\r
501/**\r
502 SD card clock supply.\r
503\r
504 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
505\r
506 @param[in] Bar The mmio base address of the slot to be accessed.\r
507 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
508\r
509 @retval EFI_SUCCESS The clock is supplied successfully.\r
510 @retval Others The clock isn't supplied successfully.\r
511\r
512**/\r
513EFI_STATUS\r
514SdPeimHcClockSupply (\r
515 IN UINTN Bar,\r
516 IN UINT64 ClockFreq\r
517 )\r
518{\r
519 EFI_STATUS Status;\r
520 SD_HC_SLOT_CAP Capability;\r
521 UINT32 BaseClkFreq;\r
522 UINT32 SettingFreq;\r
523 UINT32 Divisor;\r
524 UINT32 Remainder;\r
525 UINT16 ControllerVer;\r
526 UINT16 ClockCtrl;\r
527\r
528 //\r
529 // Calculate a divisor for SD clock frequency\r
530 //\r
531 Status = SdPeimHcGetCapability (Bar, &Capability);\r
532 if (EFI_ERROR (Status)) {\r
533 return Status;\r
534 }\r
535 ASSERT (Capability.BaseClkFreq != 0);\r
536\r
537 BaseClkFreq = Capability.BaseClkFreq;\r
538 if ((ClockFreq > (BaseClkFreq * 1000)) || (ClockFreq == 0)) {\r
539 return EFI_INVALID_PARAMETER;\r
540 }\r
541 //\r
542 // Calculate the divisor of base frequency.\r
543 //\r
544 Divisor = 0;\r
545 SettingFreq = BaseClkFreq * 1000;\r
546 while (ClockFreq < SettingFreq) {\r
547 Divisor++;\r
548\r
549 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r
550 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r
551 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r
552 break;\r
553 }\r
554 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r
555 SettingFreq ++;\r
556 }\r
557 }\r
558\r
559 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r
560\r
561 Status = SdPeimHcRwMmio (Bar + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r
562 if (EFI_ERROR (Status)) {\r
563 return Status;\r
564 }\r
565 //\r
566 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
567 //\r
568 if ((ControllerVer & 0xFF) == 2) {\r
569 ASSERT (Divisor <= 0x3FF);\r
570 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
571 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
572 //\r
573 // Only the most significant bit can be used as divisor.\r
574 //\r
575 if (((Divisor - 1) & Divisor) != 0) {\r
576 Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r
577 }\r
578 ASSERT (Divisor <= 0x80);\r
579 ClockCtrl = (Divisor & 0xFF) << 8;\r
580 } else {\r
581 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r
582 return EFI_UNSUPPORTED;\r
583 }\r
584\r
585 //\r
586 // Stop bus clock at first\r
587 //\r
588 Status = SdPeimHcStopClock (Bar);\r
589 if (EFI_ERROR (Status)) {\r
590 return Status;\r
591 }\r
592\r
593 //\r
594 // Supply clock frequency with specified divisor\r
595 //\r
596 ClockCtrl |= BIT0;\r
597 Status = SdPeimHcRwMmio (Bar + SD_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
598 if (EFI_ERROR (Status)) {\r
599 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r
600 return Status;\r
601 }\r
602\r
603 //\r
604 // Wait Internal Clock Stable in the Clock Control register to be 1\r
605 //\r
606 Status = SdPeimHcWaitMmioSet (\r
607 Bar + SD_HC_CLOCK_CTRL,\r
608 sizeof (ClockCtrl),\r
609 BIT1,\r
610 BIT1,\r
611 SD_TIMEOUT\r
612 );\r
613 if (EFI_ERROR (Status)) {\r
614 return Status;\r
615 }\r
616\r
617 //\r
618 // Set SD Clock Enable in the Clock Control register to 1\r
619 //\r
620 ClockCtrl = BIT2;\r
621 Status = SdPeimHcOrMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
622\r
623 return Status;\r
624}\r
625\r
626/**\r
627 SD bus power control.\r
628\r
629 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
630\r
631 @param[in] Bar The mmio base address of the slot to be accessed.\r
632 @param[in] PowerCtrl The value setting to the power control register.\r
633\r
634 @retval TRUE There is a SD card attached.\r
635 @retval FALSE There is no a SD card attached.\r
636\r
637**/\r
638EFI_STATUS\r
639SdPeimHcPowerControl (\r
640 IN UINTN Bar,\r
641 IN UINT8 PowerCtrl\r
642 )\r
643{\r
644 EFI_STATUS Status;\r
645\r
646 //\r
647 // Clr SD Bus Power\r
648 //\r
649 PowerCtrl &= (UINT8)~BIT0;\r
650 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
651 if (EFI_ERROR (Status)) {\r
652 return Status;\r
653 }\r
654\r
655 //\r
656 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
657 //\r
658 PowerCtrl |= BIT0;\r
659 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
660\r
661 return Status;\r
662}\r
663\r
664/**\r
665 Set the SD bus width.\r
666\r
667 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
668\r
669 @param[in] Bar The mmio base address of the slot to be accessed.\r
670 @param[in] BusWidth The bus width used by the SD device, it must be 1, 4 or 8.\r
671\r
672 @retval EFI_SUCCESS The bus width is set successfully.\r
673 @retval Others The bus width isn't set successfully.\r
674\r
675**/\r
676EFI_STATUS\r
677SdPeimHcSetBusWidth (\r
678 IN UINTN Bar,\r
679 IN UINT16 BusWidth\r
680 )\r
681{\r
682 EFI_STATUS Status;\r
683 UINT8 HostCtrl1;\r
684\r
685 if (BusWidth == 1) {\r
686 HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r
687 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
688 } else if (BusWidth == 4) {\r
689 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
690 if (EFI_ERROR (Status)) {\r
691 return Status;\r
692 }\r
693 HostCtrl1 |= BIT1;\r
694 HostCtrl1 &= (UINT8)~BIT5;\r
695 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
696 } else if (BusWidth == 8) {\r
697 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
698 if (EFI_ERROR (Status)) {\r
699 return Status;\r
700 }\r
701 HostCtrl1 &= (UINT8)~BIT1;\r
702 HostCtrl1 |= BIT5;\r
703 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
704 } else {\r
705 ASSERT (FALSE);\r
706 return EFI_INVALID_PARAMETER;\r
707 }\r
708\r
709 return Status;\r
710}\r
711\r
712/**\r
713 Supply SD card with lowest clock frequency at initialization.\r
714\r
715 @param[in] Bar The mmio base address of the slot to be accessed.\r
716\r
717 @retval EFI_SUCCESS The clock is supplied successfully.\r
718 @retval Others The clock isn't supplied successfully.\r
719\r
720**/\r
721EFI_STATUS\r
722SdPeimHcInitClockFreq (\r
723 IN UINTN Bar\r
724 )\r
725{\r
726 EFI_STATUS Status;\r
727 SD_HC_SLOT_CAP Capability;\r
728 UINT32 InitFreq;\r
729\r
730 //\r
731 // Calculate a divisor for SD clock frequency\r
732 //\r
733 Status = SdPeimHcGetCapability (Bar, &Capability);\r
734 if (EFI_ERROR (Status)) {\r
735 return Status;\r
736 }\r
737\r
738 if (Capability.BaseClkFreq == 0) {\r
739 //\r
740 // Don't support get Base Clock Frequency information via another method\r
741 //\r
742 return EFI_UNSUPPORTED;\r
743 }\r
744 //\r
745 // Supply 400KHz clock frequency at initialization phase.\r
746 //\r
747 InitFreq = 400;\r
748 Status = SdPeimHcClockSupply (Bar, InitFreq);\r
749 return Status;\r
750}\r
751\r
752/**\r
753 Supply SD card with maximum voltage at initialization.\r
754\r
755 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
756\r
757 @param[in] Bar The mmio base address of the slot to be accessed.\r
758\r
759 @retval EFI_SUCCESS The voltage is supplied successfully.\r
760 @retval Others The voltage isn't supplied successfully.\r
761\r
762**/\r
763EFI_STATUS\r
764SdPeimHcInitPowerVoltage (\r
765 IN UINTN Bar\r
766 )\r
767{\r
768 EFI_STATUS Status;\r
769 SD_HC_SLOT_CAP Capability;\r
770 UINT8 MaxVoltage;\r
771 UINT8 HostCtrl2;\r
772\r
773 //\r
774 // Get the support voltage of the Host Controller\r
775 //\r
776 Status = SdPeimHcGetCapability (Bar, &Capability);\r
777 if (EFI_ERROR (Status)) {\r
778 return Status;\r
779 }\r
780 //\r
781 // Calculate supported maximum voltage according to SD Bus Voltage Select\r
782 //\r
783 if (Capability.Voltage33 != 0) {\r
784 //\r
785 // Support 3.3V\r
786 //\r
787 MaxVoltage = 0x0E;\r
788 } else if (Capability.Voltage30 != 0) {\r
789 //\r
790 // Support 3.0V\r
791 //\r
792 MaxVoltage = 0x0C;\r
793 } else if (Capability.Voltage18 != 0) {\r
794 //\r
795 // Support 1.8V\r
796 //\r
797 MaxVoltage = 0x0A;\r
798 HostCtrl2 = BIT3;\r
799 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
800 if (EFI_ERROR (Status)) {\r
801 return Status;\r
802 }\r
803 MicroSecondDelay (5000);\r
804 } else {\r
805 ASSERT (FALSE);\r
806 return EFI_DEVICE_ERROR;\r
807 }\r
808\r
809 //\r
810 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
811 //\r
812 Status = SdPeimHcPowerControl (Bar, MaxVoltage);\r
813\r
814 return Status;\r
815}\r
816\r
817/**\r
818 Initialize the Timeout Control register with most conservative value at initialization.\r
819\r
820 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
821\r
822 @param[in] Bar The mmio base address of the slot to be accessed.\r
823\r
824 @retval EFI_SUCCESS The timeout control register is configured successfully.\r
825 @retval Others The timeout control register isn't configured successfully.\r
826\r
827**/\r
828EFI_STATUS\r
829SdPeimHcInitTimeoutCtrl (\r
830 IN UINTN Bar\r
831 )\r
832{\r
833 EFI_STATUS Status;\r
834 UINT8 Timeout;\r
835\r
836 Timeout = 0x0E;\r
837 Status = SdPeimHcRwMmio (Bar + SD_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r
838\r
839 return Status;\r
840}\r
841\r
842/**\r
843 Initial SD host controller with lowest clock frequency, max power and max timeout value\r
844 at initialization.\r
845\r
846 @param[in] Bar The mmio base address of the slot to be accessed.\r
847\r
848 @retval EFI_SUCCESS The host controller is initialized successfully.\r
849 @retval Others The host controller isn't initialized successfully.\r
850\r
851**/\r
852EFI_STATUS\r
853SdPeimHcInitHost (\r
854 IN UINTN Bar\r
855 )\r
856{\r
857 EFI_STATUS Status;\r
858\r
859 Status = SdPeimHcInitClockFreq (Bar);\r
860 if (EFI_ERROR (Status)) {\r
861 return Status;\r
862 }\r
863\r
864 Status = SdPeimHcInitPowerVoltage (Bar);\r
865 if (EFI_ERROR (Status)) {\r
866 return Status;\r
867 }\r
868\r
869 Status = SdPeimHcInitTimeoutCtrl (Bar);\r
870 return Status;\r
871}\r
872\r
873/**\r
874 Turn on/off LED.\r
875\r
876 @param[in] Bar The mmio base address of the slot to be accessed.\r
877 @param[in] On The boolean to turn on/off LED.\r
878\r
879 @retval EFI_SUCCESS The LED is turned on/off successfully.\r
880 @retval Others The LED isn't turned on/off successfully.\r
881\r
882**/\r
883EFI_STATUS\r
884SdPeimHcLedOnOff (\r
885 IN UINTN Bar,\r
886 IN BOOLEAN On\r
887 )\r
888{\r
889 EFI_STATUS Status;\r
890 UINT8 HostCtrl1;\r
891\r
892 if (On) {\r
893 HostCtrl1 = BIT0;\r
894 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
895 } else {\r
896 HostCtrl1 = (UINT8)~BIT0;\r
897 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
898 }\r
899\r
900 return Status;\r
901}\r
902\r
903/**\r
904 Build ADMA descriptor table for transfer.\r
905\r
906 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.\r
907\r
908 @param[in] Trb The pointer to the SD_TRB instance.\r
909\r
910 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r
911 @retval Others The ADMA descriptor table isn't created successfully.\r
912\r
913**/\r
914EFI_STATUS\r
915BuildAdmaDescTable (\r
916 IN SD_TRB *Trb\r
917 )\r
918{\r
919 EFI_PHYSICAL_ADDRESS Data;\r
920 UINT64 DataLen;\r
921 UINT64 Entries;\r
922 UINT32 Index;\r
923 UINT64 Remaining;\r
924 UINT32 Address;\r
925\r
926 Data = (EFI_PHYSICAL_ADDRESS)(UINTN)Trb->Data;\r
927 DataLen = Trb->DataLen;\r
928 //\r
929 // Only support 32bit ADMA Descriptor Table\r
930 //\r
931 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r
932 return EFI_INVALID_PARAMETER;\r
933 }\r
934 //\r
935 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
936 // for 32-bit address descriptor table.\r
937 //\r
938 if ((Data & (BIT0 | BIT1)) != 0) {\r
939 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
940 }\r
941\r
942 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);\r
943\r
944 Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (SD_HC_ADMA_DESC_LINE));\r
945 Trb->AdmaDesc = SdPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);\r
946 if (Trb->AdmaDesc == NULL) {\r
947 return EFI_OUT_OF_RESOURCES;\r
948 }\r
949\r
950 Remaining = DataLen;\r
951 Address = (UINT32)Data;\r
952 for (Index = 0; Index < Entries; Index++) {\r
953 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r
954 Trb->AdmaDesc[Index].Valid = 1;\r
955 Trb->AdmaDesc[Index].Act = 2;\r
956 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;\r
957 Trb->AdmaDesc[Index].Address = Address;\r
958 break;\r
959 } else {\r
960 Trb->AdmaDesc[Index].Valid = 1;\r
961 Trb->AdmaDesc[Index].Act = 2;\r
962 Trb->AdmaDesc[Index].Length = 0;\r
963 Trb->AdmaDesc[Index].Address = Address;\r
964 }\r
965\r
966 Remaining -= ADMA_MAX_DATA_PER_LINE;\r
967 Address += ADMA_MAX_DATA_PER_LINE;\r
968 }\r
969\r
970 //\r
971 // Set the last descriptor line as end of descriptor table\r
972 //\r
973 Trb->AdmaDesc[Index].End = 1;\r
974 return EFI_SUCCESS;\r
975}\r
976\r
977/**\r
978 Create a new TRB for the SD cmd request.\r
979\r
980 @param[in] Slot The slot number of the SD card to send the command to.\r
981 @param[in] Packet A pointer to the SD command data structure.\r
982\r
983 @return Created Trb or NULL.\r
984\r
985**/\r
986SD_TRB *\r
987SdPeimCreateTrb (\r
988 IN SD_PEIM_HC_SLOT *Slot,\r
989 IN SD_COMMAND_PACKET *Packet\r
990 )\r
991{\r
992 SD_TRB *Trb;\r
993 EFI_STATUS Status;\r
994 SD_HC_SLOT_CAP Capability;\r
995\r
996 //\r
997 // Calculate a divisor for SD clock frequency\r
998 //\r
999 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);\r
1000 if (EFI_ERROR (Status)) {\r
1001 return NULL;\r
1002 }\r
1003\r
1004 Trb = SdPeimAllocateMem (Slot->Private->Pool, sizeof (SD_TRB));\r
1005 if (Trb == NULL) {\r
1006 return NULL;\r
1007 }\r
1008\r
1009 Trb->Slot = Slot;\r
1010 Trb->BlockSize = 0x200;\r
1011 Trb->Packet = Packet;\r
1012 Trb->Timeout = Packet->Timeout;\r
1013\r
1014 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r
1015 Trb->Data = Packet->InDataBuffer;\r
1016 Trb->DataLen = Packet->InTransferLength;\r
1017 Trb->Read = TRUE;\r
1018 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r
1019 Trb->Data = Packet->OutDataBuffer;\r
1020 Trb->DataLen = Packet->OutTransferLength;\r
1021 Trb->Read = FALSE;\r
1022 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r
1023 Trb->Data = NULL;\r
1024 Trb->DataLen = 0;\r
1025 } else {\r
1026 goto Error;\r
1027 }\r
1028\r
1029 if ((Trb->DataLen % Trb->BlockSize) != 0) {\r
1030 if (Trb->DataLen < Trb->BlockSize) {\r
1031 Trb->BlockSize = (UINT16)Trb->DataLen;\r
1032 }\r
1033 }\r
1034\r
1035 if (Trb->DataLen == 0) {\r
1036 Trb->Mode = SdNoData;\r
1037 } else if (Capability.Adma2 != 0) {\r
1038 Trb->Mode = SdAdmaMode;\r
1039 Status = BuildAdmaDescTable (Trb);\r
1040 if (EFI_ERROR (Status)) {\r
1041 goto Error;\r
1042 }\r
1043 } else if (Capability.Sdma != 0) {\r
1044 Trb->Mode = SdSdmaMode;\r
1045 } else {\r
1046 Trb->Mode = SdPioMode;\r
1047 }\r
1048\r
1049 return Trb;\r
1050\r
1051Error:\r
1052 SdPeimFreeTrb (Trb);\r
1053 return NULL;\r
1054}\r
1055\r
1056/**\r
1057 Free the resource used by the TRB.\r
1058\r
1059 @param[in] Trb The pointer to the SD_TRB instance.\r
1060\r
1061**/\r
1062VOID\r
1063SdPeimFreeTrb (\r
1064 IN SD_TRB *Trb\r
1065 )\r
1066{\r
1067 if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {\r
1068 SdPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);\r
1069 }\r
1070\r
1071 if (Trb != NULL) {\r
1072 SdPeimFreeMem (Trb->Slot->Private->Pool, Trb, sizeof (SD_TRB));\r
1073 }\r
1074 return;\r
1075}\r
1076\r
1077/**\r
1078 Check if the env is ready for execute specified TRB.\r
1079\r
1080 @param[in] Bar The mmio base address of the slot to be accessed.\r
1081 @param[in] Trb The pointer to the SD_TRB instance.\r
1082\r
1083 @retval EFI_SUCCESS The env is ready for TRB execution.\r
1084 @retval EFI_NOT_READY The env is not ready for TRB execution.\r
1085 @retval Others Some erros happen.\r
1086\r
1087**/\r
1088EFI_STATUS\r
1089SdPeimCheckTrbEnv (\r
1090 IN UINTN Bar,\r
1091 IN SD_TRB *Trb\r
1092 )\r
1093{\r
1094 EFI_STATUS Status;\r
1095 SD_COMMAND_PACKET *Packet;\r
1096 UINT32 PresentState;\r
1097\r
1098 Packet = Trb->Packet;\r
1099\r
1100 if ((Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) ||\r
1101 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR1b) ||\r
1102 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR5b)) {\r
1103 //\r
1104 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r
1105 // the Present State register to be 0\r
1106 //\r
1107 PresentState = BIT0 | BIT1;\r
1108 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {\r
1109 PresentState = BIT0;\r
1110 }\r
1111 } else {\r
1112 //\r
1113 // Wait Command Inhibit (CMD) in the Present State register\r
1114 // to be 0\r
1115 //\r
1116 PresentState = BIT0;\r
1117 }\r
1118\r
1119 Status = SdPeimHcCheckMmioSet (\r
1120 Bar + SD_HC_PRESENT_STATE,\r
1121 sizeof (PresentState),\r
1122 PresentState,\r
1123 0\r
1124 );\r
1125\r
1126 return Status;\r
1127}\r
1128\r
1129/**\r
1130 Wait for the env to be ready for execute specified TRB.\r
1131\r
1132 @param[in] Bar The mmio base address of the slot to be accessed.\r
1133 @param[in] Trb The pointer to the SD_TRB instance.\r
1134\r
1135 @retval EFI_SUCCESS The env is ready for TRB execution.\r
1136 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r
1137 @retval Others Some erros happen.\r
1138\r
1139**/\r
1140EFI_STATUS\r
1141SdPeimWaitTrbEnv (\r
1142 IN UINTN Bar,\r
1143 IN SD_TRB *Trb\r
1144 )\r
1145{\r
1146 EFI_STATUS Status;\r
1147 SD_COMMAND_PACKET *Packet;\r
1148 UINT64 Timeout;\r
1149 BOOLEAN InfiniteWait;\r
1150\r
1151 //\r
1152 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
1153 //\r
1154 Packet = Trb->Packet;\r
1155 Timeout = Packet->Timeout;\r
1156 if (Timeout == 0) {\r
1157 InfiniteWait = TRUE;\r
1158 } else {\r
1159 InfiniteWait = FALSE;\r
1160 }\r
1161\r
1162 while (InfiniteWait || (Timeout > 0)) {\r
1163 //\r
1164 // Check Trb execution result by reading Normal Interrupt Status register.\r
1165 //\r
1166 Status = SdPeimCheckTrbEnv (Bar, Trb);\r
1167 if (Status != EFI_NOT_READY) {\r
1168 return Status;\r
1169 }\r
1170 //\r
1171 // Stall for 1 microsecond.\r
1172 //\r
1173 MicroSecondDelay (1);\r
1174\r
1175 Timeout--;\r
1176 }\r
1177\r
1178 return EFI_TIMEOUT;\r
1179}\r
1180\r
1181/**\r
1182 Execute the specified TRB.\r
1183\r
1184 @param[in] Bar The mmio base address of the slot to be accessed.\r
1185 @param[in] Trb The pointer to the SD_TRB instance.\r
1186\r
1187 @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r
1188 @retval Others Some erros happen when sending this request to the host controller.\r
1189\r
1190**/\r
1191EFI_STATUS\r
1192SdPeimExecTrb (\r
1193 IN UINTN Bar,\r
1194 IN SD_TRB *Trb\r
1195 )\r
1196{\r
1197 EFI_STATUS Status;\r
1198 SD_COMMAND_PACKET *Packet;\r
1199 UINT16 Cmd;\r
1200 UINT16 IntStatus;\r
1201 UINT32 Argument;\r
1202 UINT16 BlkCount;\r
1203 UINT16 BlkSize;\r
1204 UINT16 TransMode;\r
1205 UINT8 HostCtrl1;\r
1206 UINT32 SdmaAddr;\r
1207 UINT64 AdmaAddr;\r
1208\r
1209 Packet = Trb->Packet;\r
1210 //\r
1211 // Clear all bits in Error Interrupt Status Register\r
1212 //\r
1213 IntStatus = 0xFFFF;\r
1214 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
1215 if (EFI_ERROR (Status)) {\r
1216 return Status;\r
1217 }\r
1218 //\r
1219 // Clear all bits in Normal Interrupt Status Register\r
1220 //\r
1221 IntStatus = 0xFFFF;\r
1222 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
1223 if (EFI_ERROR (Status)) {\r
1224 return Status;\r
1225 }\r
1226 //\r
1227 // Set Host Control 1 register DMA Select field\r
1228 //\r
1229 if (Trb->Mode == SdAdmaMode) {\r
1230 HostCtrl1 = BIT4;\r
1231 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
1232 if (EFI_ERROR (Status)) {\r
1233 return Status;\r
1234 }\r
1235 }\r
1236\r
1237 SdPeimHcLedOnOff (Bar, TRUE);\r
1238\r
1239 if (Trb->Mode == SdSdmaMode) {\r
1240 if ((UINT64)(UINTN)Trb->Data >= 0x100000000ul) {\r
1241 return EFI_INVALID_PARAMETER;\r
1242 }\r
1243\r
1244 SdmaAddr = (UINT32)(UINTN)Trb->Data;\r
1245 Status = SdPeimHcRwMmio (Bar + SD_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);\r
1246 if (EFI_ERROR (Status)) {\r
1247 return Status;\r
1248 }\r
1249 } else if (Trb->Mode == SdAdmaMode) {\r
1250 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;\r
1251 Status = SdPeimHcRwMmio (Bar + SD_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r
1252 if (EFI_ERROR (Status)) {\r
1253 return Status;\r
1254 }\r
1255 }\r
1256\r
1257 BlkSize = Trb->BlockSize;\r
1258 if (Trb->Mode == SdSdmaMode) {\r
1259 //\r
1260 // Set SDMA boundary to be 512K bytes.\r
1261 //\r
1262 BlkSize |= 0x7000;\r
1263 }\r
1264\r
1265 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r
1266 if (EFI_ERROR (Status)) {\r
1267 return Status;\r
1268 }\r
1269\r
1270 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r
1271 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r
1272 if (EFI_ERROR (Status)) {\r
1273 return Status;\r
1274 }\r
1275\r
1276 Argument = Packet->SdCmdBlk->CommandArgument;\r
1277 Status = SdPeimHcRwMmio (Bar + SD_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r
1278 if (EFI_ERROR (Status)) {\r
1279 return Status;\r
1280 }\r
1281\r
1282 TransMode = 0;\r
1283 if (Trb->Mode != SdNoData) {\r
1284 if (Trb->Mode != SdPioMode) {\r
1285 TransMode |= BIT0;\r
1286 }\r
1287 if (Trb->Read) {\r
1288 TransMode |= BIT4;\r
1289 }\r
1290 if (BlkCount != 0) {\r
1291 TransMode |= BIT5 | BIT1;\r
1292 }\r
1293 if (BlkCount > 1) {\r
1294 TransMode |= BIT2;\r
1295 }\r
1296 }\r
1297\r
1298 Status = SdPeimHcRwMmio (Bar + SD_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r
1299 if (EFI_ERROR (Status)) {\r
1300 return Status;\r
1301 }\r
1302\r
1303 Cmd = (UINT16)LShiftU64(Packet->SdCmdBlk->CommandIndex, 8);\r
1304 if (Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) {\r
1305 Cmd |= BIT5;\r
1306 }\r
1307 //\r
1308 // Convert ResponseType to value\r
1309 //\r
1310 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {\r
1311 switch (Packet->SdCmdBlk->ResponseType) {\r
1312 case SdResponseTypeR1:\r
1313 case SdResponseTypeR5:\r
1314 case SdResponseTypeR6:\r
1315 case SdResponseTypeR7:\r
1316 Cmd |= (BIT1 | BIT3 | BIT4);\r
1317 break;\r
1318 case SdResponseTypeR2:\r
1319 Cmd |= (BIT0 | BIT3);\r
1320 break;\r
1321 case SdResponseTypeR3:\r
1322 case SdResponseTypeR4:\r
1323 Cmd |= BIT1;\r
1324 break;\r
1325 case SdResponseTypeR1b:\r
1326 case SdResponseTypeR5b:\r
1327 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r
1328 break;\r
1329 default:\r
1330 ASSERT (FALSE);\r
1331 break;\r
1332 }\r
1333 }\r
1334 //\r
1335 // Execute cmd\r
1336 //\r
1337 Status = SdPeimHcRwMmio (Bar + SD_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r
1338 return Status;\r
1339}\r
1340\r
1341/**\r
1342 Check the TRB execution result.\r
1343\r
1344 @param[in] Bar The mmio base address of the slot to be accessed.\r
1345 @param[in] Trb The pointer to the SD_TRB instance.\r
1346\r
1347 @retval EFI_SUCCESS The TRB is executed successfully.\r
1348 @retval EFI_NOT_READY The TRB is not completed for execution.\r
1349 @retval Others Some erros happen when executing this request.\r
1350\r
1351**/\r
1352EFI_STATUS\r
1353SdPeimCheckTrbResult (\r
1354 IN UINTN Bar,\r
1355 IN SD_TRB *Trb\r
1356 )\r
1357{\r
1358 EFI_STATUS Status;\r
1359 SD_COMMAND_PACKET *Packet;\r
1360 UINT16 IntStatus;\r
1361 UINT32 Response[4];\r
1362 UINT32 SdmaAddr;\r
1363 UINT8 Index;\r
1364 UINT8 SwReset;\r
1365\r
1366 SwReset = 0;\r
1367 Packet = Trb->Packet;\r
1368 //\r
1369 // Check Trb execution result by reading Normal Interrupt Status register.\r
1370 //\r
1371 Status = SdPeimHcRwMmio (\r
1372 Bar + SD_HC_NOR_INT_STS,\r
1373 TRUE,\r
1374 sizeof (IntStatus),\r
1375 &IntStatus\r
1376 );\r
1377 if (EFI_ERROR (Status)) {\r
1378 goto Done;\r
1379 }\r
1380 //\r
1381 // Check Transfer Complete bit is set or not.\r
1382 //\r
1383 if ((IntStatus & BIT1) == BIT1) {\r
1384 if ((IntStatus & BIT15) == BIT15) {\r
1385 //\r
1386 // Read Error Interrupt Status register to check if the error is\r
1387 // Data Timeout Error.\r
1388 // If yes, treat it as success as Transfer Complete has higher\r
1389 // priority than Data Timeout Error.\r
1390 //\r
1391 Status = SdPeimHcRwMmio (\r
1392 Bar + SD_HC_ERR_INT_STS,\r
1393 TRUE,\r
1394 sizeof (IntStatus),\r
1395 &IntStatus\r
1396 );\r
1397 if (!EFI_ERROR (Status)) {\r
1398 if ((IntStatus & BIT4) == BIT4) {\r
1399 Status = EFI_SUCCESS;\r
1400 } else {\r
1401 Status = EFI_DEVICE_ERROR;\r
1402 }\r
1403 }\r
1404 }\r
1405\r
1406 goto Done;\r
1407 }\r
1408 //\r
1409 // Check if there is a error happened during cmd execution.\r
1410 // If yes, then do error recovery procedure to follow SD Host Controller\r
1411 // Simplified Spec 3.0 section 3.10.1.\r
1412 //\r
1413 if ((IntStatus & BIT15) == BIT15) {\r
1414 Status = SdPeimHcRwMmio (\r
1415 Bar + SD_HC_ERR_INT_STS,\r
1416 TRUE,\r
1417 sizeof (IntStatus),\r
1418 &IntStatus\r
1419 );\r
1420 if (EFI_ERROR (Status)) {\r
1421 goto Done;\r
1422 }\r
1423\r
1424 if ((IntStatus & 0x0F) != 0) {\r
1425 SwReset |= BIT1;\r
1426 }\r
1427 if ((IntStatus & 0xF0) != 0) {\r
1428 SwReset |= BIT2;\r
1429 }\r
1430\r
1431 Status = SdPeimHcRwMmio (\r
1432 Bar + SD_HC_SW_RST,\r
1433 FALSE,\r
1434 sizeof (SwReset),\r
1435 &SwReset\r
1436 );\r
1437 if (EFI_ERROR (Status)) {\r
1438 goto Done;\r
1439 }\r
1440 Status = SdPeimHcWaitMmioSet (\r
1441 Bar + SD_HC_SW_RST,\r
1442 sizeof (SwReset),\r
1443 0xFF,\r
1444 0,\r
1445 SD_TIMEOUT\r
1446 );\r
1447 if (EFI_ERROR (Status)) {\r
1448 goto Done;\r
1449 }\r
1450\r
1451 Status = EFI_DEVICE_ERROR;\r
1452 goto Done;\r
1453 }\r
1454 //\r
1455 // Check if DMA interrupt is signalled for the SDMA transfer.\r
1456 //\r
1457 if ((Trb->Mode == SdSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r
1458 //\r
1459 // Clear DMA interrupt bit.\r
1460 //\r
1461 IntStatus = BIT3;\r
1462 Status = SdPeimHcRwMmio (\r
1463 Bar + SD_HC_NOR_INT_STS,\r
1464 FALSE,\r
1465 sizeof (IntStatus),\r
1466 &IntStatus\r
1467 );\r
1468 if (EFI_ERROR (Status)) {\r
1469 goto Done;\r
1470 }\r
1471 //\r
1472 // Update SDMA Address register.\r
1473 //\r
1474 SdmaAddr = SD_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->Data, SD_SDMA_BOUNDARY);\r
1475 Status = SdPeimHcRwMmio (\r
1476 Bar + SD_HC_SDMA_ADDR,\r
1477 FALSE,\r
1478 sizeof (UINT32),\r
1479 &SdmaAddr\r
1480 );\r
1481 if (EFI_ERROR (Status)) {\r
1482 goto Done;\r
1483 }\r
1484 Trb->Data = (VOID*)(UINTN)SdmaAddr;\r
1485 }\r
1486\r
1487 if ((Packet->SdCmdBlk->CommandType != SdCommandTypeAdtc) &&\r
1488 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR1b) &&\r
1489 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR5b)) {\r
1490 if ((IntStatus & BIT0) == BIT0) {\r
1491 Status = EFI_SUCCESS;\r
1492 goto Done;\r
1493 }\r
1494 }\r
1495\r
1496 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {\r
1497 Status = EFI_SUCCESS;\r
1498 goto Done;\r
1499 }\r
1500\r
1501 Status = EFI_NOT_READY;\r
1502Done:\r
1503 //\r
1504 // Get response data when the cmd is executed successfully.\r
1505 //\r
1506 if (!EFI_ERROR (Status)) {\r
1507 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {\r
1508 for (Index = 0; Index < 4; Index++) {\r
1509 Status = SdPeimHcRwMmio (\r
1510 Bar + SD_HC_RESPONSE + Index * 4,\r
1511 TRUE,\r
1512 sizeof (UINT32),\r
1513 &Response[Index]\r
1514 );\r
1515 if (EFI_ERROR (Status)) {\r
1516 SdPeimHcLedOnOff (Bar, FALSE);\r
1517 return Status;\r
1518 }\r
1519 }\r
1520 CopyMem (Packet->SdStatusBlk, Response, sizeof (Response));\r
1521 }\r
1522 }\r
1523\r
1524 if (Status != EFI_NOT_READY) {\r
1525 SdPeimHcLedOnOff (Bar, FALSE);\r
1526 }\r
1527\r
1528 return Status;\r
1529}\r
1530\r
1531/**\r
1532 Wait for the TRB execution result.\r
1533\r
1534 @param[in] Bar The mmio base address of the slot to be accessed.\r
1535 @param[in] Trb The pointer to the SD_TRB instance.\r
1536\r
1537 @retval EFI_SUCCESS The TRB is executed successfully.\r
1538 @retval Others Some erros happen when executing this request.\r
1539\r
1540**/\r
1541EFI_STATUS\r
1542SdPeimWaitTrbResult (\r
1543 IN UINTN Bar,\r
1544 IN SD_TRB *Trb\r
1545 )\r
1546{\r
1547 EFI_STATUS Status;\r
1548 SD_COMMAND_PACKET *Packet;\r
1549 UINT64 Timeout;\r
1550 BOOLEAN InfiniteWait;\r
1551\r
1552 Packet = Trb->Packet;\r
1553 //\r
1554 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
1555 //\r
1556 Timeout = Packet->Timeout;\r
1557 if (Timeout == 0) {\r
1558 InfiniteWait = TRUE;\r
1559 } else {\r
1560 InfiniteWait = FALSE;\r
1561 }\r
1562\r
1563 while (InfiniteWait || (Timeout > 0)) {\r
1564 //\r
1565 // Check Trb execution result by reading Normal Interrupt Status register.\r
1566 //\r
1567 Status = SdPeimCheckTrbResult (Bar, Trb);\r
1568 if (Status != EFI_NOT_READY) {\r
1569 return Status;\r
1570 }\r
1571 //\r
1572 // Stall for 1 microsecond.\r
1573 //\r
1574 MicroSecondDelay (1);\r
1575\r
1576 Timeout--;\r
1577 }\r
1578\r
1579 return EFI_TIMEOUT;\r
1580}\r
1581\r
1582/**\r
1583 Sends SD command to an SD card that is attached to the SD controller.\r
1584\r
1585 If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.\r
1586\r
1587 If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.\r
1588\r
1589 If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER\r
1590 is returned.\r
1591\r
1592 If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,\r
1593 EFI_INVALID_PARAMETER is returned.\r
1594\r
1595 @param[in] Slot The slot number of the Sd card to send the command to.\r
1596 @param[in,out] Packet A pointer to the SD command data structure.\r
1597\r
1598 @retval EFI_SUCCESS The SD Command Packet was sent by the host.\r
1599 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD\r
1600 command Packet.\r
1601 @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.\r
1602 @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and\r
1603 OutDataBuffer are NULL.\r
1604 @retval EFI_NO_MEDIA SD Device not present in the Slot.\r
1605 @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not\r
1606 supported by the host controller.\r
1607 @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the\r
1608 limit supported by SD card ( i.e. if the number of bytes\r
1609 exceed the Last LBA).\r
1610\r
1611**/\r
1612EFI_STATUS\r
1613EFIAPI\r
1614SdPeimExecCmd (\r
1615 IN SD_PEIM_HC_SLOT *Slot,\r
1616 IN OUT SD_COMMAND_PACKET *Packet\r
1617 )\r
1618{\r
1619 EFI_STATUS Status;\r
1620 SD_TRB *Trb;\r
1621\r
1622 if (Packet == NULL) {\r
1623 return EFI_INVALID_PARAMETER;\r
1624 }\r
1625\r
1626 if ((Packet->SdCmdBlk == NULL) || (Packet->SdStatusBlk == NULL)) {\r
1627 return EFI_INVALID_PARAMETER;\r
1628 }\r
1629\r
1630 if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {\r
1631 return EFI_INVALID_PARAMETER;\r
1632 }\r
1633\r
1634 if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {\r
1635 return EFI_INVALID_PARAMETER;\r
1636 }\r
1637\r
1638 Trb = SdPeimCreateTrb (Slot, Packet);\r
1639 if (Trb == NULL) {\r
1640 return EFI_OUT_OF_RESOURCES;\r
1641 }\r
1642\r
1643 Status = SdPeimWaitTrbEnv (Slot->SdHcBase, Trb);\r
1644 if (EFI_ERROR (Status)) {\r
1645 goto Done;\r
1646 }\r
1647\r
1648 Status = SdPeimExecTrb (Slot->SdHcBase, Trb);\r
1649 if (EFI_ERROR (Status)) {\r
1650 goto Done;\r
1651 }\r
1652\r
1653 Status = SdPeimWaitTrbResult (Slot->SdHcBase, Trb);\r
1654 if (EFI_ERROR (Status)) {\r
1655 goto Done;\r
1656 }\r
1657\r
1658Done:\r
1659 SdPeimFreeTrb (Trb);\r
1660\r
1661 return Status;\r
1662}\r
1663\r
1664/**\r
1665 Send command GO_IDLE_STATE to the device to make it go to Idle State.\r
1666\r
1667 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
1668\r
1669 @param[in] Slot The slot number of the SD card to send the command to.\r
1670\r
1671 @retval EFI_SUCCESS The SD device is reset correctly.\r
1672 @retval Others The device reset fails.\r
1673\r
1674**/\r
1675EFI_STATUS\r
1676SdPeimReset (\r
1677 IN SD_PEIM_HC_SLOT *Slot\r
1678 )\r
1679{\r
1680 SD_COMMAND_BLOCK SdCmdBlk;\r
1681 SD_STATUS_BLOCK SdStatusBlk;\r
1682 SD_COMMAND_PACKET Packet;\r
1683 EFI_STATUS Status;\r
1684\r
1685 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1686 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1687 ZeroMem (&Packet, sizeof (Packet));\r
1688\r
1689 Packet.SdCmdBlk = &SdCmdBlk;\r
1690 Packet.SdStatusBlk = &SdStatusBlk;\r
1691 Packet.Timeout = SD_TIMEOUT;\r
1692\r
1693 SdCmdBlk.CommandIndex = SD_GO_IDLE_STATE;\r
1694 SdCmdBlk.CommandType = SdCommandTypeBc;\r
1695 SdCmdBlk.ResponseType = 0;\r
1696 SdCmdBlk.CommandArgument = 0;\r
1697\r
1698 Status = SdPeimExecCmd (Slot, &Packet);\r
1699\r
1700 return Status;\r
1701}\r
1702\r
1703/**\r
1704 Send command SEND_IF_COND to the device to inquiry the SD Memory Card interface\r
1705 condition.\r
1706\r
1707 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
1708\r
1709 @param[in] Slot The slot number of the SD card to send the command to.\r
1710 @param[in] SupplyVoltage The supplied voltage by the host.\r
1711 @param[in] CheckPattern The check pattern to be sent to the device.\r
1712\r
1713 @retval EFI_SUCCESS The operation is done correctly.\r
1714 @retval Others The operation fails.\r
1715\r
1716**/\r
1717EFI_STATUS\r
1718SdPeimVoltageCheck (\r
1719 IN SD_PEIM_HC_SLOT *Slot,\r
1720 IN UINT8 SupplyVoltage,\r
1721 IN UINT8 CheckPattern\r
1722 )\r
1723{\r
1724 SD_COMMAND_BLOCK SdCmdBlk;\r
1725 SD_STATUS_BLOCK SdStatusBlk;\r
1726 SD_COMMAND_PACKET Packet;\r
1727 EFI_STATUS Status;\r
1728\r
1729 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1730 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1731 ZeroMem (&Packet, sizeof (Packet));\r
1732\r
1733 Packet.SdCmdBlk = &SdCmdBlk;\r
1734 Packet.SdStatusBlk = &SdStatusBlk;\r
1735 Packet.Timeout = SD_TIMEOUT;\r
1736\r
1737 SdCmdBlk.CommandIndex = SD_SEND_IF_COND;\r
1738 SdCmdBlk.CommandType = SdCommandTypeBcr;\r
1739 SdCmdBlk.ResponseType = SdResponseTypeR7;\r
1740 SdCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;\r
1741\r
1742 Status = SdPeimExecCmd (Slot, &Packet);\r
1743 if (!EFI_ERROR (Status)) {\r
1744 if (SdStatusBlk.Resp0 != SdCmdBlk.CommandArgument) {\r
1745 return EFI_DEVICE_ERROR;\r
1746 }\r
1747 }\r
1748\r
1749 return Status;\r
1750}\r
1751\r
1752/**\r
1753 Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device.\r
1754\r
1755 Refer to SDIO Simplified Spec 3 Section 3.2 for details.\r
1756\r
1757 @param[in] Slot The slot number of the SD card to send the command to.\r
1758 @param[in] VoltageWindow The supply voltage window.\r
1759 @param[in] S18r The boolean to show if it should switch to 1.8v.\r
1760\r
1761 @retval EFI_SUCCESS The operation is done correctly.\r
1762 @retval Others The operation fails.\r
1763\r
1764**/\r
1765EFI_STATUS\r
1766SdioSendOpCond (\r
1767 IN SD_PEIM_HC_SLOT *Slot,\r
1768 IN UINT32 VoltageWindow,\r
1769 IN BOOLEAN S18r\r
1770 )\r
1771{\r
1772 SD_COMMAND_BLOCK SdCmdBlk;\r
1773 SD_STATUS_BLOCK SdStatusBlk;\r
1774 SD_COMMAND_PACKET Packet;\r
1775 EFI_STATUS Status;\r
1776 UINT32 Switch;\r
1777\r
1778 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1779 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1780 ZeroMem (&Packet, sizeof (Packet));\r
1781\r
1782 Packet.SdCmdBlk = &SdCmdBlk;\r
1783 Packet.SdStatusBlk = &SdStatusBlk;\r
1784 Packet.Timeout = SD_TIMEOUT;\r
1785\r
1786 SdCmdBlk.CommandIndex = SDIO_SEND_OP_COND;\r
1787 SdCmdBlk.CommandType = SdCommandTypeBcr;\r
1788 SdCmdBlk.ResponseType = SdResponseTypeR4;\r
1789\r
1790 Switch = S18r ? BIT24 : 0;\r
1791\r
1792 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch;\r
1793\r
1794 Status = SdPeimExecCmd (Slot, &Packet);\r
1795\r
1796 return Status;\r
1797}\r
1798\r
1799/**\r
1800 Send command SD_SEND_OP_COND to the device to see whether it is SDIO device.\r
1801\r
1802 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
1803\r
1804 @param[in] Slot The slot number of the SD card to send the command to.\r
1805 @param[in] Rca The relative device address of addressed device.\r
1806 @param[in] VoltageWindow The supply voltage window.\r
1807 @param[in] S18r The boolean to show if it should switch to 1.8v.\r
1808 @param[in] Xpc The boolean to show if it should provide 0.36w power control.\r
1809 @param[in] Hcs The boolean to show if it support host capacity info.\r
1810 @param[out] Ocr The buffer to store returned OCR register value.\r
1811\r
1812\r
1813 @retval EFI_SUCCESS The operation is done correctly.\r
1814 @retval Others The operation fails.\r
1815\r
1816**/\r
1817EFI_STATUS\r
1818SdPeimSendOpCond (\r
1819 IN SD_PEIM_HC_SLOT *Slot,\r
1820 IN UINT16 Rca,\r
1821 IN UINT32 VoltageWindow,\r
1822 IN BOOLEAN S18r,\r
1823 IN BOOLEAN Xpc,\r
1824 IN BOOLEAN Hcs,\r
1825 OUT UINT32 *Ocr\r
1826 )\r
1827{\r
1828 SD_COMMAND_BLOCK SdCmdBlk;\r
1829 SD_STATUS_BLOCK SdStatusBlk;\r
1830 SD_COMMAND_PACKET Packet;\r
1831 EFI_STATUS Status;\r
1832 UINT32 Switch;\r
1833 UINT32 MaxPower;\r
1834 UINT32 HostCapacity;\r
1835\r
1836 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1837 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1838 ZeroMem (&Packet, sizeof (Packet));\r
1839\r
1840 Packet.SdCmdBlk = &SdCmdBlk;\r
1841 Packet.SdStatusBlk = &SdStatusBlk;\r
1842 Packet.Timeout = SD_TIMEOUT;\r
1843\r
1844 SdCmdBlk.CommandIndex = SD_APP_CMD;\r
1845 SdCmdBlk.CommandType = SdCommandTypeAc;\r
1846 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
1847 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;\r
1848\r
1849 Status = SdPeimExecCmd (Slot, &Packet);\r
1850 if (EFI_ERROR (Status)) {\r
1851 return Status;\r
1852 }\r
1853\r
1854 SdCmdBlk.CommandIndex = SD_SEND_OP_COND;\r
1855 SdCmdBlk.CommandType = SdCommandTypeBcr;\r
1856 SdCmdBlk.ResponseType = SdResponseTypeR3;\r
1857\r
1858 Switch = S18r ? BIT24 : 0;\r
1859 MaxPower = Xpc ? BIT28 : 0;\r
1860 HostCapacity = Hcs ? BIT30 : 0;\r
1861 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | MaxPower | HostCapacity;\r
1862\r
1863 Status = SdPeimExecCmd (Slot, &Packet);\r
1864 if (!EFI_ERROR (Status)) {\r
1865 //\r
1866 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
1867 //\r
1868 *Ocr = SdStatusBlk.Resp0;\r
1869 }\r
1870\r
1871 return Status;\r
1872}\r
1873\r
1874/**\r
1875 Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send the\r
1876 data of their CID registers.\r
1877\r
1878 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
1879\r
1880 @param[in] Slot The slot number of the SD card to send the command to.\r
1881\r
1882 @retval EFI_SUCCESS The operation is done correctly.\r
1883 @retval Others The operation fails.\r
1884\r
1885**/\r
1886EFI_STATUS\r
1887SdPeimAllSendCid (\r
1888 IN SD_PEIM_HC_SLOT *Slot\r
1889 )\r
1890{\r
1891 SD_COMMAND_BLOCK SdCmdBlk;\r
1892 SD_STATUS_BLOCK SdStatusBlk;\r
1893 SD_COMMAND_PACKET Packet;\r
1894 EFI_STATUS Status;\r
1895\r
1896 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1897 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1898 ZeroMem (&Packet, sizeof (Packet));\r
1899\r
1900 Packet.SdCmdBlk = &SdCmdBlk;\r
1901 Packet.SdStatusBlk = &SdStatusBlk;\r
1902 Packet.Timeout = SD_TIMEOUT;\r
1903\r
1904 SdCmdBlk.CommandIndex = SD_ALL_SEND_CID;\r
1905 SdCmdBlk.CommandType = SdCommandTypeBcr;\r
1906 SdCmdBlk.ResponseType = SdResponseTypeR2;\r
1907 SdCmdBlk.CommandArgument = 0;\r
1908\r
1909 Status = SdPeimExecCmd (Slot, &Packet);\r
1910\r
1911 return Status;\r
1912}\r
1913\r
1914/**\r
1915 Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device\r
1916 Address (RCA).\r
1917\r
1918 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
1919\r
1920 @param[in] Slot The slot number of the SD card to send the command to.\r
1921 @param[out] Rca The relative device address to be assigned.\r
1922\r
1923 @retval EFI_SUCCESS The operation is done correctly.\r
1924 @retval Others The operation fails.\r
1925\r
1926**/\r
1927EFI_STATUS\r
1928SdPeimSetRca (\r
1929 IN SD_PEIM_HC_SLOT *Slot,\r
1930 OUT UINT16 *Rca\r
1931 )\r
1932{\r
1933 SD_COMMAND_BLOCK SdCmdBlk;\r
1934 SD_STATUS_BLOCK SdStatusBlk;\r
1935 SD_COMMAND_PACKET Packet;\r
1936 EFI_STATUS Status;\r
1937\r
1938 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1939 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1940 ZeroMem (&Packet, sizeof (Packet));\r
1941\r
1942 Packet.SdCmdBlk = &SdCmdBlk;\r
1943 Packet.SdStatusBlk = &SdStatusBlk;\r
1944 Packet.Timeout = SD_TIMEOUT;\r
1945\r
1946 SdCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR;\r
1947 SdCmdBlk.CommandType = SdCommandTypeBcr;\r
1948 SdCmdBlk.ResponseType = SdResponseTypeR6;\r
1949\r
1950 Status = SdPeimExecCmd (Slot, &Packet);\r
1951 if (!EFI_ERROR (Status)) {\r
1952 *Rca = (UINT16)(SdStatusBlk.Resp0 >> 16);\r
1953 }\r
1954\r
1955 return Status;\r
1956}\r
1957\r
1958/**\r
1959 Send command SEND_CSD to the SD device to get the data of the CSD register.\r
1960\r
1961 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
1962\r
1963 @param[in] Slot The slot number of the SD card to send the command to.\r
1964 @param[in] Rca The relative device address of selected device.\r
1965 @param[out] Csd The buffer to store the content of the CSD register.\r
1966 Note the caller should ignore the lowest byte of this\r
1967 buffer as the content of this byte is meaningless even\r
1968 if the operation succeeds.\r
1969\r
1970 @retval EFI_SUCCESS The operation is done correctly.\r
1971 @retval Others The operation fails.\r
1972\r
1973**/\r
1974EFI_STATUS\r
1975SdPeimGetCsd (\r
1976 IN SD_PEIM_HC_SLOT *Slot,\r
1977 IN UINT16 Rca,\r
1978 OUT SD_CSD *Csd\r
1979 )\r
1980{\r
1981 SD_COMMAND_BLOCK SdCmdBlk;\r
1982 SD_STATUS_BLOCK SdStatusBlk;\r
1983 SD_COMMAND_PACKET Packet;\r
1984 EFI_STATUS Status;\r
1985\r
1986 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
1987 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
1988 ZeroMem (&Packet, sizeof (Packet));\r
1989\r
1990 Packet.SdCmdBlk = &SdCmdBlk;\r
1991 Packet.SdStatusBlk = &SdStatusBlk;\r
1992 Packet.Timeout = SD_TIMEOUT;\r
1993\r
1994 SdCmdBlk.CommandIndex = SD_SEND_CSD;\r
1995 SdCmdBlk.CommandType = SdCommandTypeAc;\r
1996 SdCmdBlk.ResponseType = SdResponseTypeR2;\r
1997 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;\r
1998\r
1999 Status = SdPeimExecCmd (Slot, &Packet);\r
2000 if (!EFI_ERROR (Status)) {\r
2001 //\r
2002 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
2003 //\r
2004 CopyMem (((UINT8*)Csd) + 1, &SdStatusBlk.Resp0, sizeof (SD_CSD) - 1);\r
2005 }\r
2006\r
2007 return Status;\r
2008}\r
2009\r
2010/**\r
2011 Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.\r
2012\r
2013 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2014\r
2015 @param[in] Slot The slot number of the SD card to send the command to.\r
2016 @param[in] Rca The relative device address of selected device.\r
2017\r
2018 @retval EFI_SUCCESS The operation is done correctly.\r
2019 @retval Others The operation fails.\r
2020\r
2021**/\r
2022EFI_STATUS\r
2023SdPeimSelect (\r
2024 IN SD_PEIM_HC_SLOT *Slot,\r
2025 IN UINT16 Rca\r
2026 )\r
2027{\r
2028 SD_COMMAND_BLOCK SdCmdBlk;\r
2029 SD_STATUS_BLOCK SdStatusBlk;\r
2030 SD_COMMAND_PACKET Packet;\r
2031 EFI_STATUS Status;\r
2032\r
2033 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2034 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2035 ZeroMem (&Packet, sizeof (Packet));\r
2036\r
2037 Packet.SdCmdBlk = &SdCmdBlk;\r
2038 Packet.SdStatusBlk = &SdStatusBlk;\r
2039 Packet.Timeout = SD_TIMEOUT;\r
2040\r
2041 SdCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD;\r
2042 SdCmdBlk.CommandType = SdCommandTypeAc;\r
2043 SdCmdBlk.ResponseType = SdResponseTypeR1b;\r
2044 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;\r
2045\r
2046 Status = SdPeimExecCmd (Slot, &Packet);\r
2047\r
2048 return Status;\r
2049}\r
2050\r
2051/**\r
2052 Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the device.\r
2053\r
2054 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2055\r
2056 @param[in] Slot The slot number of the SD card to send the command to.\r
2057\r
2058 @retval EFI_SUCCESS The operation is done correctly.\r
2059 @retval Others The operation fails.\r
2060\r
2061**/\r
2062EFI_STATUS\r
2063SdPeimVoltageSwitch (\r
2064 IN SD_PEIM_HC_SLOT *Slot\r
2065 )\r
2066{\r
2067 SD_COMMAND_BLOCK SdCmdBlk;\r
2068 SD_STATUS_BLOCK SdStatusBlk;\r
2069 SD_COMMAND_PACKET Packet;\r
2070 EFI_STATUS Status;\r
2071\r
2072 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2073 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2074 ZeroMem (&Packet, sizeof (Packet));\r
2075\r
2076 Packet.SdCmdBlk = &SdCmdBlk;\r
2077 Packet.SdStatusBlk = &SdStatusBlk;\r
2078 Packet.Timeout = SD_TIMEOUT;\r
2079\r
2080 SdCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;\r
2081 SdCmdBlk.CommandType = SdCommandTypeAc;\r
2082 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2083 SdCmdBlk.CommandArgument = 0;\r
2084\r
2085 Status = SdPeimExecCmd (Slot, &Packet);\r
2086\r
2087 return Status;\r
2088}\r
2089\r
2090/**\r
2091 Send command SET_BUS_WIDTH to the SD device to set the bus width.\r
2092\r
2093 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2094\r
2095 @param[in] Slot The slot number of the SD card to send the command to.\r
2096 @param[in] Rca The relative device address of addressed device.\r
2097 @param[in] BusWidth The bus width to be set, it could be 1 or 4.\r
2098\r
2099 @retval EFI_SUCCESS The operation is done correctly.\r
2100 @retval Others The operation fails.\r
2101\r
2102**/\r
2103EFI_STATUS\r
2104SdPeimSetBusWidth (\r
2105 IN SD_PEIM_HC_SLOT *Slot,\r
2106 IN UINT16 Rca,\r
2107 IN UINT8 BusWidth\r
2108 )\r
2109{\r
2110 SD_COMMAND_BLOCK SdCmdBlk;\r
2111 SD_STATUS_BLOCK SdStatusBlk;\r
2112 SD_COMMAND_PACKET Packet;\r
2113 EFI_STATUS Status;\r
2114 UINT8 Value;\r
2115\r
2116 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2117 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2118 ZeroMem (&Packet, sizeof (Packet));\r
2119\r
2120 Packet.SdCmdBlk = &SdCmdBlk;\r
2121 Packet.SdStatusBlk = &SdStatusBlk;\r
2122 Packet.Timeout = SD_TIMEOUT;\r
2123\r
2124 SdCmdBlk.CommandIndex = SD_APP_CMD;\r
2125 SdCmdBlk.CommandType = SdCommandTypeAc;\r
2126 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2127 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;\r
2128\r
2129 Status = SdPeimExecCmd (Slot, &Packet);\r
2130 if (EFI_ERROR (Status)) {\r
2131 return Status;\r
2132 }\r
2133\r
2134 SdCmdBlk.CommandIndex = SD_SET_BUS_WIDTH;\r
2135 SdCmdBlk.CommandType = SdCommandTypeAc;\r
2136 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2137\r
2138 if (BusWidth == 1) {\r
2139 Value = 0;\r
2140 } else if (BusWidth == 4) {\r
2141 Value = 2;\r
2142 } else {\r
2143 return EFI_INVALID_PARAMETER;\r
2144 }\r
2145 SdCmdBlk.CommandArgument = Value & 0x3;\r
2146\r
2147 Status = SdPeimExecCmd (Slot, &Packet);\r
2148\r
2149 return Status;\r
2150}\r
2151\r
2152/**\r
2153 Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.\r
2154\r
2155 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2156\r
2157 @param[in] Slot The slot number of the SD card to send the command to.\r
2158 @param[in] AccessMode The value for access mode group.\r
2159 @param[in] CommandSystem The value for command set group.\r
2160 @param[in] DriveStrength The value for drive length group.\r
2161 @param[in] PowerLimit The value for power limit group.\r
2162 @param[in] Mode Switch or check function.\r
2163\r
2164 @retval EFI_SUCCESS The operation is done correctly.\r
2165 @retval Others The operation fails.\r
2166\r
2167**/\r
2168EFI_STATUS\r
2169SdPeimSwitch (\r
2170 IN SD_PEIM_HC_SLOT *Slot,\r
2171 IN UINT8 AccessMode,\r
2172 IN UINT8 CommandSystem,\r
2173 IN UINT8 DriveStrength,\r
2174 IN UINT8 PowerLimit,\r
2175 IN BOOLEAN Mode\r
2176 )\r
2177{\r
2178 SD_COMMAND_BLOCK SdCmdBlk;\r
2179 SD_STATUS_BLOCK SdStatusBlk;\r
2180 SD_COMMAND_PACKET Packet;\r
2181 EFI_STATUS Status;\r
2182 UINT32 ModeValue;\r
2183 UINT8 Data[64];\r
2184\r
2185 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2186 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2187 ZeroMem (&Packet, sizeof (Packet));\r
2188\r
2189 Packet.SdCmdBlk = &SdCmdBlk;\r
2190 Packet.SdStatusBlk = &SdStatusBlk;\r
2191 Packet.Timeout = SD_TIMEOUT;\r
2192\r
2193 SdCmdBlk.CommandIndex = SD_SWITCH_FUNC;\r
2194 SdCmdBlk.CommandType = SdCommandTypeAdtc;\r
2195 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2196\r
2197 ModeValue = Mode ? BIT31 : 0;\r
2198 SdCmdBlk.CommandArgument = (AccessMode & 0xF) | ((PowerLimit & 0xF) << 4) | \\r
2199 ((DriveStrength & 0xF) << 8) | ((DriveStrength & 0xF) << 12) | \\r
2200 ModeValue;\r
2201 Packet.InDataBuffer = Data;\r
2202 Packet.InTransferLength = sizeof (Data);\r
2203\r
2204 Status = SdPeimExecCmd (Slot, &Packet);\r
2205\r
2206 return Status;\r
2207}\r
2208\r
2209/**\r
2210 Send command SEND_STATUS to the addressed SD device to get its status register.\r
2211\r
2212 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2213\r
2214 @param[in] Slot The slot number of the SD card to send the command to.\r
2215 @param[in] Rca The relative device address of addressed device.\r
2216 @param[out] DevStatus The returned device status.\r
2217\r
2218 @retval EFI_SUCCESS The operation is done correctly.\r
2219 @retval Others The operation fails.\r
2220\r
2221**/\r
2222EFI_STATUS\r
2223SdPeimSendStatus (\r
2224 IN SD_PEIM_HC_SLOT *Slot,\r
2225 IN UINT16 Rca,\r
2226 OUT UINT32 *DevStatus\r
2227 )\r
2228{\r
2229 SD_COMMAND_BLOCK SdCmdBlk;\r
2230 SD_STATUS_BLOCK SdStatusBlk;\r
2231 SD_COMMAND_PACKET Packet;\r
2232 EFI_STATUS Status;\r
2233\r
2234 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2235 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2236 ZeroMem (&Packet, sizeof (Packet));\r
2237\r
2238 Packet.SdCmdBlk = &SdCmdBlk;\r
2239 Packet.SdStatusBlk = &SdStatusBlk;\r
2240 Packet.Timeout = SD_TIMEOUT;\r
2241\r
2242 SdCmdBlk.CommandIndex = SD_SEND_STATUS;\r
2243 SdCmdBlk.CommandType = SdCommandTypeAc;\r
2244 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2245 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;\r
2246\r
2247 Status = SdPeimExecCmd (Slot, &Packet);\r
2248 if (!EFI_ERROR (Status)) {\r
2249 *DevStatus = SdStatusBlk.Resp0;\r
2250 }\r
2251\r
2252 return Status;\r
2253}\r
2254\r
2255/**\r
2256 Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device\r
2257 to read/write the specified number of blocks.\r
2258\r
2259 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2260\r
2261 @param[in] Slot The slot number of the SD card to send the command to.\r
2262 @param[in] Lba The logical block address of starting access.\r
2263 @param[in] BlockSize The block size of specified SD device partition.\r
2264 @param[in] Buffer The pointer to the transfer buffer.\r
2265 @param[in] BufferSize The size of transfer buffer.\r
2266 @param[in] IsRead Boolean to show the operation direction.\r
2267\r
2268 @retval EFI_SUCCESS The operation is done correctly.\r
2269 @retval Others The operation fails.\r
2270\r
2271**/\r
2272EFI_STATUS\r
2273SdPeimRwSingleBlock (\r
2274 IN SD_PEIM_HC_SLOT *Slot,\r
2275 IN EFI_LBA Lba,\r
2276 IN UINT32 BlockSize,\r
2277 IN VOID *Buffer,\r
2278 IN UINTN BufferSize,\r
2279 IN BOOLEAN IsRead\r
2280 )\r
2281{\r
2282 SD_COMMAND_BLOCK SdCmdBlk;\r
2283 SD_STATUS_BLOCK SdStatusBlk;\r
2284 SD_COMMAND_PACKET Packet;\r
2285 EFI_STATUS Status;\r
2286\r
2287 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2288 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2289 ZeroMem (&Packet, sizeof (Packet));\r
2290\r
2291 Packet.SdCmdBlk = &SdCmdBlk;\r
2292 Packet.SdStatusBlk = &SdStatusBlk;\r
2293 //\r
2294 // Calculate timeout value through the below formula.\r
2295 // Timeout = (transfer size) / (2MB/s).\r
2296 // Taking 2MB/s as divisor is because it's the lowest\r
2297 // transfer speed of class 2.\r
2298 //\r
2299 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;\r
2300\r
2301 if (IsRead) {\r
2302 Packet.InDataBuffer = Buffer;\r
2303 Packet.InTransferLength = (UINT32)BufferSize;\r
2304\r
2305 SdCmdBlk.CommandIndex = SD_READ_SINGLE_BLOCK;\r
2306 SdCmdBlk.CommandType = SdCommandTypeAdtc;\r
2307 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2308 } else {\r
2309 Packet.OutDataBuffer = Buffer;\r
2310 Packet.OutTransferLength = (UINT32)BufferSize;\r
2311\r
2312 SdCmdBlk.CommandIndex = SD_WRITE_SINGLE_BLOCK;\r
2313 SdCmdBlk.CommandType = SdCommandTypeAdtc;\r
2314 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2315 }\r
2316\r
2317 if (Slot->SectorAddressing) {\r
2318 SdCmdBlk.CommandArgument = (UINT32)Lba;\r
2319 } else {\r
2320 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);\r
2321 }\r
2322\r
2323 Status = SdPeimExecCmd (Slot, &Packet);\r
2324\r
2325 return Status;\r
2326}\r
2327\r
2328/**\r
2329 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device\r
2330 to read/write the specified number of blocks.\r
2331\r
2332 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2333\r
2334 @param[in] Slot The slot number of the SD card to send the command to.\r
2335 @param[in] Lba The logical block address of starting access.\r
2336 @param[in] BlockSize The block size of specified SD device partition.\r
2337 @param[in] Buffer The pointer to the transfer buffer.\r
2338 @param[in] BufferSize The size of transfer buffer.\r
2339 @param[in] IsRead Boolean to show the operation direction.\r
2340\r
2341 @retval EFI_SUCCESS The operation is done correctly.\r
2342 @retval Others The operation fails.\r
2343\r
2344**/\r
2345EFI_STATUS\r
2346SdPeimRwMultiBlocks (\r
2347 IN SD_PEIM_HC_SLOT *Slot,\r
2348 IN EFI_LBA Lba,\r
2349 IN UINT32 BlockSize,\r
2350 IN VOID *Buffer,\r
2351 IN UINTN BufferSize,\r
2352 IN BOOLEAN IsRead\r
2353 )\r
2354{\r
2355 SD_COMMAND_BLOCK SdCmdBlk;\r
2356 SD_STATUS_BLOCK SdStatusBlk;\r
2357 SD_COMMAND_PACKET Packet;\r
2358 EFI_STATUS Status;\r
2359\r
2360 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2361 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2362 ZeroMem (&Packet, sizeof (Packet));\r
2363\r
2364 Packet.SdCmdBlk = &SdCmdBlk;\r
2365 Packet.SdStatusBlk = &SdStatusBlk;\r
2366 //\r
2367 // Calculate timeout value through the below formula.\r
2368 // Timeout = (transfer size) / (2MB/s).\r
2369 // Taking 2MB/s as divisor is because it's the lowest\r
2370 // transfer speed of class 2.\r
2371 //\r
2372 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;\r
2373\r
2374 if (IsRead) {\r
2375 Packet.InDataBuffer = Buffer;\r
2376 Packet.InTransferLength = (UINT32)BufferSize;\r
2377\r
2378 SdCmdBlk.CommandIndex = SD_READ_MULTIPLE_BLOCK;\r
2379 SdCmdBlk.CommandType = SdCommandTypeAdtc;\r
2380 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2381 } else {\r
2382 Packet.OutDataBuffer = Buffer;\r
2383 Packet.OutTransferLength = (UINT32)BufferSize;\r
2384\r
2385 SdCmdBlk.CommandIndex = SD_WRITE_MULTIPLE_BLOCK;\r
2386 SdCmdBlk.CommandType = SdCommandTypeAdtc;\r
2387 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2388 }\r
2389\r
2390 if (Slot->SectorAddressing) {\r
2391 SdCmdBlk.CommandArgument = (UINT32)Lba;\r
2392 } else {\r
2393 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);\r
2394 }\r
2395\r
2396 Status = SdPeimExecCmd (Slot, &Packet);\r
2397\r
2398 return Status;\r
2399}\r
2400\r
2401/**\r
2402 Send command SEND_TUNING_BLOCK to the SD device for SDR104/SDR50 optimal sampling point\r
2403 detection.\r
2404\r
2405 It may be sent up to 40 times until the host finishes the tuning procedure.\r
2406\r
2407 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r
2408\r
2409 @param[in] Slot The slot number of the SD card to send the command to.\r
2410\r
2411 @retval EFI_SUCCESS The operation is done correctly.\r
2412 @retval Others The operation fails.\r
2413\r
2414**/\r
2415EFI_STATUS\r
2416SdPeimSendTuningBlk (\r
2417 IN SD_PEIM_HC_SLOT *Slot\r
2418 )\r
2419{\r
2420 SD_COMMAND_BLOCK SdCmdBlk;\r
2421 SD_STATUS_BLOCK SdStatusBlk;\r
2422 SD_COMMAND_PACKET Packet;\r
2423 EFI_STATUS Status;\r
2424 UINT8 TuningBlock[64];\r
2425\r
2426 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));\r
2427 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));\r
2428 ZeroMem (&Packet, sizeof (Packet));\r
2429\r
2430 Packet.SdCmdBlk = &SdCmdBlk;\r
2431 Packet.SdStatusBlk = &SdStatusBlk;\r
2432 Packet.Timeout = SD_TIMEOUT;\r
2433\r
2434 SdCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;\r
2435 SdCmdBlk.CommandType = SdCommandTypeAdtc;\r
2436 SdCmdBlk.ResponseType = SdResponseTypeR1;\r
2437 SdCmdBlk.CommandArgument = 0;\r
2438\r
2439 Packet.InDataBuffer = TuningBlock;\r
2440 Packet.InTransferLength = sizeof (TuningBlock);\r
2441\r
2442 Status = SdPeimExecCmd (Slot, &Packet);\r
2443\r
2444 return Status;\r
2445}\r
2446\r
2447/**\r
2448 Tunning the sampling point of SDR104 or SDR50 bus speed mode.\r
2449\r
2450 Command SD_SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the\r
2451 tuning procedure.\r
2452\r
2453 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and SD Host Controller\r
2454 Simplified Spec 3.0 Figure 2-29 for details.\r
2455\r
2456 @param[in] Slot The slot number of the SD card to send the command to.\r
2457\r
2458 @retval EFI_SUCCESS The operation is done correctly.\r
2459 @retval Others The operation fails.\r
2460\r
2461**/\r
2462EFI_STATUS\r
2463SdPeimTuningClock (\r
2464 IN SD_PEIM_HC_SLOT *Slot\r
2465 )\r
2466{\r
2467 EFI_STATUS Status;\r
2468 UINT8 HostCtrl2;\r
2469 UINT8 Retry;\r
2470\r
2471 //\r
2472 // Notify the host that the sampling clock tuning procedure starts.\r
2473 //\r
2474 HostCtrl2 = BIT6;\r
2475 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2476 if (EFI_ERROR (Status)) {\r
2477 return Status;\r
2478 }\r
2479 //\r
2480 // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.\r
2481 //\r
2482 Retry = 0;\r
2483 do {\r
2484 Status = SdPeimSendTuningBlk (Slot);\r
2485 if (EFI_ERROR (Status)) {\r
2486 return Status;\r
2487 }\r
2488\r
2489 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);\r
2490 if (EFI_ERROR (Status)) {\r
2491 return Status;\r
2492 }\r
2493\r
2494 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {\r
2495 break;\r
2496 }\r
2497 } while (++Retry < 40);\r
2498\r
2499 if (Retry == 40) {\r
2500 Status = EFI_TIMEOUT;\r
2501 }\r
2502 return Status;\r
2503}\r
2504\r
2505/**\r
2506 Switch the bus width to specified width.\r
2507\r
2508 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and\r
2509 SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.\r
2510\r
2511 @param[in] Slot The slot number of the SD card to send the command to.\r
2512 @param[in] Rca The relative device address to be assigned.\r
2513 @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r
2514\r
2515 @retval EFI_SUCCESS The operation is done correctly.\r
2516 @retval Others The operation fails.\r
2517\r
2518**/\r
2519EFI_STATUS\r
2520SdPeimSwitchBusWidth (\r
2521 IN SD_PEIM_HC_SLOT *Slot,\r
2522 IN UINT16 Rca,\r
2523 IN UINT8 BusWidth\r
2524 )\r
2525{\r
2526 EFI_STATUS Status;\r
2527 UINT32 DevStatus;\r
2528\r
2529 Status = SdPeimSetBusWidth (Slot, Rca, BusWidth);\r
2530 if (EFI_ERROR (Status)) {\r
2531 return Status;\r
2532 }\r
2533\r
2534 Status = SdPeimSendStatus (Slot, Rca, &DevStatus);\r
2535 if (EFI_ERROR (Status)) {\r
2536 return Status;\r
2537 }\r
2538 //\r
2539 // Check the switch operation is really successful or not.\r
2540 //\r
2541 if ((DevStatus >> 16) != 0) {\r
2542 return EFI_DEVICE_ERROR;\r
2543 }\r
2544\r
2545 Status = SdPeimHcSetBusWidth (Slot->SdHcBase, BusWidth);\r
2546\r
2547 return Status;\r
2548}\r
2549\r
2550/**\r
2551 Switch the high speed timing according to request.\r
2552\r
2553 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and\r
2554 SD Host Controller Simplified Spec 3.0 section Figure 2-29 for details.\r
2555\r
2556 @param[in] Slot The slot number of the SD card to send the command to.\r
2557 @param[in] Rca The relative device address to be assigned.\r
2558 @param[in] S18a The boolean to show if it's a UHS-I SD card.\r
2559\r
2560 @retval EFI_SUCCESS The operation is done correctly.\r
2561 @retval Others The operation fails.\r
2562\r
2563**/\r
2564EFI_STATUS\r
2565SdPeimSetBusMode (\r
2566 IN SD_PEIM_HC_SLOT *Slot,\r
2567 IN UINT16 Rca,\r
2568 IN BOOLEAN S18a\r
2569 )\r
2570{\r
2571 EFI_STATUS Status;\r
2572 SD_HC_SLOT_CAP Capability;\r
2573 UINT32 ClockFreq;\r
2574 UINT8 BusWidth;\r
2575 UINT8 AccessMode;\r
2576 UINT8 HostCtrl1;\r
2577 UINT8 HostCtrl2;\r
2578\r
2579 Status = SdPeimGetCsd (Slot, Rca, &Slot->Csd);\r
2580 if (EFI_ERROR (Status)) {\r
2581 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimGetCsd fails with %r\n", Status));\r
2582 return Status;\r
2583 }\r
2584\r
2585 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);\r
2586 if (EFI_ERROR (Status)) {\r
2587 return Status;\r
2588 }\r
2589\r
2590 Status = SdPeimSelect (Slot, Rca);\r
2591 if (EFI_ERROR (Status)) {\r
2592 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSelect fails with %r\n", Status));\r
2593 return Status;\r
2594 }\r
2595\r
2596 BusWidth = 4;\r
2597 Status = SdPeimSwitchBusWidth (Slot, Rca, BusWidth);\r
2598 if (EFI_ERROR (Status)) {\r
2599 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitchBusWidth fails with %r\n", Status));\r
2600 return Status;\r
2601 }\r
2602\r
2603 //\r
2604 // Calculate supported bus speed/bus width/clock frequency.\r
2605 //\r
2606 ClockFreq = 0;\r
2607 if (S18a && (Capability.Sdr104 != 0)) {\r
2608 ClockFreq = 208;\r
2609 AccessMode = 3;\r
2610 } else if (S18a && (Capability.Sdr50 != 0)) {\r
2611 ClockFreq = 100;\r
2612 AccessMode = 2;\r
2613 } else if (S18a && (Capability.Ddr50 != 0)) {\r
2614 ClockFreq = 50;\r
2615 AccessMode = 4;\r
2616 } else {\r
2617 ClockFreq = 50;\r
2618 AccessMode = 1;\r
2619 }\r
2620\r
2621 DEBUG ((EFI_D_INFO, "AccessMode %d ClockFreq %d BusWidth %d\n", AccessMode, ClockFreq, BusWidth));\r
2622\r
2623 Status = SdPeimSwitch (Slot, AccessMode, 0, 0, 0, TRUE);\r
2624 if (EFI_ERROR (Status)) {\r
2625 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitch fails with %r\n", Status));\r
2626 return Status;\r
2627 }\r
2628\r
2629 //\r
2630 // Set to Hight Speed timing\r
2631 //\r
2632 if (AccessMode == 1) {\r
2633 HostCtrl1 = BIT2;\r
2634 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
2635 if (EFI_ERROR (Status)) {\r
2636 return Status;\r
2637 }\r
2638 }\r
2639\r
2640 HostCtrl2 = (UINT8)~0x7;\r
2641 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2642 if (EFI_ERROR (Status)) {\r
2643 return Status;\r
2644 }\r
2645 HostCtrl2 = AccessMode;\r
2646 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2647 if (EFI_ERROR (Status)) {\r
2648 return Status;\r
2649 }\r
2650\r
2651 Status = SdPeimHcClockSupply (Slot->SdHcBase, ClockFreq * 1000);\r
2652 if (EFI_ERROR (Status)) {\r
2653 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimHcClockSupply %r\n", Status));\r
2654 return Status;\r
2655 }\r
2656\r
2657 if ((AccessMode == 3) || ((AccessMode == 2) && (Capability.TuningSDR50 != 0))) {\r
2658 Status = SdPeimTuningClock (Slot);\r
2659 if (EFI_ERROR (Status)) {\r
2660 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimTuningClock fails with %r\n", Status));\r
2661 return Status;\r
2662 }\r
2663 }\r
2664\r
2665 DEBUG ((EFI_D_INFO, "SdPeimSetBusMode: SdPeimSetBusMode %r\n", Status));\r
2666\r
2667 return Status;\r
2668}\r
2669\r
2670/**\r
2671 Execute SD device identification procedure.\r
2672\r
2673 Refer to SD Physical Layer Simplified Spec 4.1 Section 3.6 for details.\r
2674\r
2675 @param[in] Slot The slot number of the SD card to send the command to.\r
2676\r
2677 @retval EFI_SUCCESS There is a SD card.\r
2678 @retval Others There is not a SD card.\r
2679\r
2680**/\r
2681EFI_STATUS\r
2682SdPeimIdentification (\r
2683 IN SD_PEIM_HC_SLOT *Slot\r
2684 )\r
2685{\r
2686 EFI_STATUS Status;\r
2687 UINT32 Ocr;\r
2688 UINT16 Rca;\r
2689 BOOLEAN Xpc;\r
2690 BOOLEAN S18r;\r
2691 UINT64 MaxCurrent;\r
2692 UINT64 Current;\r
2693 UINT16 ControllerVer;\r
2694 UINT8 PowerCtrl;\r
2695 UINT32 PresentState;\r
2696 UINT8 HostCtrl2;\r
2697 SD_HC_SLOT_CAP Capability;\r
2698\r
2699 //\r
2700 // 1. Send Cmd0 to the device\r
2701 //\r
2702 Status = SdPeimReset (Slot);\r
2703 if (EFI_ERROR (Status)) {\r
2704 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd0 fails with %r\n", Status));\r
2705 return Status;\r
2706 }\r
2707 //\r
2708 // 2. Send Cmd8 to the device\r
2709 //\r
2710 Status = SdPeimVoltageCheck (Slot, 0x1, 0xFF);\r
2711 if (EFI_ERROR (Status)) {\r
2712 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd8 fails with %r\n", Status));\r
2713 return Status;\r
2714 }\r
2715 //\r
2716 // 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.\r
2717 //\r
2718 Status = SdioSendOpCond (Slot, 0, FALSE);\r
2719 if (!EFI_ERROR (Status)) {\r
2720 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Found SDIO device, ignore it as we don't support\n"));\r
2721 return EFI_DEVICE_ERROR;\r
2722 }\r
2723 //\r
2724 // 4. Send Acmd41 with voltage window 0 to the device\r
2725 //\r
2726 Status = SdPeimSendOpCond (Slot, 0, 0, FALSE, FALSE, FALSE, &Ocr);\r
2727 if (EFI_ERROR (Status)) {\r
2728 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSendOpCond fails with %r\n", Status));\r
2729 return EFI_DEVICE_ERROR;\r
2730 }\r
2731\r
2732 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);\r
2733 if (EFI_ERROR (Status)) {\r
2734 return Status;\r
2735 }\r
2736\r
2737 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_MAX_CURRENT_CAP, TRUE, sizeof (Current), &Current);\r
2738 if (EFI_ERROR (Status)) {\r
2739 return Status;\r
2740 }\r
2741\r
2742 if (Capability.Voltage33 != 0) {\r
2743 //\r
2744 // Support 3.3V\r
2745 //\r
2746 MaxCurrent = ((UINT32)Current & 0xFF) * 4;\r
2747 } else if (Capability.Voltage30 != 0) {\r
2748 //\r
2749 // Support 3.0V\r
2750 //\r
2751 MaxCurrent = (((UINT32)Current >> 8) & 0xFF) * 4;\r
2752 } else if (Capability.Voltage18 != 0) {\r
2753 //\r
2754 // Support 1.8V\r
2755 //\r
2756 MaxCurrent = (((UINT32)Current >> 16) & 0xFF) * 4;\r
2757 } else {\r
2758 ASSERT (FALSE);\r
2759 return EFI_DEVICE_ERROR;\r
2760 }\r
2761\r
2762 if (MaxCurrent >= 150) {\r
2763 Xpc = TRUE;\r
2764 } else {\r
2765 Xpc = FALSE;\r
2766 }\r
2767\r
2768 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r
2769 if (EFI_ERROR (Status)) {\r
2770 return Status;\r
2771 }\r
2772\r
2773 if ((ControllerVer & 0xFF) == 2) {\r
2774 S18r = TRUE;\r
2775 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
2776 S18r = FALSE;\r
2777 } else {\r
2778 ASSERT (FALSE);\r
2779 return EFI_UNSUPPORTED;\r
2780 }\r
2781 //\r
2782 // 5. Repeatly send Acmd41 with supply voltage window to the device.\r
2783 // Note here we only support the cards complied with SD physical\r
2784 // layer simplified spec version 2.0 and version 3.0 and above.\r
2785 //\r
2786 do {\r
2787 Status = SdPeimSendOpCond (Slot, 0, Ocr, S18r, Xpc, TRUE, &Ocr);\r
2788 if (EFI_ERROR (Status)) {\r
2789 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SdPeimSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", Status, Ocr, S18r, Xpc));\r
2790 return EFI_DEVICE_ERROR;\r
2791 }\r
2792 } while ((Ocr & BIT31) == 0);\r
2793\r
2794 //\r
2795 // 6. If the S18a bit is set and the Host Controller supports 1.8V signaling\r
2796 // (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the\r
2797 // Capabilities register), switch its voltage to 1.8V.\r
2798 //\r
2799 if ((Capability.Sdr50 != 0 ||\r
2800 Capability.Sdr104 != 0 ||\r
2801 Capability.Ddr50 != 0) &&\r
2802 ((Ocr & BIT24) != 0)) {\r
2803 Status = SdPeimVoltageSwitch (Slot);\r
2804 if (EFI_ERROR (Status)) {\r
2805 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimVoltageSwitch fails with %r\n", Status));\r
2806 Status = EFI_DEVICE_ERROR;\r
2807 goto Error;\r
2808 } else {\r
2809 Status = SdPeimHcStopClock (Slot->SdHcBase);\r
2810 if (EFI_ERROR (Status)) {\r
2811 Status = EFI_DEVICE_ERROR;\r
2812 goto Error;\r
2813 }\r
2814\r
2815 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
2816 if (((PresentState >> 20) & 0xF) != 0) {\r
2817 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x\n", PresentState));\r
2818 Status = EFI_DEVICE_ERROR;\r
2819 goto Error;\r
2820 }\r
2821 HostCtrl2 = BIT3;\r
2822 SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2823\r
2824 MicroSecondDelay (5000);\r
2825\r
2826 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);\r
2827 if ((HostCtrl2 & BIT3) == 0) {\r
2828 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with HostCtrl2 = 0x%x\n", HostCtrl2));\r
2829 Status = EFI_DEVICE_ERROR;\r
2830 goto Error;\r
2831 }\r
2832\r
2833 SdPeimHcInitClockFreq (Slot->SdHcBase);\r
2834\r
2835 MicroSecondDelay (1);\r
2836\r
2837 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
2838 if (((PresentState >> 20) & 0xF) != 0xF) {\r
2839 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x, It should be 0xF\n", PresentState));\r
2840 Status = EFI_DEVICE_ERROR;\r
2841 goto Error;\r
2842 }\r
2843 }\r
2844 DEBUG ((EFI_D_INFO, "SdPeimIdentification: Switch to 1.8v signal voltage success\n"));\r
2845 }\r
2846\r
2847 Status = SdPeimAllSendCid (Slot);\r
2848 if (EFI_ERROR (Status)) {\r
2849 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimAllSendCid fails with %r\n", Status));\r
2850 return Status;\r
2851 }\r
2852\r
2853 Status = SdPeimSetRca (Slot, &Rca);\r
2854 if (EFI_ERROR (Status)) {\r
2855 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSetRca fails with %r\n", Status));\r
2856 return Status;\r
2857 }\r
2858 //\r
2859 // Enter Data Tranfer Mode.\r
2860 //\r
2861 DEBUG ((EFI_D_INFO, "Found a SD device at slot [%d]\n", Slot));\r
2862\r
2863 Status = SdPeimSetBusMode (Slot, Rca, ((Ocr & BIT24) != 0));\r
2864\r
2865 return Status;\r
2866\r
2867Error:\r
2868 //\r
2869 // Set SD Bus Power = 0\r
2870 //\r
2871 PowerCtrl = (UINT8)~BIT0;\r
2872 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);\r
2873 return EFI_DEVICE_ERROR;\r
2874}\r
EFI Development Kit II mirror for PVE