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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r | |
4 | This program and the accompanying materials\r | |
5 | are licensed and made available under the terms and conditions of the BSD License\r | |
6 | which accompanies this distribution. The full text of the license may be found at\r | |
7 | http://opensource.org/licenses/bsd-license.php.\r | |
8 | \r | |
9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | \r | |
12 | **/\r | |
13 | \r | |
14 | #ifndef _SD_HCI_H_\r | |
15 | #define _SD_HCI_H_\r | |
16 | \r | |
17 | //\r | |
18 | // SD Host Controller MMIO Register Offset\r | |
19 | //\r | |
20 | #define SD_HC_SDMA_ADDR 0x00\r | |
21 | #define SD_HC_ARG2 0x00\r | |
22 | #define SD_HC_BLK_SIZE 0x04\r | |
23 | #define SD_HC_BLK_COUNT 0x06\r | |
24 | #define SD_HC_ARG1 0x08\r | |
25 | #define SD_HC_TRANS_MOD 0x0C\r | |
26 | #define SD_HC_COMMAND 0x0E\r | |
27 | #define SD_HC_RESPONSE 0x10\r | |
28 | #define SD_HC_BUF_DAT_PORT 0x20\r | |
29 | #define SD_HC_PRESENT_STATE 0x24\r | |
30 | #define SD_HC_HOST_CTRL1 0x28\r | |
31 | #define SD_HC_POWER_CTRL 0x29\r | |
32 | #define SD_HC_BLK_GAP_CTRL 0x2A\r | |
33 | #define SD_HC_WAKEUP_CTRL 0x2B\r | |
34 | #define SD_HC_CLOCK_CTRL 0x2C\r | |
35 | #define SD_HC_TIMEOUT_CTRL 0x2E\r | |
36 | #define SD_HC_SW_RST 0x2F\r | |
37 | #define SD_HC_NOR_INT_STS 0x30\r | |
38 | #define SD_HC_ERR_INT_STS 0x32\r | |
39 | #define SD_HC_NOR_INT_STS_EN 0x34\r | |
40 | #define SD_HC_ERR_INT_STS_EN 0x36\r | |
41 | #define SD_HC_NOR_INT_SIG_EN 0x38\r | |
42 | #define SD_HC_ERR_INT_SIG_EN 0x3A\r | |
43 | #define SD_HC_AUTO_CMD_ERR_STS 0x3C\r | |
44 | #define SD_HC_HOST_CTRL2 0x3E\r | |
45 | #define SD_HC_CAP 0x40\r | |
46 | #define SD_HC_MAX_CURRENT_CAP 0x48\r | |
47 | #define SD_HC_FORCE_EVT_AUTO_CMD 0x50\r | |
48 | #define SD_HC_FORCE_EVT_ERR_INT 0x52\r | |
49 | #define SD_HC_ADMA_ERR_STS 0x54\r | |
50 | #define SD_HC_ADMA_SYS_ADDR 0x58\r | |
51 | #define SD_HC_PRESET_VAL 0x60\r | |
52 | #define SD_HC_SHARED_BUS_CTRL 0xE0\r | |
53 | #define SD_HC_SLOT_INT_STS 0xFC\r | |
54 | #define SD_HC_CTRL_VER 0xFE\r | |
55 | \r | |
56 | //\r | |
57 | // The transfer modes supported by SD Host Controller\r | |
58 | // Simplified Spec 3.0 Table 1-2\r | |
59 | //\r | |
60 | typedef enum {\r | |
61 | SdNoData,\r | |
62 | SdPioMode,\r | |
63 | SdSdmaMode,\r | |
64 | SdAdmaMode\r | |
65 | } SD_HC_TRANSFER_MODE;\r | |
66 | \r | |
67 | //\r | |
68 | // The maximum data length of each descriptor line\r | |
69 | //\r | |
70 | #define ADMA_MAX_DATA_PER_LINE 0x10000\r | |
71 | #define SD_SDMA_BOUNDARY 512 * 1024\r | |
72 | #define SD_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r | |
73 | \r | |
74 | typedef enum {\r | |
75 | SdCommandTypeBc, // Broadcast commands, no response\r | |
76 | SdCommandTypeBcr, // Broadcast commands with response\r | |
77 | SdCommandTypeAc, // Addressed(point-to-point) commands\r | |
78 | SdCommandTypeAdtc // Addressed(point-to-point) data transfer commands\r | |
79 | } SD_COMMAND_TYPE;\r | |
80 | \r | |
81 | typedef enum {\r | |
82 | SdResponseTypeR1,\r | |
83 | SdResponseTypeR1b,\r | |
84 | SdResponseTypeR2,\r | |
85 | SdResponseTypeR3,\r | |
86 | SdResponseTypeR4,\r | |
87 | SdResponseTypeR5,\r | |
88 | SdResponseTypeR5b,\r | |
89 | SdResponseTypeR6,\r | |
90 | SdResponseTypeR7\r | |
91 | } SD_RESPONSE_TYPE;\r | |
92 | \r | |
93 | typedef struct _SD_COMMAND_BLOCK {\r | |
94 | UINT16 CommandIndex;\r | |
95 | UINT32 CommandArgument;\r | |
96 | UINT32 CommandType; // One of the SD_COMMAND_TYPE values\r | |
97 | UINT32 ResponseType; // One of the SD_RESPONSE_TYPE values\r | |
98 | } SD_COMMAND_BLOCK;\r | |
99 | \r | |
100 | typedef struct _SD_STATUS_BLOCK {\r | |
101 | UINT32 Resp0;\r | |
102 | UINT32 Resp1;\r | |
103 | UINT32 Resp2;\r | |
104 | UINT32 Resp3;\r | |
105 | } SD_STATUS_BLOCK;\r | |
106 | \r | |
107 | typedef struct _SD_COMMAND_PACKET {\r | |
108 | UINT64 Timeout;\r | |
109 | SD_COMMAND_BLOCK *SdCmdBlk;\r | |
110 | SD_STATUS_BLOCK *SdStatusBlk;\r | |
111 | VOID *InDataBuffer;\r | |
112 | VOID *OutDataBuffer;\r | |
113 | UINT32 InTransferLength;\r | |
114 | UINT32 OutTransferLength;\r | |
115 | } SD_COMMAND_PACKET;\r | |
116 | \r | |
117 | #pragma pack(1)\r | |
118 | \r | |
119 | typedef struct {\r | |
120 | UINT32 Valid:1;\r | |
121 | UINT32 End:1;\r | |
122 | UINT32 Int:1;\r | |
123 | UINT32 Reserved:1;\r | |
124 | UINT32 Act:2;\r | |
125 | UINT32 Reserved1:10;\r | |
126 | UINT32 Length:16;\r | |
127 | UINT32 Address;\r | |
128 | } SD_HC_ADMA_DESC_LINE;\r | |
129 | \r | |
130 | typedef struct {\r | |
131 | UINT32 TimeoutFreq:6; // bit 0:5\r | |
132 | UINT32 Reserved:1; // bit 6\r | |
133 | UINT32 TimeoutUnit:1; // bit 7\r | |
134 | UINT32 BaseClkFreq:8; // bit 8:15\r | |
135 | UINT32 MaxBlkLen:2; // bit 16:17\r | |
136 | UINT32 BusWidth8:1; // bit 18\r | |
137 | UINT32 Adma2:1; // bit 19\r | |
138 | UINT32 Reserved2:1; // bit 20\r | |
139 | UINT32 HighSpeed:1; // bit 21\r | |
140 | UINT32 Sdma:1; // bit 22\r | |
141 | UINT32 SuspRes:1; // bit 23\r | |
142 | UINT32 Voltage33:1; // bit 24\r | |
143 | UINT32 Voltage30:1; // bit 25\r | |
144 | UINT32 Voltage18:1; // bit 26\r | |
145 | UINT32 Reserved3:1; // bit 27\r | |
146 | UINT32 SysBus64:1; // bit 28\r | |
147 | UINT32 AsyncInt:1; // bit 29\r | |
148 | UINT32 SlotType:2; // bit 30:31\r | |
149 | UINT32 Sdr50:1; // bit 32\r | |
150 | UINT32 Sdr104:1; // bit 33\r | |
151 | UINT32 Ddr50:1; // bit 34\r | |
152 | UINT32 Reserved4:1; // bit 35\r | |
153 | UINT32 DriverTypeA:1; // bit 36\r | |
154 | UINT32 DriverTypeC:1; // bit 37\r | |
155 | UINT32 DriverTypeD:1; // bit 38\r | |
156 | UINT32 DriverType4:1; // bit 39\r | |
157 | UINT32 TimerCount:4; // bit 40:43\r | |
158 | UINT32 Reserved5:1; // bit 44\r | |
159 | UINT32 TuningSDR50:1; // bit 45\r | |
160 | UINT32 RetuningMod:2; // bit 46:47\r | |
161 | UINT32 ClkMultiplier:8; // bit 48:55\r | |
162 | UINT32 Reserved6:7; // bit 56:62\r | |
163 | UINT32 Hs400:1; // bit 63\r | |
164 | } SD_HC_SLOT_CAP;\r | |
165 | \r | |
166 | #pragma pack()\r | |
167 | \r | |
168 | /**\r | |
169 | Software reset the specified SD host controller and enable all interrupts.\r | |
170 | \r | |
171 | @param[in] Bar The mmio base address of the slot to be accessed.\r | |
172 | \r | |
173 | @retval EFI_SUCCESS The software reset executes successfully.\r | |
174 | @retval Others The software reset fails.\r | |
175 | \r | |
176 | **/\r | |
177 | EFI_STATUS\r | |
178 | SdPeimHcReset (\r | |
179 | IN UINTN Bar\r | |
180 | );\r | |
181 | \r | |
182 | /**\r | |
183 | Set all interrupt status bits in Normal and Error Interrupt Status Enable\r | |
184 | register.\r | |
185 | \r | |
186 | @param[in] Bar The mmio base address of the slot to be accessed.\r | |
187 | \r | |
188 | @retval EFI_SUCCESS The operation executes successfully.\r | |
189 | @retval Others The operation fails.\r | |
190 | \r | |
191 | **/\r | |
192 | EFI_STATUS\r | |
193 | SdPeimHcEnableInterrupt (\r | |
194 | IN UINTN Bar\r | |
195 | );\r | |
196 | \r | |
197 | /**\r | |
198 | Get the capability data from the specified slot.\r | |
199 | \r | |
200 | @param[in] Bar The mmio base address of the slot to be accessed.\r | |
201 | @param[out] Capability The buffer to store the capability data.\r | |
202 | \r | |
203 | @retval EFI_SUCCESS The operation executes successfully.\r | |
204 | @retval Others The operation fails.\r | |
205 | \r | |
206 | **/\r | |
207 | EFI_STATUS\r | |
208 | SdPeimHcGetCapability (\r | |
209 | IN UINTN Bar,\r | |
210 | OUT SD_HC_SLOT_CAP *Capability\r | |
211 | );\r | |
212 | \r | |
213 | /**\r | |
214 | Detect whether there is a SD card attached at the specified SD host controller\r | |
215 | slot.\r | |
216 | \r | |
217 | Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r | |
218 | \r | |
219 | @param[in] Bar The mmio base address of the slot to be accessed.\r | |
220 | \r | |
221 | @retval EFI_SUCCESS There is a SD card attached.\r | |
222 | @retval EFI_NO_MEDIA There is not a SD card attached.\r | |
223 | @retval Others The detection fails.\r | |
224 | \r | |
225 | **/\r | |
226 | EFI_STATUS\r | |
227 | SdPeimHcCardDetect (\r | |
228 | IN UINTN Bar\r | |
229 | );\r | |
230 | \r | |
231 | /**\r | |
232 | Initial SD host controller with lowest clock frequency, max power and max timeout value\r | |
233 | at initialization.\r | |
234 | \r | |
235 | @param[in] Bar The mmio base address of the slot to be accessed.\r | |
236 | \r | |
237 | @retval EFI_SUCCESS The host controller is initialized successfully.\r | |
238 | @retval Others The host controller isn't initialized successfully.\r | |
239 | \r | |
240 | **/\r | |
241 | EFI_STATUS\r | |
242 | SdPeimHcInitHost (\r | |
243 | IN UINTN Bar\r | |
244 | );\r | |
245 | \r | |
246 | /**\r | |
247 | Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.\r | |
248 | \r | |
249 | Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r | |
250 | \r | |
251 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
252 | @param[in] AccessMode The value for access mode group.\r | |
253 | @param[in] CommandSystem The value for command set group.\r | |
254 | @param[in] DriveStrength The value for drive length group.\r | |
255 | @param[in] PowerLimit The value for power limit group.\r | |
256 | @param[in] Mode Switch or check function.\r | |
257 | \r | |
258 | @retval EFI_SUCCESS The operation is done correctly.\r | |
259 | @retval Others The operation fails.\r | |
260 | \r | |
261 | **/\r | |
262 | EFI_STATUS\r | |
263 | SdPeimSwitch (\r | |
264 | IN SD_PEIM_HC_SLOT *Slot,\r | |
265 | IN UINT8 AccessMode,\r | |
266 | IN UINT8 CommandSystem,\r | |
267 | IN UINT8 DriveStrength,\r | |
268 | IN UINT8 PowerLimit,\r | |
269 | IN BOOLEAN Mode\r | |
270 | );\r | |
271 | \r | |
272 | /**\r | |
273 | Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device\r | |
274 | to read/write the specified number of blocks.\r | |
275 | \r | |
276 | Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.\r | |
277 | \r | |
278 | @param[in] Slot The slot number of the SD card to send the command to.\r | |
279 | @param[in] Lba The logical block address of starting access.\r | |
280 | @param[in] BlockSize The block size of specified SD device partition.\r | |
281 | @param[in] Buffer The pointer to the transfer buffer.\r | |
282 | @param[in] BufferSize The size of transfer buffer.\r | |
283 | @param[in] IsRead Boolean to show the operation direction.\r | |
284 | \r | |
285 | @retval EFI_SUCCESS The operation is done correctly.\r | |
286 | @retval Others The operation fails.\r | |
287 | \r | |
288 | **/\r | |
289 | EFI_STATUS\r | |
290 | SdPeimRwSingleBlock (\r | |
291 | IN SD_PEIM_HC_SLOT *Slot,\r | |
292 | IN EFI_LBA Lba,\r | |
293 | IN UINT32 BlockSize,\r | |
294 | IN VOID *Buffer,\r | |
295 | IN UINTN BufferSize,\r | |
296 | IN BOOLEAN IsRead\r | |
297 | );\r | |
298 | \r | |
299 | /**\r | |
300 | Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device\r | |
301 | to read/write the specified number of blocks.\r | |
302 | \r | |
303 | Refer to SD Electrical Standard Spec 5.1 Section 6.10.4 for details.\r | |
304 | \r | |
305 | @param[in] Slot The slot number of the Sd card to send the command to.\r | |
306 | @param[in] Lba The logical block address of starting access.\r | |
307 | @param[in] BlockSize The block size of specified SD device partition.\r | |
308 | @param[in] Buffer The pointer to the transfer buffer.\r | |
309 | @param[in] BufferSize The size of transfer buffer.\r | |
310 | @param[in] IsRead Boolean to show the operation direction.\r | |
311 | \r | |
312 | @retval EFI_SUCCESS The operation is done correctly.\r | |
313 | @retval Others The operation fails.\r | |
314 | \r | |
315 | **/\r | |
316 | EFI_STATUS\r | |
317 | SdPeimRwMultiBlocks (\r | |
318 | IN SD_PEIM_HC_SLOT *Slot,\r | |
319 | IN EFI_LBA Lba,\r | |
320 | IN UINT32 BlockSize,\r | |
321 | IN VOID *Buffer,\r | |
322 | IN UINTN BufferSize,\r | |
323 | IN BOOLEAN IsRead\r | |
324 | );\r | |
325 | \r | |
326 | /**\r | |
327 | Execute SD device identification procedure.\r | |
328 | \r | |
329 | Refer to SD Electrical Standard Spec 5.1 Section 6.4 for details.\r | |
330 | \r | |
331 | @param[in] Slot The slot number of the Sd card to send the command to.\r | |
332 | \r | |
333 | @retval EFI_SUCCESS There is a SD card.\r | |
334 | @retval Others There is not a SD card.\r | |
335 | \r | |
336 | **/\r | |
337 | EFI_STATUS\r | |
338 | SdPeimIdentification (\r | |
339 | IN SD_PEIM_HC_SLOT *Slot\r | |
340 | );\r | |
341 | \r | |
342 | /**\r | |
343 | Free the resource used by the TRB.\r | |
344 | \r | |
345 | @param[in] Trb The pointer to the SD_TRB instance.\r | |
346 | \r | |
347 | **/\r | |
348 | VOID\r | |
349 | SdPeimFreeTrb (\r | |
350 | IN SD_TRB *Trb\r | |
351 | );\r | |
352 | \r | |
353 | #endif\r | |
354 | \r |