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504214c4 LG |
1 | /** @file \r |
2 | \r | |
3 | Task priority (TPL) function \r | |
28a00297 | 4 | \r |
504214c4 | 5 | Copyright (c) 2006 - 2008, Intel Corporation \r |
28a00297 | 6 | All rights reserved. This program and the accompanying materials \r |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
504214c4 | 14 | **/\r |
28a00297 | 15 | \r |
16 | #include <DxeMain.h>\r | |
17 | \r | |
18 | STATIC\r | |
19 | VOID\r | |
20 | CoreSetInterruptState (\r | |
21 | IN BOOLEAN Enable\r | |
22 | )\r | |
23 | /*++\r | |
24 | \r | |
25 | Routine Description:\r | |
26 | \r | |
27 | Set Interrupt State\r | |
28 | \r | |
29 | Arguments:\r | |
30 | \r | |
31 | Enable - The state of enable or disable interrupt\r | |
32 | \r | |
33 | Returns:\r | |
34 | \r | |
35 | None\r | |
36 | \r | |
37 | --*/\r | |
38 | \r | |
39 | {\r | |
40 | if (gCpu != NULL) {\r | |
41 | if (Enable) {\r | |
42 | gCpu->EnableInterrupt(gCpu);\r | |
43 | } else {\r | |
44 | gCpu->DisableInterrupt(gCpu);\r | |
45 | }\r | |
46 | }\r | |
47 | }\r | |
48 | \r | |
49 | //\r | |
50 | // Return the highest set bit\r | |
51 | //\r | |
52 | UINTN\r | |
53 | CoreHighestSetBit (\r | |
54 | IN UINTN Number\r | |
55 | )\r | |
56 | /*++\r | |
57 | \r | |
58 | Routine Description:\r | |
59 | \r | |
60 | Return the highest set bit\r | |
61 | \r | |
62 | Arguments:\r | |
63 | \r | |
64 | Number - The value to check\r | |
65 | \r | |
66 | Returns:\r | |
67 | \r | |
68 | Bit position of the highest set bit\r | |
69 | \r | |
70 | --*/\r | |
71 | {\r | |
72 | UINTN msb;\r | |
73 | \r | |
74 | msb = 31;\r | |
75 | while ((msb > 0) && ((Number & (UINTN)(1 << msb)) == 0)) {\r | |
76 | msb--;\r | |
77 | }\r | |
78 | \r | |
79 | return msb;\r | |
80 | }\r | |
81 | \r | |
82 | \r | |
83 | \r | |
84 | EFI_TPL\r | |
85 | EFIAPI\r | |
86 | CoreRaiseTpl (\r | |
87 | IN EFI_TPL NewTpl\r | |
88 | )\r | |
89 | /*++\r | |
90 | \r | |
91 | Routine Description:\r | |
92 | \r | |
93 | Raise the task priority level to the new level.\r | |
94 | High level is implemented by disabling processor interrupts.\r | |
95 | \r | |
96 | Arguments:\r | |
97 | \r | |
98 | NewTpl - New task priority level\r | |
99 | \r | |
100 | Returns:\r | |
101 | \r | |
102 | The previous task priority level\r | |
103 | \r | |
104 | --*/\r | |
105 | {\r | |
106 | EFI_TPL OldTpl;\r | |
107 | \r | |
108 | OldTpl = gEfiCurrentTpl;\r | |
109 | ASSERT (OldTpl <= NewTpl);\r | |
110 | ASSERT (VALID_TPL (NewTpl));\r | |
111 | \r | |
112 | //\r | |
113 | // If raising to high level, disable interrupts\r | |
114 | //\r | |
115 | if (NewTpl >= TPL_HIGH_LEVEL && OldTpl < TPL_HIGH_LEVEL) {\r | |
116 | CoreSetInterruptState (FALSE);\r | |
117 | }\r | |
118 | \r | |
119 | //\r | |
120 | // Set the new value\r | |
121 | //\r | |
122 | gEfiCurrentTpl = NewTpl;\r | |
123 | \r | |
124 | return OldTpl;\r | |
125 | }\r | |
126 | \r | |
127 | \r | |
128 | \r | |
129 | VOID\r | |
130 | EFIAPI\r | |
131 | CoreRestoreTpl (\r | |
132 | IN EFI_TPL NewTpl\r | |
133 | )\r | |
134 | /*++\r | |
135 | \r | |
136 | Routine Description:\r | |
137 | \r | |
138 | Lowers the task priority to the previous value. If the new \r | |
139 | priority unmasks events at a higher priority, they are dispatched.\r | |
140 | \r | |
141 | Arguments:\r | |
142 | \r | |
143 | NewTpl - New, lower, task priority\r | |
144 | \r | |
145 | Returns:\r | |
146 | \r | |
147 | None\r | |
148 | \r | |
149 | --*/\r | |
150 | {\r | |
151 | EFI_TPL OldTpl;\r | |
152 | \r | |
153 | OldTpl = gEfiCurrentTpl;\r | |
154 | ASSERT (NewTpl <= OldTpl);\r | |
155 | ASSERT (VALID_TPL (NewTpl));\r | |
156 | \r | |
157 | //\r | |
158 | // If lowering below HIGH_LEVEL, make sure\r | |
159 | // interrupts are enabled\r | |
160 | //\r | |
161 | \r | |
162 | if (OldTpl >= TPL_HIGH_LEVEL && NewTpl < TPL_HIGH_LEVEL) {\r | |
163 | gEfiCurrentTpl = TPL_HIGH_LEVEL; \r | |
164 | }\r | |
165 | \r | |
166 | //\r | |
167 | // Dispatch any pending events\r | |
168 | //\r | |
169 | \r | |
170 | while ((-2 << NewTpl) & gEventPending) {\r | |
171 | gEfiCurrentTpl = CoreHighestSetBit (gEventPending);\r | |
172 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
173 | CoreSetInterruptState (TRUE);\r | |
174 | }\r | |
175 | CoreDispatchEventNotifies (gEfiCurrentTpl);\r | |
176 | }\r | |
177 | \r | |
178 | //\r | |
179 | // Set the new value\r | |
180 | //\r | |
181 | \r | |
182 | gEfiCurrentTpl = NewTpl;\r | |
183 | \r | |
184 | //\r | |
185 | // If lowering below HIGH_LEVEL, make sure\r | |
186 | // interrupts are enabled\r | |
187 | //\r | |
188 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
189 | CoreSetInterruptState (TRUE);\r | |
190 | }\r | |
191 | \r | |
192 | }\r |