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96226baa | 1 | /** @file\r |
48557c65 | 2 | Ia32-specific functionality for DxeLoad.\r |
95276127 | 3 | \r |
5630cdfe | 4 | Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r |
cd5ebaa0 | 5 | This program and the accompanying materials\r |
95276127 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
96226baa | 13 | **/\r |
95276127 | 14 | \r |
95276127 | 15 | #include "DxeIpl.h"\r |
16 | #include "VirtualMemory.h"\r | |
17 | \r | |
df7aaeb9 | 18 | #define IDT_ENTRY_COUNT 32\r |
e7af83ae | 19 | \r |
bdfbe63e | 20 | typedef struct _X64_IDT_TABLE {\r |
21 | //\r | |
22 | // Reserved 4 bytes preceding PeiService and IdtTable,\r | |
23 | // since IDT base address should be 8-byte alignment.\r | |
24 | //\r | |
25 | UINT32 Reserved;\r | |
26 | CONST EFI_PEI_SERVICES **PeiService;\r | |
27 | X64_IDT_GATE_DESCRIPTOR IdtTable[IDT_ENTRY_COUNT];\r | |
28 | } X64_IDT_TABLE;\r | |
29 | \r | |
95276127 | 30 | //\r |
31 | // Global Descriptor Table (GDT)\r | |
32 | //\r | |
b98da1b1 | 33 | GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries[] = {\r |
0cf27ce0 | 34 | /* selector { Global Segment Descriptor } */\r |
35 | /* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor\r | |
95276127 | 36 | /* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor\r |
37 | /* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear code segment descriptor\r | |
38 | /* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor\r | |
39 | /* 0x20 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system code segment descriptor\r | |
40 | /* 0x28 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor\r | |
41 | /* 0x30 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor\r | |
42 | /* 0x38 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 1, 0, 1, 0}}, //system code segment descriptor\r | |
43 | /* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor\r | |
44 | };\r | |
45 | \r | |
46 | //\r | |
47 | // IA32 Gdt register\r | |
48 | //\r | |
49 | GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR gGdt = {\r | |
50 | sizeof (gGdtEntries) - 1,\r | |
51 | (UINTN) gGdtEntries\r | |
52 | };\r | |
53 | \r | |
5d582956 | 54 | GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDescriptor = {\r |
e7af83ae | 55 | sizeof (X64_IDT_GATE_DESCRIPTOR) * IDT_ENTRY_COUNT - 1,\r |
5d582956 | 56 | 0\r |
57 | };\r | |
58 | \r | |
5630cdfe SZ |
59 | /**\r |
60 | Allocates and fills in the Page Directory and Page Table Entries to\r | |
61 | establish a 4G page table.\r | |
62 | \r | |
63 | @param[in] StackBase Stack base address.\r | |
64 | @param[in] StackSize Stack size.\r | |
65 | \r | |
66 | @return The address of page table.\r | |
67 | \r | |
68 | **/\r | |
69 | UINTN\r | |
70 | Create4GPageTablesIa32Pae (\r | |
71 | IN EFI_PHYSICAL_ADDRESS StackBase,\r | |
72 | IN UINTN StackSize\r | |
73 | )\r | |
74 | { \r | |
75 | UINT8 PhysicalAddressBits;\r | |
76 | EFI_PHYSICAL_ADDRESS PhysicalAddress;\r | |
77 | UINTN IndexOfPdpEntries;\r | |
78 | UINTN IndexOfPageDirectoryEntries;\r | |
79 | UINT32 NumberOfPdpEntriesNeeded;\r | |
80 | PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r | |
81 | PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r | |
82 | PAGE_TABLE_ENTRY *PageDirectoryEntry;\r | |
83 | UINTN TotalPagesNum;\r | |
84 | UINTN PageAddress;\r | |
85 | \r | |
86 | PhysicalAddressBits = 32;\r | |
87 | \r | |
88 | //\r | |
89 | // Calculate the table entries needed.\r | |
90 | //\r | |
91 | NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));\r | |
92 | \r | |
93 | TotalPagesNum = NumberOfPdpEntriesNeeded + 1;\r | |
94 | PageAddress = (UINTN) AllocatePages (TotalPagesNum);\r | |
95 | ASSERT (PageAddress != 0);\r | |
96 | \r | |
97 | PageMap = (VOID *) PageAddress;\r | |
98 | PageAddress += SIZE_4KB;\r | |
99 | \r | |
100 | PageDirectoryPointerEntry = PageMap;\r | |
101 | PhysicalAddress = 0;\r | |
102 | \r | |
103 | for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r | |
104 | //\r | |
105 | // Each Directory Pointer entries points to a page of Page Directory entires.\r | |
106 | // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r | |
107 | // \r | |
108 | PageDirectoryEntry = (VOID *) PageAddress;\r | |
109 | PageAddress += SIZE_4KB;\r | |
110 | \r | |
111 | //\r | |
112 | // Fill in a Page Directory Pointer Entries\r | |
113 | //\r | |
114 | PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry;\r | |
115 | PageDirectoryPointerEntry->Bits.Present = 1;\r | |
116 | \r | |
117 | for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {\r | |
118 | if ((PhysicalAddress < StackBase + StackSize) && ((PhysicalAddress + SIZE_2MB) > StackBase)) {\r | |
119 | //\r | |
120 | // Need to split this 2M page that covers stack range.\r | |
121 | //\r | |
122 | Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize);\r | |
123 | } else {\r | |
124 | //\r | |
125 | // Fill in the Page Directory entries\r | |
126 | //\r | |
127 | PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress;\r | |
128 | PageDirectoryEntry->Bits.ReadWrite = 1;\r | |
129 | PageDirectoryEntry->Bits.Present = 1;\r | |
130 | PageDirectoryEntry->Bits.MustBe1 = 1;\r | |
131 | }\r | |
132 | }\r | |
133 | }\r | |
134 | \r | |
135 | for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r | |
136 | ZeroMem (\r | |
137 | PageDirectoryPointerEntry,\r | |
138 | sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r | |
139 | );\r | |
140 | }\r | |
141 | \r | |
142 | return (UINTN) PageMap;\r | |
143 | }\r | |
144 | \r | |
145 | /**\r | |
146 | The function will check if IA32 PAE is supported.\r | |
147 | \r | |
148 | @retval TRUE IA32 PAE is supported.\r | |
149 | @retval FALSE IA32 PAE is not supported.\r | |
150 | \r | |
151 | **/\r | |
152 | BOOLEAN\r | |
153 | IsIa32PaeSupport (\r | |
154 | VOID\r | |
155 | )\r | |
156 | {\r | |
157 | UINT32 RegEax;\r | |
158 | UINT32 RegEdx;\r | |
159 | BOOLEAN Ia32PaeSupport;\r | |
160 | \r | |
161 | Ia32PaeSupport = FALSE;\r | |
162 | AsmCpuid (0x0, &RegEax, NULL, NULL, NULL);\r | |
163 | if (RegEax >= 0x1) {\r | |
164 | AsmCpuid (0x1, NULL, NULL, NULL, &RegEdx);\r | |
165 | if ((RegEdx & BIT6) != 0) {\r | |
166 | Ia32PaeSupport = TRUE;\r | |
167 | }\r | |
168 | }\r | |
169 | \r | |
170 | return Ia32PaeSupport;\r | |
171 | }\r | |
172 | \r | |
173 | /**\r | |
174 | The function will check if Execute Disable Bit is available.\r | |
175 | \r | |
176 | @retval TRUE Execute Disable Bit is available.\r | |
177 | @retval FALSE Execute Disable Bit is not available.\r | |
178 | \r | |
179 | **/\r | |
180 | BOOLEAN\r | |
181 | IsExecuteDisableBitAvailable (\r | |
182 | VOID\r | |
183 | )\r | |
184 | {\r | |
185 | UINT32 RegEax;\r | |
186 | UINT32 RegEdx;\r | |
187 | BOOLEAN Available;\r | |
188 | \r | |
189 | Available = FALSE;\r | |
190 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
191 | if (RegEax >= 0x80000001) {\r | |
192 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
193 | if ((RegEdx & BIT20) != 0) {\r | |
194 | //\r | |
195 | // Bit 20: Execute Disable Bit available.\r | |
196 | //\r | |
197 | Available = TRUE;\r | |
198 | }\r | |
199 | }\r | |
200 | \r | |
201 | return Available;\r | |
202 | }\r | |
203 | \r | |
91d92e25 | 204 | /**\r |
205 | Transfers control to DxeCore.\r | |
206 | \r | |
207 | This function performs a CPU architecture specific operations to execute\r | |
208 | the entry point of DxeCore with the parameters of HobList.\r | |
48557c65 | 209 | It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.\r |
91d92e25 | 210 | \r |
48557c65 | 211 | @param DxeCoreEntryPoint The entry point of DxeCore.\r |
91d92e25 | 212 | @param HobList The start of HobList passed to DxeCore.\r |
91d92e25 | 213 | \r |
214 | **/\r | |
95276127 | 215 | VOID\r |
216 | HandOffToDxeCore (\r | |
217 | IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,\r | |
9b937a73 | 218 | IN EFI_PEI_HOB_POINTERS HobList\r |
95276127 | 219 | )\r |
220 | {\r | |
221 | EFI_STATUS Status;\r | |
222 | EFI_PHYSICAL_ADDRESS BaseOfStack;\r | |
223 | EFI_PHYSICAL_ADDRESS TopOfStack;\r | |
224 | UINTN PageTables;\r | |
5d582956 | 225 | X64_IDT_GATE_DESCRIPTOR *IdtTable;\r |
226 | UINTN SizeOfTemplate;\r | |
227 | VOID *TemplateBase;\r | |
228 | EFI_PHYSICAL_ADDRESS VectorAddress;\r | |
229 | UINT32 Index;\r | |
bdfbe63e | 230 | X64_IDT_TABLE *IdtTableForX64;\r |
57f360f2 JF |
231 | EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r |
232 | EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;\r | |
5630cdfe | 233 | BOOLEAN BuildPageTablesIa32Pae;\r |
95276127 | 234 | \r |
235 | Status = PeiServicesAllocatePages (EfiBootServicesData, EFI_SIZE_TO_PAGES (STACK_SIZE), &BaseOfStack);\r | |
236 | ASSERT_EFI_ERROR (Status);\r | |
0cf27ce0 | 237 | \r |
95276127 | 238 | if (FeaturePcdGet(PcdDxeIplSwitchToLongMode)) {\r |
239 | //\r | |
0cf27ce0 | 240 | // Compute the top of the stack we were allocated, which is used to load X64 dxe core.\r |
95276127 | 241 | // Pre-allocate a 32 bytes which confroms to x64 calling convention.\r |
242 | //\r | |
0cf27ce0 | 243 | // The first four parameters to a function are passed in rcx, rdx, r8 and r9.\r |
244 | // Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the\r | |
245 | // register parameters is reserved on the stack, in case the called function\r | |
246 | // wants to spill them; this is important if the function is variadic.\r | |
95276127 | 247 | //\r |
248 | TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - 32;\r | |
249 | \r | |
250 | //\r | |
b98da1b1 | 251 | // x64 Calling Conventions requires that the stack must be aligned to 16 bytes\r |
95276127 | 252 | //\r |
253 | TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, 16);\r | |
254 | \r | |
255 | //\r | |
256 | // Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA\r | |
0cf27ce0 | 257 | // memory, it may be corrupted when copying FV to high-end memory\r |
95276127 | 258 | //\r |
259 | AsmWriteGdtr (&gGdt);\r | |
260 | //\r | |
261 | // Create page table and save PageMapLevel4 to CR3\r | |
262 | //\r | |
5630cdfe | 263 | PageTables = CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZE);\r |
95276127 | 264 | \r |
265 | //\r | |
48557c65 | 266 | // End of PEI phase signal\r |
95276127 | 267 | //\r |
9b937a73 | 268 | Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r |
95276127 | 269 | ASSERT_EFI_ERROR (Status);\r |
0cf27ce0 | 270 | \r |
95276127 | 271 | AsmWriteCr3 (PageTables);\r |
5d582956 | 272 | \r |
30c8f861 | 273 | //\r |
274 | // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r | |
0cf27ce0 | 275 | //\r |
30c8f861 | 276 | UpdateStackHob (BaseOfStack, STACK_SIZE);\r |
5d582956 | 277 | \r |
4bfa7dc4 | 278 | SizeOfTemplate = AsmGetVectorTemplatInfo (&TemplateBase);\r |
279 | \r | |
280 | Status = PeiServicesAllocatePages (\r | |
0cf27ce0 | 281 | EfiBootServicesData,\r |
bdfbe63e | 282 | EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE) + SizeOfTemplate * IDT_ENTRY_COUNT),\r |
283 | (EFI_PHYSICAL_ADDRESS *) &IdtTableForX64\r | |
4bfa7dc4 | 284 | );\r |
285 | ASSERT_EFI_ERROR (Status);\r | |
286 | \r | |
bdfbe63e | 287 | //\r |
288 | // Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that\r | |
289 | // it may not be gotten correctly after IDT register is re-written.\r | |
290 | //\r | |
291 | IdtTableForX64->PeiService = GetPeiServicesTablePointer ();\r | |
292 | \r | |
293 | VectorAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (IdtTableForX64 + 1);\r | |
294 | IdtTable = IdtTableForX64->IdtTable;\r | |
e7af83ae | 295 | for (Index = 0; Index < IDT_ENTRY_COUNT; Index++) {\r |
4bfa7dc4 | 296 | IdtTable[Index].Ia32IdtEntry.Bits.GateType = 0x8e;\r |
297 | IdtTable[Index].Ia32IdtEntry.Bits.Reserved_0 = 0;\r | |
298 | IdtTable[Index].Ia32IdtEntry.Bits.Selector = SYS_CODE64_SEL;\r | |
299 | \r | |
300 | IdtTable[Index].Ia32IdtEntry.Bits.OffsetLow = (UINT16) VectorAddress;\r | |
301 | IdtTable[Index].Ia32IdtEntry.Bits.OffsetHigh = (UINT16) (RShiftU64 (VectorAddress, 16));\r | |
302 | IdtTable[Index].Offset32To63 = (UINT32) (RShiftU64 (VectorAddress, 32));\r | |
303 | IdtTable[Index].Reserved = 0;\r | |
304 | \r | |
305 | CopyMem ((VOID *) (UINTN) VectorAddress, TemplateBase, SizeOfTemplate);\r | |
306 | AsmVectorFixup ((VOID *) (UINTN) VectorAddress, (UINT8) Index);\r | |
307 | \r | |
308 | VectorAddress += SizeOfTemplate;\r | |
5d582956 | 309 | }\r |
4bfa7dc4 | 310 | \r |
311 | gLidtDescriptor.Base = (UINTN) IdtTable;\r | |
0cf27ce0 | 312 | \r |
e7af83ae | 313 | //\r |
314 | // Disable interrupt of Debug timer, since new IDT table cannot handle it.\r | |
315 | //\r | |
316 | SaveAndSetDebugTimerInterrupt (FALSE);\r | |
317 | \r | |
4bfa7dc4 | 318 | AsmWriteIdtr (&gLidtDescriptor);\r |
319 | \r | |
5d582956 | 320 | //\r |
b98da1b1 | 321 | // Go to Long Mode and transfer control to DxeCore.\r |
322 | // Interrupts will not get turned on until the CPU AP is loaded.\r | |
95276127 | 323 | // Call x64 drivers passing in single argument, a pointer to the HOBs.\r |
0cf27ce0 | 324 | //\r |
95276127 | 325 | AsmEnablePaging64 (\r |
326 | SYS_CODE64_SEL,\r | |
327 | DxeCoreEntryPoint,\r | |
328 | (EFI_PHYSICAL_ADDRESS)(UINTN)(HobList.Raw),\r | |
329 | 0,\r | |
330 | TopOfStack\r | |
331 | );\r | |
332 | } else {\r | |
57f360f2 JF |
333 | //\r |
334 | // Get Vector Hand-off Info PPI and build Guided HOB\r | |
335 | //\r | |
336 | Status = PeiServicesLocatePpi (\r | |
337 | &gEfiVectorHandoffInfoPpiGuid,\r | |
338 | 0,\r | |
339 | NULL,\r | |
340 | (VOID **)&VectorHandoffInfoPpi\r | |
341 | );\r | |
342 | if (Status == EFI_SUCCESS) {\r | |
343 | DEBUG ((EFI_D_INFO, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));\r | |
344 | VectorInfo = VectorHandoffInfoPpi->Info;\r | |
345 | Index = 1;\r | |
346 | while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {\r | |
347 | VectorInfo ++;\r | |
348 | Index ++;\r | |
349 | }\r | |
350 | BuildGuidDataHob (\r | |
351 | &gEfiVectorHandoffInfoPpiGuid,\r | |
352 | VectorHandoffInfoPpi->Info,\r | |
353 | sizeof (EFI_VECTOR_HANDOFF_INFO) * Index\r | |
354 | );\r | |
355 | }\r | |
356 | \r | |
95276127 | 357 | //\r |
358 | // Compute the top of the stack we were allocated. Pre-allocate a UINTN\r | |
359 | // for safety.\r | |
360 | //\r | |
361 | TopOfStack = BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT;\r | |
362 | TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);\r | |
363 | \r | |
5630cdfe SZ |
364 | BuildPageTablesIa32Pae = (BOOLEAN) (PcdGetBool (PcdSetNxForStack) && IsIa32PaeSupport () && IsExecuteDisableBitAvailable ());\r |
365 | if (BuildPageTablesIa32Pae) {\r | |
366 | PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);\r | |
367 | EnableExecuteDisableBit ();\r | |
368 | }\r | |
369 | \r | |
95276127 | 370 | //\r |
48557c65 | 371 | // End of PEI phase signal\r |
95276127 | 372 | //\r |
9b937a73 | 373 | Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);\r |
95276127 | 374 | ASSERT_EFI_ERROR (Status);\r |
375 | \r | |
5630cdfe SZ |
376 | if (BuildPageTablesIa32Pae) {\r |
377 | AsmWriteCr3 (PageTables);\r | |
378 | //\r | |
379 | // Set Physical Address Extension (bit 5 of CR4).\r | |
380 | //\r | |
381 | AsmWriteCr4 (AsmReadCr4 () | BIT5);\r | |
382 | }\r | |
383 | \r | |
30c8f861 | 384 | //\r |
385 | // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.\r | |
0cf27ce0 | 386 | //\r |
30c8f861 | 387 | UpdateStackHob (BaseOfStack, STACK_SIZE);\r |
0cf27ce0 | 388 | \r |
b98da1b1 | 389 | //\r |
390 | // Transfer the control to the entry point of DxeCore.\r | |
391 | //\r | |
5630cdfe SZ |
392 | if (BuildPageTablesIa32Pae) {\r |
393 | AsmEnablePaging32 (\r | |
394 | (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r | |
395 | HobList.Raw,\r | |
396 | NULL,\r | |
397 | (VOID *) (UINTN) TopOfStack\r | |
398 | );\r | |
399 | } else {\r | |
400 | SwitchStack (\r | |
401 | (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,\r | |
402 | HobList.Raw,\r | |
403 | NULL,\r | |
404 | (VOID *) (UINTN) TopOfStack\r | |
405 | );\r | |
406 | }\r | |
0cf27ce0 | 407 | }\r |
95276127 | 408 | }\r |
409 | \r |