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3e4df77f | 1 | /** @file\r |
2 | EFI SMM Control PPI definition.\r | |
3 | \r | |
4 | This PPI is used to initiate SMI/PMI activations. This protocol could be published by either:\r | |
5 | - A processor driver to abstract the SMI/PMI IPI\r | |
6 | - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an\r | |
7 | Intel chipset\r | |
8 | Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this\r | |
9 | event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based\r | |
10 | systems.\r | |
11 | \r | |
d1102dba | 12 | Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r |
3e4df77f | 13 | \r |
14 | This program and the accompanying materials\r | |
15 | are licensed and made available under the terms and conditions\r | |
16 | of the BSD License which accompanies this distribution. The\r | |
17 | full text of the license may be found at\r | |
18 | http://opensource.org/licenses/bsd-license.php\r | |
19 | \r | |
20 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
21 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
22 | \r | |
23 | **/\r | |
24 | \r | |
25 | \r | |
26 | #ifndef _SMM_CONTROL_PPI_H_\r | |
27 | #define _SMM_CONTROL_PPI_H_\r | |
28 | \r | |
29 | #define PEI_SMM_CONTROL_PPI_GUID \\r | |
30 | { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }\r | |
31 | \r | |
32 | typedef struct _PEI_SMM_CONTROL_PPI PEI_SMM_CONTROL_PPI;\r | |
33 | \r | |
34 | /**\r | |
35 | Invokes SMI activation from either the preboot or runtime environment.\r | |
36 | \r | |
37 | @param PeiServices General purpose services available to every PEIM.\r | |
38 | @param This The PEI_SMM_CONTROL_PPI instance.\r | |
39 | @param ArgumentBuffer The optional sized data to pass into the protocol activation.\r | |
40 | @param ArgumentBufferSize The optional size of the data.\r | |
41 | @param Periodic An optional mechanism to periodically repeat activation.\r | |
42 | @param ActivationInterval An optional parameter to repeat at this period one\r | |
43 | time or, if the Periodic Boolean is set, periodically.\r | |
44 | \r | |
45 | @retval EFI_SUCCESS The SMI/PMI has been engendered.\r | |
46 | @retval EFI_DEVICE_ERROR The timing is unsupported.\r | |
47 | @retval EFI_INVALID_PARAMETER The activation period is unsupported.\r | |
48 | @retval EFI_NOT_STARTED The SMM base service has not been initialized.\r | |
49 | \r | |
50 | **/\r | |
51 | typedef\r | |
52 | EFI_STATUS\r | |
53 | (EFIAPI *PEI_SMM_ACTIVATE) (\r | |
54 | IN EFI_PEI_SERVICES **PeiServices,\r | |
55 | IN PEI_SMM_CONTROL_PPI * This,\r | |
56 | IN OUT INT8 *ArgumentBuffer OPTIONAL,\r | |
57 | IN OUT UINTN *ArgumentBufferSize OPTIONAL,\r | |
58 | IN BOOLEAN Periodic OPTIONAL,\r | |
59 | IN UINTN ActivationInterval OPTIONAL\r | |
60 | );\r | |
61 | \r | |
62 | /**\r | |
63 | Clears any system state that was created in response to the Active call.\r | |
64 | \r | |
65 | @param PeiServices General purpose services available to every PEIM.\r | |
66 | @param This The PEI_SMM_CONTROL_PPI instance.\r | |
d1102dba | 67 | @param Periodic Optional parameter to repeat at this period one\r |
3e4df77f | 68 | time or, if the Periodic Boolean is set, periodically.\r |
69 | \r | |
70 | @retval EFI_SUCCESS The SMI/PMI has been engendered.\r | |
71 | @retval EFI_DEVICE_ERROR The source could not be cleared.\r | |
72 | @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.\r | |
73 | \r | |
74 | **/\r | |
75 | typedef\r | |
76 | EFI_STATUS\r | |
77 | (EFIAPI *PEI_SMM_DEACTIVATE) (\r | |
78 | IN EFI_PEI_SERVICES **PeiServices,\r | |
79 | IN PEI_SMM_CONTROL_PPI * This,\r | |
80 | IN BOOLEAN Periodic OPTIONAL\r | |
81 | );\r | |
82 | \r | |
83 | ///\r | |
84 | /// PEI SMM Control PPI is used to initiate SMI/PMI activations. This protocol could be published by either:\r | |
85 | /// - A processor driver to abstract the SMI/PMI IPI\r | |
86 | /// - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an\r | |
87 | /// Intel chipset\r | |
d1102dba | 88 | ///\r |
3e4df77f | 89 | struct _PEI_SMM_CONTROL_PPI {\r |
90 | PEI_SMM_ACTIVATE Trigger;\r | |
91 | PEI_SMM_DEACTIVATE Clear;\r | |
92 | };\r | |
93 | \r | |
94 | extern EFI_GUID gPeiSmmControlPpiGuid;\r | |
95 | \r | |
96 | #endif\r |