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a89fd3a3 ZG |
1 | /** @file\r |
2 | Flush the cache is required for most architectures while do capsule\r | |
3 | update. It is not support at Runtime.\r | |
4 | \r | |
5 | Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>\r | |
6 | Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r | |
7 | \r | |
9d510e61 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a89fd3a3 ZG |
9 | \r |
10 | **/\r | |
11 | \r | |
12 | #include "CapsuleService.h"\r | |
13 | \r | |
14 | #include <Library/CacheMaintenanceLib.h>\r | |
15 | \r | |
16 | /**\r | |
17 | Writes Back a range of data cache lines covering a set of capsules in memory.\r | |
18 | \r | |
19 | Writes Back the data cache lines specified by ScatterGatherList.\r | |
20 | \r | |
21 | @param ScatterGatherList Physical address of the data structure that\r | |
22 | describes a set of capsules in memory\r | |
23 | \r | |
24 | **/\r | |
25 | VOID\r | |
26 | CapsuleCacheWriteBack (\r | |
1436aea4 | 27 | IN EFI_PHYSICAL_ADDRESS ScatterGatherList\r |
a89fd3a3 ZG |
28 | )\r |
29 | {\r | |
1436aea4 | 30 | EFI_CAPSULE_BLOCK_DESCRIPTOR *Desc;\r |
a89fd3a3 ZG |
31 | \r |
32 | if (!EfiAtRuntime ()) {\r | |
33 | Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)ScatterGatherList;\r | |
34 | do {\r | |
35 | WriteBackDataCacheRange (\r | |
36 | (VOID *)(UINTN)Desc,\r | |
37 | (UINTN)sizeof (*Desc)\r | |
38 | );\r | |
39 | \r | |
40 | if (Desc->Length > 0) {\r | |
41 | WriteBackDataCacheRange (\r | |
42 | (VOID *)(UINTN)Desc->Union.DataBlock,\r | |
43 | (UINTN)Desc->Length\r | |
44 | );\r | |
45 | Desc++;\r | |
46 | } else if (Desc->Union.ContinuationPointer > 0) {\r | |
47 | Desc = (EFI_CAPSULE_BLOCK_DESCRIPTOR *)(UINTN)Desc->Union.ContinuationPointer;\r | |
48 | }\r | |
49 | } while (Desc->Length > 0 || Desc->Union.ContinuationPointer > 0);\r | |
50 | \r | |
51 | WriteBackDataCacheRange (\r | |
52 | (VOID *)(UINTN)Desc,\r | |
53 | (UINTN)sizeof (*Desc)\r | |
54 | );\r | |
55 | }\r | |
56 | }\r |