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bd86cb02 LG |
1 | /** @file\r |
2 | GUID used for MemoryOverwriteRequestControl UEFI variable defined in \r | |
3 | TCG Platform Reset Attack Mitigation Specification 1.00.\r | |
4 | See http://trustedcomputinggroup.org for the latest specification\r | |
5 | \r | |
6 | The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to \r | |
7 | indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon \r | |
8 | a restart. The OS loader should not create the variable. Rather, the firmware is required to create it. \r | |
9 | \r | |
9df063a0 HT |
10 | Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>\r |
11 | This program and the accompanying materials \r | |
bd86cb02 LG |
12 | are licensed and made available under the terms and conditions of the BSD License \r |
13 | which accompanies this distribution. The full text of the license may be found at \r | |
14 | http://opensource.org/licenses/bsd-license.php \r | |
15 | \r | |
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
18 | \r | |
19 | **/\r | |
20 | \r | |
21 | #ifndef _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_\r | |
22 | #define _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_\r | |
23 | \r | |
24 | #define MEMORY_ONLY_RESET_CONTROL_GUID \\r | |
25 | { \\r | |
26 | 0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29} \\r | |
27 | }\r | |
28 | \r | |
29 | ///\r | |
30 | /// Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value. \r | |
31 | /// The attributes should be: \r | |
32 | /// EFI_VARIABLE_NON_VOLATILE | \r | |
33 | /// EFI_VARIABLE_BOOTSERVICE_ACCESS | \r | |
34 | /// EFI_VARIABLE_RUNTIME_ACCESS \r | |
35 | ///\r | |
36 | #define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"\r | |
37 | \r | |
38 | ///\r | |
39 | /// 0 = Firmware MUST clear the MOR bi\r | |
40 | /// 1 = Firmware MUST set the MOR bit \r | |
41 | ///\r | |
42 | #define MOR_CLEAR_MEMORY_BIT_MASK 0x01\r | |
43 | \r | |
44 | ///\r | |
45 | /// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS.\r | |
46 | /// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS.\r | |
47 | ///\r | |
48 | #define MOR_DISABLEAUTODETECT_BIT_MASK 0x10\r | |
49 | \r | |
50 | ///\r | |
51 | /// MOR field bit offset\r | |
52 | ///\r | |
53 | #define MOR_CLEAR_MEMORY_BIT_OFFSET 0\r | |
54 | #define MOR_DISABLEAUTODETECT_BIT_OFFSET 4\r | |
55 | \r | |
56 | /**\r | |
57 | Return the ClearMemory bit value 0 or 1.\r | |
58 | \r | |
59 | @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.\r | |
60 | \r | |
61 | @return ClearMemory bit value\r | |
62 | **/\r | |
63 | #define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)\r | |
64 | \r | |
65 | /**\r | |
66 | Return the DisableAutoDetect bit value 0 or 1.\r | |
67 | \r | |
68 | @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.\r | |
69 | \r | |
70 | @return DisableAutoDetect bit value\r | |
71 | **/\r | |
72 | #define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)\r | |
73 | \r | |
74 | extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;\r | |
75 | \r | |
76 | #endif\r |