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1 | /** @file\r |
2 | Arm Error Source Table as described in the\r | |
3 | 'ACPI for the Armv8 RAS Extensions 1.1' Specification.\r | |
4 | \r | |
5 | Copyright (c) 2020 Arm Limited.\r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | @par Reference(s):\r | |
9 | - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document,\r | |
10 | dated 28 September 2020.\r | |
11 | (https://developer.arm.com/documentation/den0085/0101/)\r | |
12 | \r | |
13 | @par Glossary\r | |
14 | - Ref : Reference\r | |
15 | - Id : Identifier\r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef ARM_ERROR_SOURCE_TABLE_H_\r | |
19 | #define ARM_ERROR_SOURCE_TABLE_H_\r | |
20 | \r | |
21 | ///\r | |
22 | /// "AEST" Arm Error Source Table\r | |
23 | ///\r | |
24 | #define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('A', 'E', 'S', 'T')\r | |
25 | \r | |
26 | #define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1\r | |
27 | \r | |
28 | #pragma pack(1)\r | |
29 | \r | |
30 | ///\r | |
31 | /// Arm Error Source Table definition.\r | |
32 | ///\r | |
33 | typedef struct {\r | |
34 | EFI_ACPI_DESCRIPTION_HEADER Header;\r | |
35 | } EFI_ACPI_ARM_ERROR_SOURCE_TABLE;\r | |
36 | \r | |
37 | ///\r | |
38 | /// AEST Node structure.\r | |
39 | ///\r | |
40 | typedef struct {\r | |
41 | /// Node type:\r | |
42 | /// 0x00 - Processor error node\r | |
43 | /// 0x01 - Memory error node\r | |
44 | /// 0x02 - SMMU error node\r | |
45 | /// 0x03 - Vendor-defined error node\r | |
46 | /// 0x04 - GIC error node\r | |
47 | UINT8 Type;\r | |
48 | \r | |
49 | /// Length of structure in bytes.\r | |
50 | UINT16 Length;\r | |
51 | \r | |
52 | /// Reserved - Must be zero.\r | |
53 | UINT8 Reserved;\r | |
54 | \r | |
55 | /// Offset from the start of the node to node-specific data.\r | |
56 | UINT32 DataOffset;\r | |
57 | \r | |
58 | /// Offset from the start of the node to the node interface structure.\r | |
59 | UINT32 InterfaceOffset;\r | |
60 | \r | |
61 | /// Offset from the start of the node to node interrupt array.\r | |
62 | UINT32 InterruptArrayOffset;\r | |
63 | \r | |
64 | /// Number of entries in the interrupt array.\r | |
65 | UINT32 InterruptArrayCount;\r | |
66 | \r | |
67 | // Generic node data\r | |
68 | \r | |
69 | /// The timestamp frequency of the counter in Hz.\r | |
70 | UINT64 TimestampRate;\r | |
71 | \r | |
72 | /// Reserved - Must be zero.\r | |
73 | UINT64 Reserved1;\r | |
74 | \r | |
75 | /// The rate in Hz at which the Error Generation Counter decrements.\r | |
76 | UINT64 ErrorInjectionCountdownRate;\r | |
77 | } EFI_ACPI_AEST_NODE_STRUCT;\r | |
78 | \r | |
79 | // AEST Node type definitions\r | |
80 | #define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0\r | |
81 | #define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1\r | |
82 | #define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2\r | |
83 | #define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3\r | |
84 | #define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4\r | |
85 | \r | |
86 | ///\r | |
87 | /// AEST Node Interface structure.\r | |
88 | ///\r | |
89 | typedef struct {\r | |
90 | /// Interface type:\r | |
91 | /// 0x0 - System register (SR)\r | |
92 | /// 0x1 - Memory mapped (MMIO)\r | |
93 | UINT8 Type;\r | |
94 | \r | |
95 | /// Reserved - Must be zero.\r | |
96 | UINT8 Reserved[3];\r | |
97 | \r | |
98 | /// AEST node interface flags.\r | |
99 | UINT32 Flags;\r | |
100 | \r | |
101 | /// Base address of error group that contains the error node.\r | |
102 | UINT64 BaseAddress;\r | |
103 | \r | |
104 | /// Zero-based index of the first standard error record that\r | |
105 | /// belongs to this node.\r | |
106 | UINT32 StartErrorRecordIndex;\r | |
107 | \r | |
108 | /// Number of error records in this node including both\r | |
109 | /// implemented and unimplemented records.\r | |
110 | UINT32 NumberErrorRecords;\r | |
111 | \r | |
112 | /// A bitmap indicating the error records within this\r | |
113 | /// node that are implemented in the current system.\r | |
114 | UINT64 ErrorRecordImplemented;\r | |
115 | \r | |
116 | /// A bitmap indicating the error records within this node that\r | |
117 | /// support error status reporting through the ERRGSR register.\r | |
118 | UINT64 ErrorRecordStatusReportingSupported;\r | |
119 | \r | |
120 | /// A bitmap indicating the addressing mode used by each error\r | |
121 | /// record within this node to populate the ERR<n>_ADDR register.\r | |
122 | UINT64 AddressingMode;\r | |
123 | } EFI_ACPI_AEST_INTERFACE_STRUCT;\r | |
124 | \r | |
125 | // AEST Interface node type definitions.\r | |
126 | #define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0\r | |
127 | #define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1\r | |
128 | \r | |
129 | // AEST node interface flag definitions.\r | |
130 | #define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0\r | |
131 | #define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0\r | |
132 | #define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1\r | |
133 | \r | |
134 | ///\r | |
135 | /// AEST Node Interrupt structure.\r | |
136 | ///\r | |
137 | typedef struct {\r | |
138 | /// Interrupt type:\r | |
139 | /// 0x0 - Fault Handling Interrupt\r | |
140 | /// 0x1 - Error Recovery Interrupt\r | |
141 | UINT8 InterruptType;\r | |
142 | \r | |
143 | /// Reserved - Must be zero.\r | |
144 | UINT8 Reserved[2];\r | |
145 | \r | |
146 | /// Interrupt flags\r | |
147 | /// Bits [31:1]: Must be zero.\r | |
148 | /// Bit 0:\r | |
149 | /// 0b - Interrupt is edge-triggered\r | |
150 | /// 1b - Interrupt is level-triggered\r | |
151 | UINT8 InterruptFlags;\r | |
152 | \r | |
153 | /// GSIV of interrupt, if interrupt is an SPI or a PPI.\r | |
154 | UINT32 InterruptGsiv;\r | |
155 | \r | |
156 | /// If MSI is supported, then this field must be set to the\r | |
157 | /// Identifier field of the IORT ITS Group node.\r | |
158 | UINT8 ItsGroupRefId;\r | |
159 | \r | |
160 | /// Reserved - must be zero.\r | |
161 | UINT8 Reserved1[3];\r | |
162 | } EFI_ACPI_AEST_INTERRUPT_STRUCT;\r | |
163 | \r | |
164 | // AEST Interrupt node - interrupt type defintions.\r | |
165 | #define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0\r | |
166 | #define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1\r | |
167 | \r | |
168 | // AEST Interrupt node - interrupt flag defintions.\r | |
169 | #define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0\r | |
170 | #define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0\r | |
171 | \r | |
172 | ///\r | |
173 | /// Cache Processor Resource structure.\r | |
174 | ///\r | |
175 | typedef struct {\r | |
176 | /// Reference to the cache structure in the PPTT table.\r | |
177 | UINT32 CacheRefId;\r | |
178 | \r | |
179 | /// Reserved\r | |
180 | UINT32 Reserved;\r | |
181 | } EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT;\r | |
182 | \r | |
183 | ///\r | |
184 | /// TLB Processor Resource structure.\r | |
185 | ///\r | |
186 | typedef struct {\r | |
187 | /// TLB level from perspective of current processor.\r | |
188 | UINT32 TlbRefId;\r | |
189 | \r | |
190 | /// Reserved\r | |
191 | UINT32 Reserved;\r | |
192 | } EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT;\r | |
193 | \r | |
194 | ///\r | |
195 | /// Processor Generic Resource structure.\r | |
196 | ///\r | |
197 | typedef struct {\r | |
198 | /// Vendor-defined supplementary data.\r | |
199 | UINT32 Data;\r | |
200 | } EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT;\r | |
201 | \r | |
202 | ///\r | |
203 | /// AEST Processor Resource union.\r | |
204 | ///\r | |
205 | typedef union {\r | |
206 | /// Processor Cache resource.\r | |
207 | EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache;\r | |
208 | \r | |
209 | /// Processor TLB resource.\r | |
210 | EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb;\r | |
211 | \r | |
212 | /// Processor Generic resource.\r | |
213 | EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic;\r | |
214 | } EFI_ACPI_AEST_PROCESSOR_RESOURCE;\r | |
215 | \r | |
216 | ///\r | |
217 | /// AEST Processor structure.\r | |
218 | ///\r | |
219 | typedef struct {\r | |
220 | /// AEST Node header\r | |
221 | EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r | |
222 | \r | |
223 | /// Processor ID of node.\r | |
224 | UINT32 AcpiProcessorId;\r | |
225 | \r | |
226 | /// Resource type of the processor node.\r | |
227 | /// 0x0 - Cache\r | |
228 | /// 0x1 - TLB\r | |
229 | /// 0x2 - Generic\r | |
230 | UINT8 ResourceType;\r | |
231 | \r | |
232 | /// Reserved - must be zero.\r | |
233 | UINT8 Reserved;\r | |
234 | \r | |
235 | /// Processor structure flags.\r | |
236 | UINT8 Flags;\r | |
237 | \r | |
238 | /// Processor structure revision.\r | |
239 | UINT8 Revision;\r | |
240 | \r | |
241 | /// Processor affinity descriptor for the resource that this\r | |
242 | /// error node pertains to.\r | |
243 | UINT64 ProcessorAffinityLevelIndicator;\r | |
244 | \r | |
245 | /// Processor resource\r | |
246 | EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource;\r | |
247 | \r | |
248 | // Node Interface\r | |
249 | // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r | |
250 | \r | |
251 | // Node Interrupt Array\r | |
252 | // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];\r | |
253 | } EFI_ACPI_AEST_PROCESSOR_STRUCT;\r | |
254 | \r | |
255 | // AEST Processor resource type definitions.\r | |
256 | #define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0\r | |
257 | #define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1\r | |
258 | #define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2\r | |
259 | \r | |
260 | // AEST Processor flag definitions.\r | |
261 | #define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0\r | |
262 | #define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1\r | |
263 | \r | |
264 | ///\r | |
265 | /// Memory Controller structure.\r | |
266 | ///\r | |
267 | typedef struct {\r | |
268 | /// AEST Node header\r | |
269 | EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r | |
270 | \r | |
271 | /// SRAT proximity domain.\r | |
272 | UINT32 ProximityDomain;\r | |
273 | \r | |
274 | // Node Interface\r | |
275 | // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r | |
276 | \r | |
277 | // Node Interrupt Array\r | |
278 | // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];\r | |
279 | } EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT;\r | |
280 | \r | |
281 | ///\r | |
282 | /// SMMU structure.\r | |
283 | ///\r | |
284 | typedef struct {\r | |
285 | /// AEST Node header\r | |
286 | EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r | |
287 | \r | |
288 | /// Reference to the IORT table node that describes this SMMU.\r | |
289 | UINT32 SmmuRefId;\r | |
290 | \r | |
291 | /// Reference to the IORT table node that is associated with the\r | |
292 | /// sub-component within this SMMU.\r | |
293 | UINT32 SubComponentRefId;\r | |
294 | \r | |
295 | // Node Interface\r | |
296 | // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r | |
297 | \r | |
298 | // Node Interrupt Array\r | |
299 | // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];\r | |
300 | } EFI_ACPI_AEST_SMMU_STRUCT;\r | |
301 | \r | |
302 | ///\r | |
303 | /// Vendor-Defined structure.\r | |
304 | ///\r | |
305 | typedef struct {\r | |
306 | /// AEST Node header\r | |
307 | EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r | |
308 | \r | |
309 | /// ACPI HID of the component.\r | |
310 | UINT32 HardwareId;\r | |
311 | \r | |
312 | /// The ACPI Unique identifier of the component.\r | |
313 | UINT32 UniqueId;\r | |
314 | \r | |
315 | /// Vendor-specific data, for example to identify this error source.\r | |
316 | UINT8 VendorData[16];\r | |
317 | \r | |
318 | // Node Interface\r | |
319 | // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r | |
320 | \r | |
321 | // Node Interrupt Array\r | |
322 | // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];\r | |
323 | } EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT;\r | |
324 | \r | |
325 | ///\r | |
326 | /// GIC structure.\r | |
327 | ///\r | |
328 | typedef struct {\r | |
329 | /// AEST Node header\r | |
330 | EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r | |
331 | \r | |
332 | /// Type of GIC interface that is associated with this error node.\r | |
333 | /// 0x0 - GIC CPU (GICC)\r | |
334 | /// 0x1 - GIC Distributor (GICD)\r | |
335 | /// 0x2 - GIC Resistributor (GICR)\r | |
336 | /// 0x3 - GIC ITS (GITS)\r | |
337 | UINT32 InterfaceType;\r | |
338 | \r | |
339 | /// Identifier for the interface instance.\r | |
340 | UINT32 GicInterfaceRefId;\r | |
341 | \r | |
342 | // Node Interface\r | |
343 | // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r | |
344 | \r | |
345 | // Node Interrupt Array\r | |
346 | // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n];\r | |
347 | } EFI_ACPI_AEST_GIC_STRUCT;\r | |
348 | \r | |
349 | // AEST GIC interface type definitions.\r | |
350 | #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0\r | |
351 | #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1\r | |
352 | #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2\r | |
353 | #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3\r | |
354 | \r | |
355 | #pragma pack()\r | |
356 | \r | |
357 | #endif // ARM_ERROR_SOURCE_TABLE_H_\r |