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1 | /** @file\r |
2 | Header file for eMMC support.\r | |
3 | \r | |
4 | This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.\r | |
5 | \r | |
6 | Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #ifndef __EMMC_H__\r | |
18 | #define __EMMC_H__\r | |
19 | \r | |
20 | //\r | |
21 | // EMMC command index\r | |
22 | //\r | |
23 | #define EMMC_GO_IDLE_STATE 0\r | |
24 | #define EMMC_SEND_OP_COND 1\r | |
25 | #define EMMC_ALL_SEND_CID 2\r | |
26 | #define EMMC_SET_RELATIVE_ADDR 3\r | |
27 | #define EMMC_SET_DSR 4\r | |
28 | #define EMMC_SLEEP_AWAKE 5\r | |
29 | #define EMMC_SWITCH 6\r | |
30 | #define EMMC_SELECT_DESELECT_CARD 7\r | |
31 | #define EMMC_SEND_EXT_CSD 8\r | |
32 | #define EMMC_SEND_CSD 9\r | |
33 | #define EMMC_SEND_CID 10\r | |
34 | #define EMMC_STOP_TRANSMISSION 12\r | |
35 | #define EMMC_SEND_STATUS 13\r | |
36 | #define EMMC_BUSTEST_R 14\r | |
37 | #define EMMC_GO_INACTIVE_STATE 15\r | |
38 | #define EMMC_SET_BLOCKLEN 16\r | |
39 | #define EMMC_READ_SINGLE_BLOCK 17\r | |
40 | #define EMMC_READ_MULTIPLE_BLOCK 18\r | |
41 | #define EMMC_BUSTEST_W 19\r | |
42 | #define EMMC_SEND_TUNING_BLOCK 21\r | |
43 | #define EMMC_SET_BLOCK_COUNT 23\r | |
44 | #define EMMC_WRITE_BLOCK 24\r | |
45 | #define EMMC_WRITE_MULTIPLE_BLOCK 25\r | |
46 | #define EMMC_PROGRAM_CID 26\r | |
47 | #define EMMC_PROGRAM_CSD 27\r | |
48 | #define EMMC_SET_WRITE_PROT 28\r | |
49 | #define EMMC_CLR_WRITE_PROT 29\r | |
50 | #define EMMC_SEND_WRITE_PROT 30\r | |
51 | #define EMMC_SEND_WRITE_PROT_TYPE 31\r | |
52 | #define EMMC_ERASE_GROUP_START 35\r | |
53 | #define EMMC_ERASE_GROUP_END 36\r | |
54 | #define EMMC_ERASE 38\r | |
55 | #define EMMC_FAST_IO 39\r | |
56 | #define EMMC_GO_IRQ_STATE 40\r | |
57 | #define EMMC_LOCK_UNLOCK 42\r | |
58 | #define EMMC_SET_TIME 49\r | |
59 | #define EMMC_PROTOCOL_RD 53\r | |
60 | #define EMMC_PROTOCOL_WR 54\r | |
61 | #define EMMC_APP_CMD 55\r | |
62 | #define EMMC_GEN_CMD 56\r | |
63 | \r | |
64 | typedef enum {\r | |
65 | EmmcPartitionUserData = 0,\r | |
66 | EmmcPartitionBoot1 = 1,\r | |
67 | EmmcPartitionBoot2 = 2,\r | |
68 | EmmcPartitionRPMB = 3,\r | |
69 | EmmcPartitionGP1 = 4,\r | |
70 | EmmcPartitionGP2 = 5,\r | |
71 | EmmcPartitionGP3 = 6,\r | |
72 | EmmcPartitionGP4 = 7,\r | |
73 | EmmcPartitionUnknown\r | |
74 | } EMMC_PARTITION_TYPE;\r | |
75 | \r | |
76 | #pragma pack(1)\r | |
77 | typedef struct {\r | |
78 | UINT8 NotUsed:1; // Not used [0:0]\r | |
79 | UINT8 Crc:7; // CRC [7:1]\r | |
80 | UINT8 ManufacturingDate; // Manufacturing date [15:8]\r | |
81 | UINT8 ProductSerialNumber[4]; // Product serial number [47:16]\r | |
82 | UINT8 ProductRevision; // Product revision [55:48]\r | |
83 | UINT8 ProductName[6]; // Product name [103:56]\r | |
84 | UINT8 OemId; // OEM/Application ID [111:104]\r | |
85 | UINT8 DeviceType:2; // Device/BGA [113:112]\r | |
86 | UINT8 Reserved:6; // Reserved [119:114]\r | |
87 | UINT8 ManufacturerId; // Manufacturer ID [127:120]\r | |
88 | } EMMC_CID;\r | |
89 | \r | |
90 | typedef struct {\r | |
91 | UINT32 NotUsed:1; // Not used [0:0]\r | |
92 | UINT32 Crc:7; // CRC [7:1]\r | |
93 | UINT32 Ecc:2; // ECC code [9:8]\r | |
94 | UINT32 FileFormat:2; // File format [11:10]\r | |
95 | UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r | |
96 | UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r | |
97 | UINT32 Copy:1; // Copy flag (OTP) [14:14]\r | |
98 | UINT32 FileFormatGrp:1; // File format group [15:15]\r | |
99 | UINT32 ContentProtApp:1; // Content protection application [16:16]\r | |
100 | UINT32 Reserved:4; // Reserved [20:17]\r | |
101 | UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r | |
102 | UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r | |
103 | UINT32 R2WFactor:3; // Write speed factor [28:26]\r | |
104 | UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]\r | |
105 | UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r | |
106 | \r | |
107 | UINT32 WpGrpSize:5; // Write protect group size [36:32]\r | |
108 | UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]\r | |
109 | UINT32 EraseGrpSize:5; // Erase group size [46:42]\r | |
110 | UINT32 CSizeMult:3; // Device size multiplier [49:47]\r | |
111 | UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]\r | |
112 | UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]\r | |
113 | UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]\r | |
114 | UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]\r | |
115 | UINT32 CSizeLow:2; // Device size low two bits [63:62]\r | |
116 | \r | |
117 | UINT32 CSizeHigh:10; // Device size high eight bits [73:64]\r | |
118 | UINT32 Reserved1:2; // Reserved [75:74]\r | |
119 | UINT32 DsrImp:1; // DSR implemented [76:76]\r | |
120 | UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r | |
121 | UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r | |
122 | UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r | |
123 | UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r | |
124 | UINT32 Ccc:12; // Device command classes [95:84]\r | |
125 | \r | |
126 | UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]\r | |
127 | UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r | |
128 | UINT32 Taac:8; // Data read access-time 1 [119:112]\r | |
129 | UINT32 Reserved2:2; // Reserved [121:120]\r | |
130 | UINT32 SpecVers:4; // System specification version [125:122]\r | |
131 | UINT32 CsdStructure:2; // CSD structure [127:126]\r | |
132 | } EMMC_CSD;\r | |
133 | \r | |
134 | typedef struct {\r | |
135 | //\r | |
136 | // Modes Segment\r | |
137 | //\r | |
138 | UINT8 Reserved[16]; // Reserved [15:0]\r | |
139 | UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]\r | |
140 | UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]\r | |
141 | UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]\r | |
142 | UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]\r | |
143 | UINT8 FfuStatus; // FFU status R [26]\r | |
144 | UINT8 Reserved1[2]; // Reserved [28:27]\r | |
145 | UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]\r | |
146 | UINT8 ModeConfig; // Mode config R/W/EP [30]\r | |
147 | UINT8 Reserved2; // Reserved [31]\r | |
148 | UINT8 FlushCache; // Flushing of the cache W/EP [32]\r | |
149 | UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]\r | |
150 | UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]\r | |
151 | UINT8 PackedFailureIndex; // Packed command failure index R [35]\r | |
152 | UINT8 PackedCommandStatus; // Packed command status R [36]\r | |
153 | UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]\r | |
154 | UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]\r | |
155 | UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]\r | |
156 | UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]\r | |
157 | UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]\r | |
158 | UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]\r | |
159 | UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]\r | |
160 | UINT8 DataSectorSize; // Sector size R [61]\r | |
161 | UINT8 UseNativeSector; // Sector size emulation R/W [62]\r | |
162 | UINT8 NativeSectorSize; // Native sector size R [63]\r | |
163 | UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]\r | |
164 | UINT8 Reserved3[2]; // Reserved [129:128]\r | |
165 | UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]\r | |
166 | UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]\r | |
167 | UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]\r | |
168 | UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]\r | |
169 | UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]\r | |
170 | UINT8 Reserved4; // Reserved [135]\r | |
171 | UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]\r | |
172 | UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]\r | |
173 | UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]\r | |
174 | UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]\r | |
175 | UINT8 PartitionsAttribute; // Partitions attribute R/W [156]\r | |
176 | UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]\r | |
177 | UINT8 PartitioningSupport; // Partitioning Support R [160]\r | |
178 | UINT8 HpiMgmt; // HPI management R/W/EP [161]\r | |
179 | UINT8 RstFunction; // H/W reset function R/W [162]\r | |
180 | UINT8 BkopsEn; // Enable background operations handshake R/W [163]\r | |
181 | UINT8 BkopsStart; // Manually start background operations W/EP [164]\r | |
182 | UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]\r | |
183 | UINT8 WrRelParam; // Write reliability parameter register R [166]\r | |
184 | UINT8 WrRelSet; // Write reliability setting register R/W [167]\r | |
185 | UINT8 RpmbSizeMult; // RPMB Size R [168]\r | |
186 | UINT8 FwConfig; // FW configuration R/W [169]\r | |
187 | UINT8 Reserved5; // Reserved [170]\r | |
188 | UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]\r | |
189 | UINT8 Reserved6; // Reserved [172]\r | |
190 | UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]\r | |
191 | UINT8 BootWpStatus; // Boot write protection status registers R [174]\r | |
192 | UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]\r | |
193 | UINT8 Reserved7; // Reserved [176]\r | |
194 | UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]\r | |
195 | UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]\r | |
196 | UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]\r | |
197 | UINT8 Reserved8; // Reserved [180]\r | |
198 | UINT8 ErasedMemCont; // Erased memory content R [181]\r | |
199 | UINT8 Reserved9; // Reserved [182]\r | |
200 | UINT8 BusWidth; // Bus width mode W/EP [183]\r | |
201 | UINT8 Reserved10; // Reserved [184]\r | |
202 | UINT8 HsTiming; // High-speed interface timing R/W/EP [185]\r | |
203 | UINT8 Reserved11; // Reserved [186]\r | |
204 | UINT8 PowerClass; // Power class R/W/EP [187]\r | |
205 | UINT8 Reserved12; // Reserved [188]\r | |
206 | UINT8 CmdSetRev; // Command set revision R [189]\r | |
207 | UINT8 Reserved13; // Reserved [190]\r | |
208 | UINT8 CmdSet; // Command set R/W/EP [191]\r | |
209 | //\r | |
210 | // Properties Segment\r | |
211 | //\r | |
212 | UINT8 ExtCsdRev; // Extended CSD revision [192]\r | |
213 | UINT8 Reserved14; // Reserved [193]\r | |
214 | UINT8 CsdStructure; // CSD STRUCTURE [194]\r | |
215 | UINT8 Reserved15; // Reserved [195]\r | |
216 | UINT8 DeviceType; // Device type [196]\r | |
217 | UINT8 DriverStrength; // I/O Driver Strength [197]\r | |
218 | UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]\r | |
219 | UINT8 PartitionSwitchTime; // Partition switching timing [199]\r | |
220 | UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]\r | |
221 | UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]\r | |
222 | UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]\r | |
223 | UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]\r | |
224 | UINT8 Reserved16; // Reserved [204]\r | |
225 | UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]\r | |
226 | UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]\r | |
227 | UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]\r | |
228 | UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]\r | |
229 | UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]\r | |
230 | UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r | |
231 | UINT8 Reserved17; // Reserved [211]\r | |
232 | UINT8 SecCount[4]; // Sector Count [215:212]\r | |
233 | UINT8 SleepNotificationTime; // Sleep Notification Timout [216]\r | |
234 | UINT8 SATimeout; // Sleep/awake timeout [217]\r | |
235 | UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r | |
236 | UINT8 SCVccq; // Sleep current (VCCQ) [219]\r | |
237 | UINT8 SCVcc; // Sleep current (VCC) [220]\r | |
238 | UINT8 HcWpGrpSize; // High-capacity write protect group size [221]\r | |
239 | UINT8 RelWrSecC; // Reliable write sector count [222]\r | |
240 | UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]\r | |
241 | UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]\r | |
242 | UINT8 AccSize; // Access size [225]\r | |
243 | UINT8 BootSizeMult; // Boot partition size [226]\r | |
244 | UINT8 Reserved18; // Reserved [227]\r | |
245 | UINT8 BootInfo; // Boot information [228]\r | |
246 | UINT8 SecTrimMult; // Secure TRIM Multiplier [229]\r | |
247 | UINT8 SecEraseMult; // Secure Erase Multiplier [230]\r | |
248 | UINT8 SecFeatureSupport; // Secure Feature support [231]\r | |
249 | UINT8 TrimMult; // TRIM Multiplier [232]\r | |
250 | UINT8 Reserved19; // Reserved [233]\r | |
251 | UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]\r | |
252 | UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]\r | |
253 | UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]\r | |
254 | UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]\r | |
255 | UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]\r | |
256 | UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]\r | |
257 | UINT8 Reserved20; // Reserved [240]\r | |
258 | UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]\r | |
259 | UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]\r | |
260 | UINT8 BkopsStatus; // Background operations status [246]\r | |
261 | UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]\r | |
262 | UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]\r | |
263 | UINT8 CacheSize[4]; // Cache size [252:249]\r | |
264 | UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]\r | |
265 | UINT8 FirmwareVersion[8]; // Firmware version [261:254]\r | |
266 | UINT8 DeviceVersion[2]; // Device version [263:262]\r | |
267 | UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]\r | |
268 | UINT8 OptimalWriteSize; // Optimal write size [265]\r | |
269 | UINT8 OptimalReadSize; // Optimal read size [266]\r | |
270 | UINT8 PreEolInfo; // Pre EOL information [267]\r | |
271 | UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]\r | |
272 | UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]\r | |
273 | UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]\r | |
274 | UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]\r | |
275 | UINT8 Reserved21[181]; // Reserved [486:306]\r | |
276 | UINT8 FfuArg[4]; // FFU Argument [490:487]\r | |
277 | UINT8 OperationCodeTimeout; // Operation codes timeout [491]\r | |
278 | UINT8 FfuFeatures; // FFU features [492]\r | |
279 | UINT8 SupportedModes; // Supported modes [493]\r | |
280 | UINT8 ExtSupport; // Extended partitions attribute support [494]\r | |
281 | UINT8 LargeUnitSizeM1; // Large Unit size [495]\r | |
282 | UINT8 ContextCapabilities; // Context management capabilities [496]\r | |
283 | UINT8 TagResSize; // Tag Resources Size [497]\r | |
284 | UINT8 TagUnitSize; // Tag Unit Size [498]\r | |
285 | UINT8 DataTagSupport; // Data Tag Support [499]\r | |
286 | UINT8 MaxPackedWrites; // Max packed write commands [500]\r | |
287 | UINT8 MaxPackedReads; // Max packed read commands[501]\r | |
288 | UINT8 BkOpsSupport; // Background operations support [502]\r | |
289 | UINT8 HpiFeatures; // HPI features [503]\r | |
290 | UINT8 SupportedCmdSet; // Supported Command Sets [504]\r | |
291 | UINT8 ExtSecurityErr; // Extended Security Commands Error [505]\r | |
292 | UINT8 Reserved22[6]; // Reserved [511:506]\r | |
293 | } EMMC_EXT_CSD;\r | |
294 | \r | |
295 | #pragma pack()\r | |
296 | \r | |
297 | #endif\r |