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42eedea9 | 1 | /** @file\r |
9095d37b | 2 | ACPI memory mapped configuration space access table definition, defined at\r |
000f6a28 | 3 | in the PCI Firmware Specification, version 3.0.\r |
568eb0cb | 4 | Specification is available at http://www.pcisig.com.\r |
9095d37b LG |
5 | \r |
6 | Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
568eb0cb | 8 | **/\r |
9 | \r | |
10 | #ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_\r | |
11 | #define _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_\r | |
12 | \r | |
766f4bc1 | 13 | //\r |
14 | // Ensure proper structure formats\r | |
15 | //\r | |
16 | #pragma pack(1)\r | |
17 | \r | |
1bc5d021 | 18 | ///\r |
19 | /// Memory Mapped Configuration Space Access Table (MCFG)\r | |
20 | /// This table is a basic description table header followed by\r | |
21 | /// a number of base address allocation structures.\r | |
22 | ///\r | |
568eb0cb | 23 | typedef struct {\r |
24 | UINT64 BaseAddress;\r | |
25 | UINT16 PciSegmentGroupNumber;\r | |
26 | UINT8 StartBusNumber;\r | |
27 | UINT8 EndBusNumber;\r | |
28 | UINT32 Reserved;\r | |
29 | } EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;\r | |
1bc5d021 | 30 | \r |
31 | ///\r | |
9095d37b | 32 | /// MCFG Table header definition. The rest of the table\r |
1bc5d021 | 33 | /// must be defined in a platform specific manner.\r |
34 | ///\r | |
3431f363 | 35 | typedef struct {\r |
36 | EFI_ACPI_DESCRIPTION_HEADER Header;\r | |
37 | UINT64 Reserved;\r | |
38 | } EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;\r | |
1bc5d021 | 39 | \r |
40 | ///\r | |
41 | /// MCFG Revision (defined in spec)\r | |
42 | ///\r | |
568eb0cb | 43 | #define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION 0x01\r |
44 | \r | |
766f4bc1 | 45 | #pragma pack()\r |
46 | \r | |
568eb0cb | 47 | #endif\r |