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a7b64584 1/** @file\r
5d51e463 2 Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.\r
a7b64584 3\r
4 Copyright (c) 2006 - 2008, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
13**/\r
14\r
15#ifndef __PAL_API_H__\r
16#define __PAL_API_H__\r
17\r
18#define PAL_SUCCESS 0x0\r
19\r
20//\r
21// CacheType of PAL_CACHE_FLUSH.\r
22//\r
23#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
24#define PAL_CACHE_FLUSH_DATA_ALL 2\r
25#define PAL_CACHE_FLUSH_ALL 3\r
26#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
27\r
28\r
29//\r
30// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
31//\r
32#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r
33#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r
34#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r
35#define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r
36\r
37/**\r
38 PAL Procedure - PAL_CACHE_FLUSH.\r
39\r
40 Flush the instruction or data caches. It is required by IPF.\r
41 The PAL procedure supports the Static Registers calling\r
42 convention. It could be called at virtual mode and physical\r
43 mode.\r
44\r
45 @param Index Index of PAL_CACHE_FLUSH within the\r
46 list of PAL procedures.\r
47 @param CacheType Unsigned 64-bit integer indicating\r
48 which cache to flush.\r
49 @param Operation Formatted bit vector indicating the\r
50 operation of this call.\r
51 @param ProgressIndicator Unsigned 64-bit integer specifying\r
52 the starting position of the flush\r
53 operation.\r
54\r
55 @retval 2 Call completed without error, but a PMI\r
56 was taken during the execution of this\r
57 procedure.\r
58 @retval 1 Call has not completed flushing due to\r
59 a pending interrupt.\r
60 @retval 0 Call completed without error\r
61 @retval -2 Invalid argument\r
62 @retval -3 Call completed with error\r
63\r
64 @return R9 Unsigned 64-bit integer specifying the vector\r
65 number of the pending interrupt.\r
66 @return R10 Unsigned 64-bit integer specifying the\r
67 starting position of the flush operation.\r
68 @return R11 Unsigned 64-bit integer specifying the vector\r
69 number of the pending interrupt.\r
70\r
71**/\r
72#define PAL_CACHE_FLUSH 1\r
73\r
74\r
75//\r
76// Attributes of PAL_CACHE_CONFIG_INFO1\r
77//\r
78#define PAL_CACHE_ATTR_WT 0\r
79#define PAL_CACHE_ATTR_WB 1\r
80\r
81//\r
82// PAL_CACHE_CONFIG_INFO1.StoreHint\r
83//\r
84#define PAL_CACHE_STORE_TEMPORAL 0\r
85#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
86\r
87//\r
88// PAL_CACHE_CONFIG_INFO1.StoreHint\r
89//\r
90#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
91#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
92\r
93//\r
94// PAL_CACHE_CONFIG_INFO1.StoreHint\r
95//\r
96#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
97#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
98#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
99\r
100//\r
101// Detail the characteristics of a given processor controlled\r
102// cache in the cache hierarchy.\r
103//\r
104typedef struct {\r
105 UINT64 IsUnified : 1;\r
106 UINT64 Attributes : 2;\r
107 UINT64 Associativity:8;\r
108 UINT64 LineSize:8;\r
109 UINT64 Stride:8;\r
110 UINT64 StoreLatency:8;\r
111 UINT64 StoreHint:8;\r
112 UINT64 LoadHint:8;\r
113} PAL_CACHE_INFO_RETURN1;\r
114\r
115//\r
116// Detail the characteristics of a given processor controlled\r
117// cache in the cache hierarchy.\r
118//\r
119typedef struct {\r
120 UINT64 CacheSize:32;\r
121 UINT64 AliasBoundary:8;\r
122 UINT64 TagLsBits:8;\r
123 UINT64 TagMsBits:8;\r
124} PAL_CACHE_INFO_RETURN2;\r
125\r
126/**\r
127 PAL Procedure - PAL_CACHE_INFO.\r
128\r
129 Return detailed instruction or data cache information. It is\r
130 required by IPF. The PAL procedure supports the Static\r
131 Registers calling convention. It could be called at virtual\r
132 mode and physical mode.\r
133\r
134 @param Index Index of PAL_CACHE_INFO within the list of\r
135 PAL procedures.\r
136 @param CacheLevel Unsigned 64-bit integer specifying the\r
137 level in the cache hierarchy for which\r
138 information is requested. This value must\r
139 be between 0 and one less than the value\r
140 returned in the cache_levels return value\r
141 from PAL_CACHE_SUMMARY.\r
142 @param CacheType Unsigned 64-bit integer with a value of 1\r
143 for instruction cache and 2 for data or\r
144 unified cache. All other values are\r
145 reserved.\r
146 @param Reserved Should be 0.\r
147\r
148 @retval 0 Call completed without error\r
149 @retval -2 Invalid argument\r
150 @retval -3 Call completed with error\r
151\r
152 @return R9 Detail the characteristics of a given\r
153 processor controlled cache in the cache\r
154 hierarchy. See PAL_CACHE_INFO_RETURN1.\r
155 @return R10 Detail the characteristics of a given\r
156 processor controlled cache in the cache\r
157 hierarchy. See PAL_CACHE_INFO_RETURN2.\r
158 @return R11 Reserved with 0.\r
159\r
160**/\r
161#define PAL_CACHE_INFO 2\r
162\r
163\r
164\r
165//\r
166// Level of PAL_CACHE_INIT.\r
167//\r
168#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
169\r
170//\r
171// CacheType\r
172//\r
173#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r
174#define PAL_CACHE_INIT_TYPE_DATA 0x2\r
175#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r
176\r
177//\r
178// Restrict of PAL_CACHE_INIT.\r
179//\r
180#define PAL_CACHE_INIT_NO_RESTRICT 0\r
181#define PAL_CACHE_INIT_RESTRICTED 1\r
182\r
183/**\r
184 PAL Procedure - PAL_CACHE_INIT.\r
185\r
186 Initialize the instruction or data caches. It is required by\r
187 IPF. The PAL procedure supports the Static Registers calling\r
188 convention. It could be called at physical mode.\r
189\r
190 @param Index Index of PAL_CACHE_INIT within the list of PAL\r
191 procedures.\r
192 @param Level Unsigned 64-bit integer containing the level of\r
193 cache to initialize. If the cache level can be\r
194 initialized independently, only that level will\r
195 be initialized. Otherwise\r
196 implementation-dependent side-effects will\r
197 occur.\r
198 @param CacheType Unsigned 64-bit integer with a value of 1 to\r
199 initialize the instruction cache, 2 to\r
200 initialize the data cache, or 3 to\r
201 initialize both. All other values are\r
202 reserved.\r
203 @param Restrict Unsigned 64-bit integer with a value of 0 or\r
204 1. All other values are reserved. If\r
205 restrict is 1 and initializing the specified\r
206 level and cache_type of the cache would\r
207 cause side-effects, PAL_CACHE_INIT will\r
208 return -4 instead of initializing the cache.\r
209\r
210 @retval 0 Call completed without error\r
211 @retval -2 Invalid argument\r
212 @retval -3 Call completed with error.\r
213 @retval -4 Call could not initialize the specified\r
214 level and cache_type of the cache without\r
215 side-effects and restrict was 1.\r
216\r
217**/\r
218#define PAL_CACHE_INIT 3\r
219\r
220\r
221//\r
222// PAL_CACHE_PROTECTION.Method.\r
223//\r
224#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
225#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
226#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
227#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
228\r
229\r
230\r
231//\r
232// PAL_CACHE_PROTECTION.TagOrData.\r
233//\r
234#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
235#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
236#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
237#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
238\r
239//\r
240// 32-bit protection information structures.\r
241//\r
242typedef struct {\r
243 UINT32 DataBits:8;\r
244 UINT32 TagProtLsb:6;\r
245 UINT32 TagProtMsb:6;\r
246 UINT32 ProtBits:6;\r
247 UINT32 Method:4;\r
248 UINT32 TagOrData:2;\r
249} PAL_CACHE_PROTECTION;\r
250\r
251/**\r
252 PAL Procedure - PAL_CACHE_PROT_INFO.\r
253\r
254 Return instruction or data cache protection information. It is\r
255 required by IPF. The PAL procedure supports the Static\r
256 Registers calling convention. It could be called at physical\r
257 mode and Virtual mode.\r
258\r
259 @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
260 PAL procedures.\r
261 @param CacheLevel Unsigned 64-bit integer specifying the level\r
262 in the cache hierarchy for which information\r
263 is requested. This value must be between 0\r
264 and one less than the value returned in the\r
265 cache_levels return value from\r
266 PAL_CACHE_SUMMARY.\r
267 @param CacheType Unsigned 64-bit integer with a value of 1\r
268 for instruction cache and 2 for data or\r
269 unified cache. All other values are\r
270 reserved.\r
271\r
272 @retval 0 Call completed without error\r
273 @retval -2 Invalid argument\r
274 @retval -3 Call completed with error.\r
275\r
276 @return R9 Detail the characteristics of a given\r
277 processor controlled cache in the cache\r
278 hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
279 @return R10 Detail the characteristics of a given\r
280 processor controlled cache in the cache\r
281 hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
282 @return R11 Detail the characteristics of a given\r
283 processor controlled cache in the cache\r
284 hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
285\r
286**/\r
287#define PAL_CACHE_PROT_INFO 38\r
288\r
289/**\r
290\r
291 @param ThreadId The thread identifier of the logical\r
292 processor for which information is being\r
293 returned. This value will be unique on a per\r
294 core basis.\r
295\r
296 @param CoreId The core identifier of the logical processor\r
297 for which information is being returned.\r
298 This value will be unique on a per physical\r
299 processor package basis.\r
300\r
301**/\r
302typedef struct {\r
303 UINT64 ThreadId : 16;\r
304 UINT64 Reserved1: 16;\r
305 UINT64 CoreId: 16;\r
306 UINT64 Reserved2: 16;\r
307} PAL_PCOC_N_CACHE_INFO1;\r
308\r
309/**\r
310\r
311 @param LogicalAddress Logical address: geographical address\r
312 of the logical processor for which\r
313 information is being returned. This is\r
314 the same value that is returned by the\r
315 PAL_FIXED_ADDR procedure when it is\r
316 called on the logical processor.\r
317\r
318**/\r
319typedef struct {\r
320 UINT64 LogicalAddress : 16;\r
321 UINT64 Reserved1: 16;\r
322 UINT64 Reserved2: 32;\r
323} PAL_PCOC_N_CACHE_INFO2;\r
324\r
325/**\r
326 PAL Procedure - PAL_CACHE_SHARED_INFO.\r
327\r
328 Returns information on which logical processors share caches.\r
329 It is optional. The PAL procedure supports the Static\r
330 Registers calling convention. It could be called at physical\r
331 mode and Virtual mode.\r
332\r
333 @param Index Index of PAL_CACHE_SHARED_INFO within the list\r
334 of PAL procedures.\r
335 @param CacheLevel Unsigned 64-bit integer specifying the\r
336 level in the cache hierarchy for which\r
337 information is requested. This value must\r
338 be between 0 and one less than the value\r
339 returned in the cache_levels return value\r
340 from PAL_CACHE_SUMMARY.\r
341 @param CacheType Unsigned 64-bit integer with a value of 1\r
342 for instruction cache and 2 for data or\r
343 unified cache. All other values are\r
344 reserved.\r
345 @param ProcNumber Unsigned 64-bit integer that specifies for\r
346 which logical processor information is\r
347 being requested. This input argument must\r
348 be zero for the first call to this\r
349 procedure and can be a maximum value of\r
350 one less than the number of logical\r
351 processors sharing this cache, which is\r
352 returned by the num_shared return value.\r
353\r
354 @retval 0 Call completed without error\r
355 @retval -1 Unimplemented procedure\r
356 @retval -2 Invalid argument\r
357 @retval -3 Call completed with error.\r
358\r
359 @return R9 Unsigned integer that returns the number of\r
360 logical processors that share the processor\r
361 cache level and type, for which information was\r
362 requested.\r
363 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r
364 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r
365\r
366**/\r
367#define PAL_CACHE_SHARED_INFO 43\r
368\r
369\r
370/**\r
371 PAL Procedure - PAL_CACHE_SUMMARY.\r
372\r
373 Return a summary of the cache hierarchy. It is required by\r
374 IPF. The PAL procedure supports the Static Registers calling\r
375 convention. It could be called at physical mode and Virtual\r
376 mode.\r
377\r
378 @param Index Index of PAL_CACHE_SUMMARY within the list of\r
379 PAL procedures.\r
380\r
381 @retval 0 Call completed without error\r
382 @retval -2 Invalid argument\r
383 @retval -3 Call completed with error.\r
384\r
385 @return R9 CacheLevels Unsigned 64-bit integer denoting the\r
386 number of levels of cache\r
387 implemented by the processor.\r
388 Strictly, this is the number of\r
389 levels for which the cache\r
390 controller is integrated into the\r
391 processor (the cache SRAMs may be\r
392 external to the processor).\r
393 @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r
394 number of unique caches implemented\r
395 by the processor. This has a maximum\r
396 of 2*cache_levels, but may be less\r
397 if any of the levels in the cache\r
398 hierarchy are unified caches or do\r
399 not have both instruction and data\r
400 caches.\r
401\r
402**/\r
403#define PAL_CACHE_SUMMARY 4\r
404\r
405\r
406//\r
407// Virtual Memory Attributes implemented by processor.\r
408//\r
409#define PAL_MEMORY_ATTR_WB 0\r
410#define PAL_MEMORY_ATTR_WC 6\r
411#define PAL_MEMORY_ATTR_UC 4\r
412#define PAL_MEMORY_ATTR_UCE 5\r
413#define PAL_MEMORY_ATTR_NATPAGE 7\r
414\r
415/**\r
416 PAL Procedure - PAL_MEM_ATTRIB.\r
417\r
418 Return a list of supported memory attributes.. It is required\r
419 by IPF. The PAL procedure supports the Static Registers calling\r
420 convention. It could be called at physical mode and Virtual\r
421 mode.\r
422\r
423 @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r
424 procedures.\r
425\r
426 @retval 0 Call completed without error\r
427 @retval -2 Invalid argument\r
428 @retval -3 Call completed with error.\r
429\r
430 @return R9 Attributes 8-bit vector of memory attributes\r
431 implemented by processor. See Virtual\r
432 Memory Attributes above.\r
433\r
434**/\r
435\r
436#define PAL_MEM_ATTRIB 5\r
437\r
438/**\r
439 PAL Procedure - PAL_PREFETCH_VISIBILITY.\r
440\r
441 Used in architected sequence to transition pages from a\r
442 cacheable, speculative attribute to an uncacheable attribute.\r
443 It is required by IPF. The PAL procedure supports the Static\r
444 Registers calling convention. It could be called at physical\r
445 mode and Virtual mode.\r
446\r
447 @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r
448 of PAL procedures.\r
449 @param TransitionType Unsigned integer specifying the type\r
450 of memory attribute transition that is\r
451 being performed.\r
452\r
453 @retval 1 Call completed without error; this\r
454 call is not necessary on remote\r
455 processors.\r
456 @retval 0 Call completed without error\r
457 @retval -2 Invalid argument\r
458 @retval -3 Call completed with error.\r
459\r
460**/\r
461#define PAL_PREFETCH_VISIBILITY 41\r
462\r
463/**\r
464 PAL Procedure - PAL_PTCE_INFO.\r
465\r
466 Return information needed for ptc.e instruction to purge\r
467 entire TC. It is required by IPF. The PAL procedure supports\r
468 the Static Registers calling convention. It could be called at\r
469 physical mode and Virtual mode.\r
470\r
471 @param Index Index of PAL_PTCE_INFO within the list\r
472 of PAL procedures.\r
473\r
474 @retval 0 Call completed without error\r
475 @retval -2 Invalid argument\r
476 @retval -3 Call completed with error.\r
477\r
478 @return R9 Unsigned 64-bit integer denoting the beginning\r
479 address to be used by the first PTCE instruction\r
480 in the purge loop.\r
481 @return R10 Two unsigned 32-bit integers denoting the loop\r
482 counts of the outer (loop 1) and inner (loop 2)\r
483 purge loops. count1 (loop 1) is contained in bits\r
484 63:32 of the parameter, and count2 (loop 2) is\r
485 contained in bits 31:0 of the parameter.\r
486 @return R11 Two unsigned 32-bit integers denoting the loop\r
487 strides of the outer (loop 1) and inner (loop 2)\r
488 purge loops. stride1 (loop 1) is contained in bits\r
489 63:32 of the parameter, and stride2 (loop 2) is\r
490 contained in bits 31:0 of the parameter.\r
491\r
492**/\r
493#define PAL_PTCE_INFO 6\r
494\r
495\r
496\r
497/**\r
498\r
499 @param NumberSets Unsigned 8-bit integer denoting the number\r
500 of hash sets for the specified level\r
501 (1=fully associative)\r
502\r
503 @param NumberWays Unsigned 8-bit integer denoting the\r
504 associativity of the specified level\r
505 (1=direct).\r
506\r
507 @param NumberEntries Unsigned 16-bit integer denoting the\r
508 number of entries in the specified TC.\r
509\r
510\r
511 @param PageSizeIsOptimized Flag denoting whether the\r
512 specified level is optimized for\r
513 the region's preferred page size\r
514 (1=optimized) tc_pages indicates\r
515 which page sizes are usable by\r
516 this translation cache.\r
517\r
518 @param TcIsUnified Flag denoting whether the specified TC is\r
519 unified (1=unified).\r
520\r
521 @param EntriesReduction Flag denoting whether installed\r
522 translation registers will reduce\r
523 the number of entries within the\r
524 specified TC.\r
525\r
526**/\r
527typedef struct {\r
528 UINT64 NumberSets:8;\r
529 UINT64 NumberWays:8;\r
530 UINT64 NumberEntries:16;\r
531 UINT64 PageSizeIsOptimized:1;\r
532 UINT64 TcIsUnified:1;\r
533 UINT64 EntriesReduction:1;\r
534} PAL_TC_INFO;\r
535\r
536/**\r
537 PAL Procedure - PAL_VM_INFO.\r
538\r
539 Return detailed information about virtual memory features\r
540 supported in the processor. It is required by IPF. The PAL\r
541 procedure supports the Static Registers calling convention. It\r
542 could be called at physical mode and Virtual mode.\r
543\r
544 @param Index Index of PAL_VM_INFO within the list\r
545 of PAL procedures.\r
546 @param TcLevel Unsigned 64-bit integer specifying the level\r
547 in the TLB hierarchy for which information is\r
548 required. This value must be between 0 and one\r
549 less than the value returned in the\r
550 vm_info_1.num_tc_levels return value from\r
551 PAL_VM_SUMMARY.\r
552 @param TcType Unsigned 64-bit integer with a value of 1 for\r
553 instruction translation cache and 2 for data\r
554 or unified translation cache. All other values\r
555 are reserved.\r
556\r
557 @retval 0 Call completed without error\r
558 @retval -2 Invalid argument\r
559 @retval -3 Call completed with error.\r
560\r
561 @return R9 8-byte formatted value returning information\r
562 about the specified TC. See PAL_TC_INFO above.\r
563 @return R10 64-bit vector containing a bit for each page\r
564 size supported in the specified TC, where bit\r
565 position n indicates a page size of 2**n.\r
566\r
567**/\r
568#define PAL_VM_INFO 7\r
569\r
570\r
571/**\r
572 PAL Procedure - PAL_VM_PAGE_SIZE.\r
573\r
574 Return virtual memory TC and hardware walker page sizes\r
575 supported in the processor. It is required by IPF. The PAL\r
576 procedure supports the Static Registers calling convention. It\r
577 could be called at physical mode and Virtual mode.\r
578\r
579 @param Index Index of PAL_VM_PAGE_SIZE within the list\r
580 of PAL procedures.\r
581\r
582 @retval 0 Call completed without error\r
583 @retval -2 Invalid argument\r
584 @retval -3 Call completed with error.\r
585\r
586 @return R9 64-bit vector containing a bit for each\r
587 architected page size that is supported for\r
588 TLB insertions and region registers.\r
589 @return R10 64-bit vector containing a bit for each\r
590 architected page size supported for TLB purge\r
591 operations.\r
592\r
593**/\r
594#define PAL_VM_PAGE_SIZE 34\r
595\r
596/**\r
597\r
598 @param WalkerPresent 1-bit flag indicating whether a hardware\r
599 TLB walker is implemented (1 = walker\r
600 present).\r
601\r
602 @param WidthOfPhysicalAddress Unsigned 7-bit integer\r
603 denoting the number of bits of\r
604 physical address implemented.\r
605\r
606 @param WidthOfKey Unsigned 8-bit integer denoting the number\r
607 of bits mplemented in the PKR.key field.\r
608\r
609 @param MaxPkrIndex Unsigned 8-bit integer denoting the\r
610 maximum PKR index (number of PKRs-1).\r
611\r
612 @param HashTagId Unsigned 8-bit integer which uniquely\r
613 identifies the processor hash and tag\r
614 algorithm.\r
615\r
616 @param MaxDtrIndex Unsigned 8 bit integer denoting the\r
617 maximum data translation register index\r
618 (number of dtr entries - 1).\r
619\r
620 @param MaxItrIndex Unsigned 8 bit integer denoting the\r
621 maximum instruction translation register\r
622 index (number of itr entries - 1).\r
623\r
624 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the\r
625 number of unique TCs implemented.\r
626 This is a maximum of\r
627 2*num_tc_levels.\r
628\r
629 @param NumberOfTcLevels Unsigned 8-bit integer denoting the\r
630 number of TC levels.\r
631\r
632**/\r
633typedef struct {\r
634 UINT64 WalkerPresent:1;\r
635 UINT64 WidthOfPhysicalAddress: 7;\r
636 UINT64 WidthOfKey:8;\r
637 UINT64 MaxPkrIndex:8;\r
638 UINT64 HashTagId:8;\r
639 UINT64 MaxDtrIndex:8;\r
640 UINT64 MaxItrIndex:8;\r
641 UINT64 NumberOfUniqueTc:8;\r
642 UINT64 NumberOfTcLevels:8;\r
643} PAL_VM_INFO1;\r
644\r
645/**\r
646\r
647 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r
648 is the total number of virtual\r
649 address bits - 1.\r
650\r
651 @param WidthOfRid Unsigned 8-bit integer denoting the number\r
652 of bits implemented in the RR.rid field.\r
653\r
654 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the\r
655 maximum number of concurrent outstanding\r
656 TLB purges allowed by the processor. A\r
657 value of 0 indicates one outstanding\r
658 purge allowed. A value of 216-1\r
659 indicates no limit on outstanding\r
660 purges. All other values indicate the\r
661 actual number of concurrent outstanding\r
662 purges allowed.\r
663\r
664**/\r
665typedef struct {\r
666 UINT64 WidthOfVirtualAddress:8;\r
667 UINT64 WidthOfRid:8;\r
668 UINT64 MaxPurgedTlbs:16;\r
669 UINT64 Reserved:32;\r
670} PAL_VM_INFO2;\r
671\r
672/**\r
673 PAL Procedure - PAL_VM_SUMMARY.\r
674\r
675 Return summary information about virtual memory features\r
676 supported in the processor. It is required by IPF. The PAL\r
677 procedure supports the Static Registers calling convention. It\r
678 could be called at physical mode and Virtual mode.\r
679\r
680 @param Index Index of PAL_VM_SUMMARY within the list\r
681 of PAL procedures.\r
682\r
683 @retval 0 Call completed without error\r
684 @retval -2 Invalid argument\r
685 @retval -3 Call completed with error.\r
686\r
687 @return R9 8-byte formatted value returning global virtual\r
688 memory information. See PAL_VM_INFO1 above.\r
689 @return R10 8-byte formatted value returning global virtual\r
690 memory information. See PAL_VM_INFO2 above.\r
691\r
692**/\r
693#define PAL_VM_SUMMARY 8\r
694\r
695\r
696//\r
697// Bit mask of TR_valid flag.\r
698//\r
699#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r
700#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r
701#define PAL_TR_DIRTY_IS_VALID BIT2\r
702#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r
703\r
704\r
705/**\r
706 PAL Procedure - PAL_VM_TR_READ.\r
707\r
708 Read contents of a translation register. It is required by\r
709 IPF. The PAL procedure supports the Stacked Register calling\r
710 convention. It could be called at physical mode.\r
711\r
712 @param Index Index of PAL_VM_TR_READ within the list\r
713 of PAL procedures.\r
714 @param RegNumber Unsigned 64-bit number denoting which TR to\r
715 read.\r
716 @param TrType Unsigned 64-bit number denoting whether to\r
717 read an ITR (0) or DTR (1). All other values\r
718 are reserved.\r
719 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r
720 which translation data is returned.\r
721\r
722 @retval 0 Call completed without error\r
723 @retval -2 Invalid argument\r
724 @retval -3 Call completed with error.\r
725\r
726 @return R9 Formatted bit vector denoting which fields are\r
727 valid. See TR_valid above.\r
728\r
729**/\r
730#define PAL_VM_TR_READ 261\r
731\r
732\r
733\r
734\r
735//\r
736// Bit Mask of Processor Bus Fesatures .\r
737//\r
738\r
739/**\r
740\r
741 When 0, bus data errors are detected and single bit errors are\r
742 corrected. When 1, no error detection or correction is done.\r
743\r
744**/\r
745#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r
746\r
747\r
748/**\r
749\r
750 When 0, bus address errors are signalled on the bus. When 1,\r
751 no bus errors are signalled on the bus. If Disable Bus Address\r
752 Error Checking is 1, this bit is ignored.\r
753\r
754**/\r
755#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r
756\r
757\r
758\r
759\r
760/**\r
761\r
762 When 0, bus errors are detected, single bit errors are\r
763 corrected., and a CMCI or MCA is generated internally to the\r
764 processor. When 1, no bus address errors are detected or\r
765 corrected.\r
766\r
767**/\r
768#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r
769\r
770\r
771/**\r
772\r
773 When 0, bus protocol errors (BINIT#) are signaled by the\r
774 processor on the bus. When 1, bus protocol errors (BINIT#) are\r
775 not signaled on the bus. If Disable Bus Initialization Event\r
776 Checking is 1, this bit is ignored.\r
777\r
778**/\r
779#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r
780\r
781\r
782/**\r
783\r
784 When 0, bus protocol errors (BINIT#) are detected and sampled\r
785 and an MCA is generated internally to the processor. When 1,\r
786 the processor will ignore bus protocol error conditions\r
787 (BINIT#).\r
788\r
789**/\r
790#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r
791\r
792\r
793\r
794/**\r
795\r
796 When 0, BERR# is signalled if a bus error is detected. When 1,\r
797 bus errors are not signalled on the bus.\r
798\r
799**/\r
800#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r
801\r
802\r
803\r
804\r
805/**\r
806\r
807 When 0, BERR# is signalled when internal processor requestor\r
808 initiated bus errors are detected. When 1, internal requester\r
809 bus errors are not signalled on the bus.\r
810\r
811**/\r
812#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r
813\r
814\r
815/**\r
816\r
817 When 0, the processor takes an MCA if BERR# is asserted. When\r
818 1, the processor ignores the BERR# signal.\r
819\r
820**/\r
821#define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r
822\r
823\r
824/**\r
825\r
826 When 0, the processor asserts BINIT# if it detects a parity\r
827 error on the signals which identify the transactions to which\r
828 this is a response. When 1, the processor ignores parity on\r
829 these signals.\r
830\r
831**/\r
832#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r
833\r
834\r
835/**\r
836\r
837 When 0, the in-order transaction queue is limited only by the\r
838 number of hardware entries. When 1, the processor's in-order\r
839 transactions queue is limited to one entry.\r
840\r
841**/\r
842#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r
843\r
844/**\r
845\r
846 Enable a bus cache line replacement transaction when a cache\r
847 line in the exclusive state is replaced from the highest level\r
848 processor cache and is not present in the lower level processor\r
849 caches. When 0, no bus cache line replacement transaction will\r
850 be seen on the bus. When 1, bus cache line replacement\r
851 transactions will be seen on the bus when the above condition is\r
852 detected.\r
853\r
854**/\r
855#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r
856\r
857\r
858/**\r
859\r
860 Enable a bus cache line replacement transaction when a cache\r
861 line in the shared or exclusive state is replaced from the\r
862 highest level processor cache and is not present in the lower\r
863 level processor caches.\r
864 When 0, no bus cache line replacement transaction will be seen\r
865 on the bus. When 1, bus cache line replacement transactions\r
866 will be seen on the bus when the above condition is detected.\r
867\r
868**/\r
869#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r
870\r
871\r
872\r
873/**\r
874\r
875 When 0, the data bus is configured at the 2x data transfer\r
876 rate.When 1, the data bus is configured at the 1x data\r
877 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r
878 processor executes locked transactions atomically. When 1, the\r
879 processor masks the bus lock signal and executes locked\r
880 transactions as a non-atomic series of transactions.\r
881\r
882**/\r
883#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r
884\r
885/**\r
886\r
887 When 0, the processor will deassert bus request when finished\r
888 with each transaction. When 1, the processor will continue to\r
889 assert bus request after it has finished, if it was the last\r
890 agent to own the bus and if there are no other pending\r
891 requests.\r
892\r
893**/\r
894#define PAL_BUS_REQUEST_BUS_PARKING BIT29\r
895\r
896\r
897/**\r
898 PAL Procedure - PAL_BUS_GET_FEATURES.\r
899\r
900 Return configurable processor bus interface features and their\r
901 current settings. It is required by IPF. The PAL procedure\r
902 supports the Stacked Register calling convention. It could be\r
903 called at physical mode.\r
904\r
905 @param Index Index of PAL_BUS_GET_FEATURES within the list\r
906 of PAL procedures.\r
907\r
908 @retval 0 Call completed without error\r
909 @retval -2 Invalid argument\r
910 @retval -3 Call completed with error.\r
911\r
912 @return R9 64-bit vector of features implemented.\r
913 (1=implemented, 0=not implemented)\r
914 @return R10 64-bit vector of current feature settings.\r
915 @return R11 64-bit vector of features controllable by\r
916 software. (1=controllable, 0= not controllable)\r
917\r
918**/\r
919#define PAL_BUS_GET_FEATURES 9\r
920\r
921/**\r
922 PAL Procedure - PAL_BUS_SET_FEATURES.\r
923\r
924 Enable or disable configurable features in processor bus\r
925 interface. It is required by IPF. It is required by IPF. The PAL procedure\r
926 supports the Static Registers calling convention. It could be\r
927 called at physical mode.\r
928\r
929 @param Index Index of PAL_BUS_SET_FEATURES within the list\r
930 of PAL procedures.\r
931 @param FeatureSelect 64-bit vector denoting desired state of\r
932 each feature (1=select, 0=non-select).\r
933\r
934 @retval 0 Call completed without error\r
935 @retval -2 Invalid argument\r
936 @retval -3 Call completed with error.\r
937\r
938**/\r
939#define PAL_BUS_SET_FEATURES 10\r
940\r
941\r
942/**\r
943 PAL Procedure - PAL_DEBUG_INFO.\r
944\r
945 Return the number of instruction and data breakpoint\r
946 registers. It is required by IPF. It is required by IPF. The\r
947 PAL procedure supports the Static Registers calling\r
948 convention. It could be called at physical mode and virtual\r
949 mode.\r
950\r
951 @param Index Index of PAL_DEBUG_INFO within the list of PAL\r
952 procedures.\r
953\r
954 @retval 0 Call completed without error\r
955 @retval -2 Invalid argument\r
956 @retval -3 Call completed with error.\r
957\r
958 @return R9 Unsigned 64-bit integer denoting the number of\r
959 pairs of instruction debug registers implemented\r
960 by the processor.\r
961 @return R10 Unsigned 64-bit integer denoting the number of\r
962 pairs of data debug registers implemented by the\r
963 processor.\r
964\r
965**/\r
966#define PAL_DEBUG_INFO 11\r
967\r
968/**\r
969 PAL Procedure - PAL_FIXED_ADDR.\r
970\r
971 Return the fixed component of a processor's directed address.\r
972 It is required by IPF. It is required by IPF. The PAL\r
973 procedure supports the Static Registers calling convention. It\r
974 could be called at physical mode and virtual mode.\r
975\r
976 @param Index Index of PAL_FIXED_ADDR within the list of PAL\r
977 procedures.\r
978\r
979 @retval 0 Call completed without error\r
980 @retval -2 Invalid argument\r
981 @retval -3 Call completed with error.\r
982\r
983 @return R9 Fixed geographical address of this processor.\r
984\r
985**/\r
986#define PAL_FIXED_ADDR 12\r
987\r
988/**\r
989 PAL Procedure - PAL_FREQ_BASE.\r
990\r
991 Return the frequency of the output clock for use by the\r
992 platform, if generated by the processor. It is optinal. The\r
993 PAL procedure supports the Static Registers calling\r
994 convention. It could be called at physical mode and virtual\r
995 mode.\r
996\r
997 @param Index Index of PAL_FREQ_BASE within the list of PAL\r
998 procedures.\r
999\r
1000 @retval 0 Call completed without error\r
1001 @retval -1 Unimplemented procedure\r
1002 @retval -2 Invalid argument\r
1003 @retval -3 Call completed with error.\r
1004\r
1005 @return R9 Base frequency of the platform if generated by the\r
1006 processor chip.\r
1007\r
1008**/\r
1009#define PAL_FREQ_BASE 13\r
1010\r
1011\r
1012/**\r
1013 PAL Procedure - PAL_FREQ_RATIOS.\r
1014\r
1015 Return ratio of processor, bus, and interval time counter to\r
1016 processor input clock or output clock for platform use, if\r
1017 generated by the processor. It is required by IPF. The PAL\r
1018 procedure supports the Static Registers calling convention. It\r
1019 could be called at physical mode and virtual mode.\r
1020\r
1021 @param Index Index of PAL_FREQ_RATIOS within the list of PAL\r
1022 procedures.\r
1023\r
1024 @retval 0 Call completed without error\r
1025 @retval -2 Invalid argument\r
1026 @retval -3 Call completed with error.\r
1027\r
1028 @return R9 Ratio of the processor frequency to the input\r
1029 clock of the processor, if the platform clock is\r
1030 generated externally or to the output clock to the\r
1031 platform, if the platform clock is generated by\r
1032 the processor.\r
1033 @return R10 Ratio of the bus frequency to the input clock of\r
1034 the processor, if the platform clock is generated\r
1035 externally or to the output clock to the platform,\r
1036 if the platform clock is generated by the\r
1037 processor.\r
1038 @return R11 Ratio of the interval timer counter rate to input\r
1039 clock of the processor, if the platform clock is\r
1040 generated externally or to the output clock to the\r
1041 platform, if the platform clock is generated by\r
1042 the processor.\r
1043\r
1044**/\r
1045#define PAL_FREQ_RATIOS 14\r
1046\r
1047/**\r
1048\r
1049 @param NumberOfLogicalProcessors Total number of logical\r
1050 processors on this physical\r
1051 processor package that are\r
1052 enabled.\r
1053\r
1054 @param ThreadsPerCore Number of threads per core.\r
1055\r
1056 @param CoresPerProcessor Total number of cores on this\r
1057 physical processor package.\r
1058\r
1059 @param PhysicalProcessorPackageId Physical processor package\r
1060 identifier which was\r
1061 assigned at reset by the\r
1062 platform or bus\r
1063 controller. This value may\r
1064 or may not be unique\r
1065 across the entire platform\r
1066 since it depends on the\r
1067 platform vendor's policy.\r
1068**/\r
1069typedef struct {\r
1070 UINT64 NumberOfLogicalProcessors:16;\r
1071 UINT64 ThreadsPerCore:8;\r
1072 UINT64 Reserved1:8;\r
1073 UINT64 CoresPerProcessor;\r
1074 UINT64 Reserved2:8;\r
1075 UINT64 PhysicalProcessorPackageId:8;\r
1076 UINT64 Reserved3:8;\r
1077} PAL_LOGICAL_PROCESSPR_OVERVIEW;\r
1078\r
1079/**\r
1080\r
1081 @param ThreadId The thread identifier of the logical\r
1082 processor for which information is being\r
1083 returned. This value will be unique on a per\r
1084 core basis.\r
1085\r
1086 @param CoreId The core identifier of the logical processor\r
1087 for which information is being returned.\r
1088 This value will be unique on a per physical\r
1089 processor package basis.\r
1090\r
1091**/\r
1092typedef struct {\r
1093 UINT64 ThreadId:16;\r
1094 UINT64 Reserved1:16;\r
1095 UINT64 CoreId:16;\r
1096 UINT64 Reserved2:16;\r
1097} PAL_LOGICAL_PROCESSORN_INFO1;\r
1098\r
1099\r
1100/**\r
1101\r
1102 @param LogicalAddress Geographical address of the logical\r
1103 processor for which information is being\r
1104 returned. This is the same value that is\r
1105 returned by the PAL_FIXED_ADDR procedure\r
1106 when it is called on the logical\r
1107 processor.\r
1108\r
1109\r
1110**/\r
1111typedef struct {\r
1112 UINT64 LogicalAddress:16;\r
1113 UINT64 Reserved:48;\r
1114} PAL_LOGICAL_PROCESSORN_INFO2;\r
1115\r
1116/**\r
1117 PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r
1118\r
1119 Return information on which logical processors map to a\r
1120 physical processor die. It is optinal. The PAL procedure\r
1121 supports the Static Registers calling convention. It could be\r
1122 called at physical mode and virtual mode.\r
1123\r
1124 @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r
1125 procedures.\r
1126 @param ProcessorNumber Signed 64-bit integer that specifies\r
1127 for which logical processor\r
1128 information is being requested. When\r
1129 this input argument is -1, information\r
1130 is returned about the logical\r
1131 processor on which the procedure call\r
1132 is made. This input argument must be\r
1133 in the range of 1 up to one less than\r
1134 the number of logical processors\r
1135 returned by num_log in the\r
1136 log_overview return value.\r
1137\r
1138 @retval 0 Call completed without error\r
1139 @retval -1 Unimplemented procedure\r
1140 @retval -2 Invalid argument\r
1141 @retval -3 Call completed with error.\r
1142\r
1143 @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r
1144 @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r
1145 @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r
1146\r
1147**/\r
1148#define PAL_LOGICAL_TO_PHYSICAL 42\r
1149\r
1150\r
1151/**\r
1152\r
1153 @param NumberOfPmcPairs Unsigned 8-bit number defining the\r
1154 number of generic PMC/PMD pairs.\r
1155\r
1156 @param WidthOfCounter Unsigned 8-bit number in the range\r
1157 0:60 defining the number of\r
1158 implemented counter bits.\r
1159\r
1160 @param TypeOfCycleCounting Unsigned 8-bit number defining the\r
1161 event type for counting processor\r
1162 cycles.\r
1163\r
1164\r
1165 @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit\r
1166 number defining the\r
1167 event type for retired\r
1168 instruction bundles.\r
1169\r
1170**/\r
1171typedef struct {\r
1172 UINT64 NumberOfPmcPairs:8;\r
1173 UINT64 WidthOfCounter:8;\r
1174 UINT64 TypeOfCycleCounting:8;\r
1175 UINT64 TypeOfRetiredInstructionBundle:8;\r
1176 UINT64 Reserved:32;\r
1177} PAL_PERFORMANCE_INFO;\r
1178\r
1179/**\r
1180 PAL Procedure - PAL_PERF_MON_INFO.\r
1181\r
1182 Return the number and type of performance monitors. It is\r
1183 required by IPF. The PAL procedure supports the Static\r
1184 Registers calling convention. It could be called at physical\r
1185 mode and virtual mode.\r
1186\r
1187 @param Index Index of PAL_PERF_MON_INFO within the list of\r
1188 PAL procedures.\r
1189 @param PerformanceBuffer An address to an 8-byte aligned\r
1190 128-byte memory buffer.\r
1191\r
1192 @retval 0 Call completed without error\r
1193 @retval -2 Invalid argument\r
1194 @retval -3 Call completed with error.\r
1195\r
1196 @return R9 Information about the performance monitors\r
1197 implemented. See PAL_PERFORMANCE_INFO;\r
1198\r
1199**/\r
1200#define PAL_PERF_MON_INFO 15\r
1201\r
1202#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0\r
1203#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r
1204\r
1205/**\r
1206 PAL Procedure - PAL_PLATFORM_ADDR.\r
1207\r
1208 Specify processor interrupt block address and I/O port space\r
1209 address. It is required by IPF. The PAL procedure supports the\r
1210 Static Registers calling convention. It could be called at\r
1211 physical mode and virtual mode.\r
1212\r
1213 @param Index Index of PAL_PLATFORM_ADDR within the list of\r
1214 PAL procedures.\r
1215 @param Type Unsigned 64-bit integer specifying the type of\r
1216 block. 0 indicates that the processor interrupt\r
1217 block pointer should be initialized. 1 indicates\r
1218 that the processor I/O block pointer should be\r
1219 initialized.\r
1220 @param Address Unsigned 64-bit integer specifying the address\r
1221 to which the processor I/O block or interrupt\r
1222 block shall be set. The address must specify\r
1223 an implemented physical address on the\r
1224 processor model, bit 63 is ignored.\r
1225\r
1226 @retval 0 Call completed without error\r
1227 @retval -1 Unimplemented procedure.\r
1228 @retval -2 Invalid argument\r
1229 @retval -3 Call completed with error.\r
1230\r
1231**/\r
1232#define PAL_PLATFORM_ADDR 16\r
1233\r
1234\r
1235/**\r
1236\r
1237 @param EnableBerrPromotion Bit63. Enable BERR promotion. When\r
1238 1, the Bus Error (BERR) signal is\r
1239 promoted to the Bus Initialization\r
1240 (BINIT) signal, and the BINIT pin\r
1241 is asserted on the occurrence of\r
1242 each Bus Error. Setting this bit\r
1243 has no effect if BINIT signalling\r
1244 is disabled. (See\r
1245 PAL_BUS_GET/SET_FEATURES)\r
1246\r
1247 @param EnableMcaPromotion Bit62, Enable MCA promotion. When\r
1248 1, machine check aborts (MCAs) are\r
1249 promoted to the Bus Error signal,\r
1250 and the BERR pin is assert on each\r
1251 occurrence of an MCA. Setting this\r
1252 bit has no effect if BERR\r
1253 signalling is disabled. (See\r
1254 PAL_BUS_GET/SET_FEATURES)\r
1255\r
1256 @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT\r
1257 promotion. When 1, machine\r
1258 check aborts (MCAs) are\r
1259 promoted to the Bus\r
1260 Initialization signal, and\r
1261 the BINIT pin is assert on\r
1262 each occurrence of an MCA.\r
1263 Setting this bit has no\r
1264 effect if BINIT signalling\r
1265 is disabled. (See\r
1266 PAL_BUS_GET/SET_FEATURES)\r
1267\r
1268 @param EnableCmciPromotion Bit60, Enable CMCI promotion When\r
1269 1, Corrected Machine Check\r
1270 Interrupts (CMCI) are promoted to\r
1271 MCAs. They are also further\r
1272 promoted to BERR if bit 39, Enable\r
1273 MCA promotion, is also set and\r
1274 they are promoted to BINIT if bit\r
1275 38, Enable MCA to BINIT promotion,\r
1276 is also set. This bit has no\r
1277 effect if MCA signalling is\r
1278 disabled (see\r
1279 PAL_BUS_GET/SET_FEATURES)\r
1280\r
1281 @param DisableCache Bit59, Disable Cache. When 0, the\r
1282 processor performs cast outs on\r
1283 cacheable pages and issues and responds\r
1284 to coherency requests normally. When 1,\r
1285 the processor performs a memory access\r
1286 for each reference regardless of cache\r
1287 contents and issues no coherence\r
1288 requests and responds as if the line\r
1289 were not present. Cache contents cannot\r
1290 be relied upon when the cache is\r
1291 disabled. WARNING: Semaphore\r
1292 instructions may not be atomic or may\r
1293 cause Unsupported Data Reference faults\r
1294 if caches are disabled.\r
1295\r
1296 @param DisableCoherency Bit58, Disable Coherency. When 0,\r
1297 the processor uses normal coherency\r
1298 requests and responses. When 1, the\r
1299 processor answers all requests as if\r
1300 the line were not present.\r
1301\r
1302 @param DisableDPM Bit57, Disable Dynamic Power Management\r
1303 (DPM). When 0, the hardware may reduce\r
1304 power consumption by removing the clock\r
1305 input from idle functional units. When 1,\r
1306 all functional units will receive clock\r
1307 input, even when idle.\r
1308\r
1309 @param DisableBinitWithTimeout Bit56, Disable a BINIT on\r
1310 internal processor time-out.\r
1311 When 0, the processor may\r
1312 generate a BINIT on an\r
1313 internal processor time-out.\r
1314 When 1, the processor will not\r
1315 generate a BINIT on an\r
1316 internal processor time-out.\r
1317 The event is silently ignored.\r
1318\r
1319\r
1320 @param EnableEnvNotification Bit55, Enable external\r
1321 notification when the processor\r
1322 detects hardware errors caused\r
1323 by environmental factors that\r
1324 could cause loss of\r
1325 deterministic behavior of the\r
1326 processor. When 1, this bit will\r
1327 enable external notification,\r
1328 when 0 external notification is\r
1329 not provided. The type of\r
1330 external notification of these\r
1331 errors is processor-dependent. A\r
1332 loss of processor deterministic\r
1333 behavior is considered to have\r
1334 occurred if these\r
1335 environmentally induced errors\r
1336 cause the processor to deviate\r
1337 from its normal execution and\r
1338 eventually causes different\r
1339 behavior which can be observed\r
1340 at the processor bus pins.\r
1341 Processor errors that do not\r
1342 have this effects (i.e.,\r
1343 software induced machine checks)\r
1344 may or may not be promoted\r
1345 depending on the processor\r
1346 implementation.\r
1347\r
1348 @param EnableVmsw Bit54, Enable the use of the vmsw\r
1349 instruction. When 0, the vmsw instruction\r
1350 causes a Virtualization fault when\r
1351 executed at the most privileged level.\r
1352 When 1, this bit will enable normal\r
1353 operation of the vmsw instruction.\r
1354\r
1355 @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling\r
1356 on data-poisoning event\r
1357 detection. When 0, a CMCI\r
1358 will be signaled on error\r
1359 detection. When 1, an MCA\r
1360 will be signaled on error\r
1361 detection. If this feature\r
1362 is not supported, then the\r
1363 corresponding argument is\r
1364 ignored when calling\r
1365 PAL_PROC_SET_FEATURES. Note\r
1366 that the functionality of\r
1367 this bit is independent of\r
1368 the setting in bit 60\r
1369 (Enable CMCI promotion), and\r
1370 that the bit 60 setting does\r
1371 not affect CMCI signaling\r
1372 for data-poisoning related\r
1373 events. Volume 2: Processor\r
1374 Abstraction Layer 2:431\r
1375 PAL_PROC_GET_FEATURES\r
1376\r
1377 @param DisablePState Bit52, Disable P-states. When 1, the PAL\r
1378 P-state procedures (PAL_PSTATE_INFO,\r
1379 PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
1380 return with a status of -1\r
1381 (Unimplemented procedure).\r
1382\r
1383 @param DisableBranchPrediction Bit47, Disable Dynamic branch\r
1384 prediction. When 0, the\r
1385 processor may predict branch\r
1386 targets and speculatively\r
1387 execute, but may not commit\r
1388 results. When 1, the processor\r
1389 must wait until branch targets\r
1390 are known to execute.\r
1391\r
1392 @param DisableDynamicInsCachePrefetch Bit46, Disable\r
1393 DynamicInstruction Cache\r
1394 Prefetch. When 0, the\r
1395 processor may prefetch\r
1396 into the caches any\r
1397 instruction which has\r
1398 not been executed, but\r
1399 whose execution is\r
1400 likely. When 1,\r
1401 instructions may not be\r
1402 fetched until needed or\r
1403 hinted for execution.\r
1404 (Prefetch for a hinted\r
1405 branch is allowed even\r
1406 when dynamic instruction\r
1407 cache prefetch is\r
1408 disabled.)\r
1409\r
1410 @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic\r
1411 Data Cache Prefetch.\r
1412 When 0, the processor\r
1413 may prefetch into the\r
1414 caches any data which\r
1415 has not been accessed\r
1416 by instruction\r
1417 execution, but which\r
1418 is likely to be\r
1419 accessed. When 1, no\r
1420 data may be fetched\r
1421 until it is needed for\r
1422 instruction execution\r
1423 or is fetched by an\r
1424 lfetch instruction.\r
1425\r
1426 @param DisableSpontaneousDeferral Bit44, Disable Spontaneous\r
1427 Deferral. When 1, the\r
1428 processor may optionally\r
1429 defer speculative loads\r
1430 that do not encounter any\r
1431 exception conditions, but\r
1432 that trigger other\r
1433 implementation-dependent\r
1434 conditions (e.g., cache\r
1435 miss). When 0, spontaneous\r
1436 deferral is disabled.\r
1437\r
1438 @param DisableDynamicPrediction Bit43, Disable Dynamic\r
1439 Predicate Prediction. When\r
1440 0, the processor may predict\r
1441 predicate results and\r
1442 execute speculatively, but\r
1443 may not commit results until\r
1444 the actual predicates are\r
1445 known. When 1, the processor\r
1446 shall not execute predicated\r
1447 instructions until the\r
1448 actual predicates are known.\r
1449\r
1450 @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.\r
1451 Denotes whether XR1 XR3 are\r
1452 implemented for machine check\r
1453 recovery. This feature may only be\r
1454 interrogated by PAL_PROC_GET_FEATURES.\r
1455 It may not be enabled or disabled by\r
1456 PAL_PROC_SET_FEATURES. The\r
1457 corresponding argument is ignored.\r
1458\r
1459 @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS\r
1460 implemented. Denotes whether XIP, XPSR,\r
1461 and XFS are implemented for machine\r
1462 check recovery. This feature may only be\r
1463 interrogated by PAL_PROC_GET_FEATURES.\r
1464 It may not be enabled or disabled by\r
1465 PAL_PROC_SET_FEATURES. The corresponding\r
1466 argument is ignored.\r
1467\r
1468 @param NoVM Bit40, No Virtual Machine features implemented.\r
1469 Denotes whether PSR.vm is implemented. This\r
1470 feature may only be interrogated by\r
1471 PAL_PROC_GET_FEATURES. It may not be enabled or\r
1472 disabled by PAL_PROC_SET_FEATURES. The\r
1473 corresponding argument is ignored.\r
1474\r
1475 @param NoVariablePState Bit39, No Variable P-state\r
1476 performance: A value of 1, indicates\r
1477 that a processor implements\r
1478 techniques to optimize performance\r
1479 for the given P-state power budget\r
1480 by dynamically varying the\r
1481 frequency, such that maximum\r
1482 performance is achieved for the\r
1483 power budget. A value of 0,\r
1484 indicates that P-states have no\r
1485 frequency variation or very small\r
1486 frequency variations for their given\r
1487 power budget. This feature may only\r
1488 be interrogated by\r
1489 PAL_PROC_GET_FEATURES. it may not be\r
1490 enabled or disabled by\r
1491 PAL_PROC_SET_FEATURES. The\r
1492 corresponding argument is ignored.\r
1493\r
1494\r
1495 @param NoSimpleImpInUndefinedIns Bit38, No Simple\r
1496 implementation of\r
1497 unimplemented instruction\r
1498 addresses. Denotes how an\r
1499 unimplemented instruction\r
1500 address is recorded in IIP\r
1501 on an Unimplemented\r
1502 Instruction Address trap or\r
1503 fault. When 1, the full\r
1504 unimplemented address is\r
1505 recorded in IIP; when 0, the\r
1506 address is sign extended\r
1507 (virtual addresses) or zero\r
1508 extended (physical\r
1509 addresses). This feature may\r
1510 only be interrogated by\r
1511 PAL_PROC_GET_FEATURES. It\r
1512 may not be enabled or\r
1513 disabled by\r
1514 PAL_PROC_SET_FEATURES. The\r
1515 corresponding argument is\r
1516 ignored.\r
1517\r
1518 @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins\r
1519 present. Denotes the absence of INIT,\r
1520 PMI, LINT0 and LINT1 pins on the\r
1521 processor. When 1, the pins are absent.\r
1522 When 0, the pins are present. This\r
1523 feature may only be interrogated by\r
1524 PAL_PROC_GET_FEATURES. It may not be\r
1525 enabled or disabled by\r
1526 PAL_PROC_SET_FEATURES. The corresponding\r
1527 argument is ignored.\r
1528\r
1529 @param FaultInUndefinedIns Bit36, No Unimplemented\r
1530 instruction address reported as\r
1531 fault. Denotes how the processor\r
1532 reports the detection of\r
1533 unimplemented instruction\r
1534 addresses. When 1, the processor\r
1535 reports an Unimplemented\r
1536 Instruction Address fault on the\r
1537 unimplemented address; when 0, it\r
1538 reports an Unimplemented\r
1539 Instruction Address trap on the\r
1540 previous instruction in program\r
1541 order. This feature may only be\r
1542 interrogated by\r
1543 PAL_PROC_GET_FEATURES. It may not\r
1544 be enabled or disabled by\r
1545 PAL_PROC_SET_FEATURES. The\r
1546 corresponding argument is\r
1547 ignored.\r
1548\r
1549**/\r
1550typedef struct {\r
1551 UINT64 Reserved1:36;\r
1552 UINT64 FaultInUndefinedIns:1;\r
1553 UINT64 NoPresentPmi:1;\r
1554 UINT64 NoSimpleImpInUndefinedIns:1;\r
1555 UINT64 NoVariablePState:1;\r
1556 UINT64 NoVM:1;\r
1557 UINT64 NoXipXpsrXfs:1;\r
1558 UINT64 NoXr1ThroughXr3:1;\r
1559 UINT64 DisableDynamicPrediction:1;\r
1560 UINT64 DisableSpontaneousDeferral:1;\r
1561 UINT64 DisableDynamicDataCachePrefetch:1;\r
1562 UINT64 DisableDynamicInsCachePrefetch:1;\r
1563 UINT64 DisableBranchPrediction:1;\r
1564 UINT64 Reserved2:4;\r
1565 UINT64 DisablePState:1;\r
1566 UINT64 EnableMcaOnDataPoisoning:1;\r
1567 UINT64 EnableVmsw:1;\r
1568 UINT64 EnableEnvNotification:1;\r
1569 UINT64 DisableBinitWithTimeout:1;\r
1570 UINT64 DisableDPM:1;\r
1571 UINT64 DisableCoherency:1;\r
1572 UINT64 DisableCache:1;\r
1573 UINT64 EnableCmciPromotion:1;\r
1574 UINT64 EnableMcaToBinitPromotion:1;\r
1575 UINT64 EnableMcaPromotion:1;\r
1576 UINT64 EnableBerrPromotion:1;\r
1577} PAL_PROCESSOR_FEATURES;\r
1578\r
1579/**\r
1580 PAL Procedure - PAL_PROC_GET_FEATURES.\r
1581\r
1582 Return configurable processor features and their current\r
1583 setting. It is required by IPF. The PAL procedure supports the\r
1584 Static Registers calling convention. It could be called at\r
1585 physical mode and virtual mode.\r
1586\r
1587 @param Index Index of PAL_PROC_GET_FEATURES within the list of\r
1588 PAL procedures.\r
1589 @param Reserved Reserved parameter.\r
1590 @param FeatureSet Feature set information is being requested\r
1591 for.\r
1592\r
1593 @retval 1 Call completed without error; The\r
1594 feature_set passed is not supported but a\r
1595 feature_set of a larger value is supported.\r
1596 @retval 0 Call completed without error\r
1597 @retval -2 Invalid argument\r
1598 @retval -3 Call completed with error.\r
1599 @retval -8 feature_set passed is beyond the maximum\r
1600 feature_set supported\r
1601\r
1602 @return R9 64-bit vector of features implemented. See\r
1603 PAL_PROCESSOR_FEATURES.\r
1604 @return R10 64-bit vector of current feature settings. See\r
1605 PAL_PROCESSOR_FEATURES.\r
1606 @return R11 64-bit vector of features controllable by\r
1607 software.\r
1608\r
1609**/\r
1610#define PAL_PROC_GET_FEATURES 17\r
1611\r
1612\r
1613/**\r
1614 PAL Procedure - PAL_PROC_SET_FEATURES.\r
1615\r
1616 Enable or disable configurable processor features. It is\r
1617 required by IPF. The PAL procedure supports the Static\r
1618 Registers calling convention. It could be called at physical\r
1619 mode.\r
1620\r
1621 @param Index Index of PAL_PROC_SET_FEATURES within the list of\r
1622 PAL procedures.\r
1623 @param FeatureSelect 64-bit vector denoting desired state of\r
1624 each feature (1=select, 0=non-select).\r
1625 @param FeatureSet Feature set to apply changes to. See\r
1626 PAL_PROC_GET_FEATURES for more information\r
1627 on feature sets.\r
1628\r
1629 @retval 1 Call completed without error; The\r
1630 feature_set passed is not supported but a\r
1631 feature_set of a larger value is supported\r
1632 @retval 0 Call completed without error\r
1633 @retval -2 Invalid argument\r
1634 @retval -3 Call completed with error.\r
1635 @retval -8 feature_set passed is beyond the maximum\r
1636 feature_set supported\r
1637\r
1638**/\r
1639#define PAL_PROC_SET_FEATURES 18\r
1640\r
1641\r
1642//\r
1643// Value of PAL_REGISTER_INFO.InfoRequest.\r
1644//\r
1645#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r
1646#define PAL_APPLICATION_REGISTER_READABLE 1\r
1647#define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r
1648#define PAL_CONTROL_REGISTER_READABLE 3\r
1649\r
1650\r
1651/**\r
1652 PAL Procedure - PAL_REGISTER_INFO.\r
1653\r
1654 Return AR and CR register information. It is required by IPF.\r
1655 The PAL procedure supports the Static Registers calling\r
1656 convention. It could be called at physical mode and virtual\r
1657 mode.\r
1658\r
1659 @param Index Index of PAL_REGISTER_INFO within the list of\r
1660 PAL procedures.\r
1661 @param InfoRequest Unsigned 64-bit integer denoting what\r
1662 register information is requested. See\r
1663 PAL_REGISTER_INFO.InfoRequest above.\r
1664\r
1665 @retval 0 Call completed without error\r
1666 @retval -2 Invalid argument\r
1667 @retval -3 Call completed with error.\r
1668\r
1669 @return R9 64-bit vector denoting information for registers\r
1670 0-63. Bit 0 is register 0, bit 63 is register 63.\r
1671 @return R10 64-bit vector denoting information for registers\r
1672 64-127. Bit 0 is register 64, bit 63 is register\r
1673 127.\r
1674\r
1675**/\r
1676#define PAL_REGISTER_INFO 39\r
1677\r
1678/**\r
1679 PAL Procedure - PAL_RSE_INFO.\r
1680\r
1681 Return RSE information. It is required by IPF. The PAL\r
1682 procedure supports the Static Registers calling convention. It\r
1683 could be called at physical mode and virtual mode.\r
1684\r
1685 @param Index Index of PAL_RSE_INFO within the list of\r
1686 PAL procedures.\r
1687 @param InfoRequest Unsigned 64-bit integer denoting what\r
1688 register information is requested. See\r
1689 PAL_REGISTER_INFO.InfoRequest above.\r
1690\r
1691 @retval 0 Call completed without error\r
1692 @retval -2 Invalid argument\r
1693 @retval -3 Call completed with error.\r
1694\r
1695 @return R9 Number of physical stacked general registers.\r
1696 @return R10 RSE hints supported by processor.\r
1697\r
1698**/\r
1699#define PAL_RSE_INFO 19\r
1700\r
1701/**\r
1702\r
1703 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r
1704 number that provides identification\r
1705 information about the PAL_B firmware.\r
1706\r
1707 @param PalVendor Is an unsigned 8-bit integer indicating the\r
1708 vendor of the PAL code.\r
1709\r
1710 @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r
1711 number that provides identification\r
1712 information about the PAL_A firmware. In\r
1713 the split PAL_A model, this return value\r
1714 is the version number of the\r
1715 processor-specific PAL_A. The generic\r
1716 PAL_A version is not returned by this\r
1717 procedure in the split PAL_A model.\r
1718\r
1719**/\r
1720typedef struct {\r
1721 UINT64 VersionOfPalB:16;\r
1722 UINT64 Reserved1:8;\r
1723 UINT64 PalVendor:8;\r
1724 UINT64 VersionOfPalA:16;\r
1725 UINT64 Reserved2:16;\r
1726} PAL_VERSION_INFO;\r
1727\r
1728/**\r
1729 PAL Procedure - PAL_VERSION.\r
1730\r
1731 Return version of PAL code. It is required by IPF. The PAL\r
1732 procedure supports the Static Registers calling convention. It\r
1733 could be called at physical mode and virtual mode.\r
1734\r
1735 @param Index Index of PAL_VERSION within the list of\r
1736 PAL procedures.\r
1737 @param InfoRequest Unsigned 64-bit integer denoting what\r
1738 register information is requested. See\r
1739 PAL_REGISTER_INFO.InfoRequest above.\r
1740\r
1741 @retval 0 Call completed without error\r
1742 @retval -2 Invalid argument\r
1743 @retval -3 Call completed with error.\r
1744\r
1745 @return R9 8-byte formatted value returning the minimum PAL\r
1746 version needed for proper operation of the\r
1747 processor. See PAL_VERSION_INFO above.\r
1748 @return R10 8-byte formatted value returning the current PAL\r
1749 version running on the processor. See\r
1750 PAL_VERSION_INFO above.\r
1751\r
1752**/\r
1753#define PAL_VERSION 20\r
1754\r
1755\r
1756\r
1757//\r
1758// Vectors of PAL_MC_CLEAR_LOG.pending\r
1759//\r
1760#define PAL_MC_PENDING BIT0\r
1761#define PAL_INIT_PENDING BIT1\r
1762\r
1763/**\r
1764 PAL Procedure - PAL_MC_CLEAR_LOG.\r
1765\r
1766 Clear all error information from processor error logging\r
1767 registers. It is required by IPF. The PAL procedure supports\r
1768 the Static Registers calling convention. It could be called at\r
1769 physical mode and virtual mode.\r
1770\r
1771 @param Index Index of PAL_MC_CLEAR_LOG within the list of\r
1772 PAL procedures.\r
1773\r
1774 @retval 0 Call completed without error\r
1775 @retval -2 Invalid argument\r
1776 @retval -3 Call completed with error.\r
1777\r
1778 @return R9 64-bit vector denoting whether an event is\r
1779 pending. See PAL_MC_CLEAR_LOG.pending above.\r
1780\r
1781**/\r
1782#define PAL_MC_CLEAR_LOG 21\r
1783\r
1784/**\r
1785 PAL Procedure - PAL_MC_DRAIN.\r
1786\r
1787 Ensure that all operations that could cause an MCA have\r
1788 completed. It is required by IPF. The PAL procedure supports\r
1789 the Static Registers calling convention. It could be called at\r
1790 physical mode and virtual mode.\r
1791\r
1792 @param Index Index of PAL_MC_DRAIN within the list of PAL\r
1793 procedures.\r
1794\r
1795 @retval 0 Call completed without error\r
1796 @retval -2 Invalid argument\r
1797 @retval -3 Call completed with error.\r
1798\r
1799**/\r
1800#define PAL_MC_DRAIN 22\r
1801\r
1802\r
1803/**\r
1804 PAL Procedure - PAL_MC_DYNAMIC_STATE.\r
1805\r
1806 Return Processor Dynamic State for logging by SAL. It is\r
1807 optional. The PAL procedure supports the Static Registers\r
1808 calling convention. It could be called at physical mode.\r
1809\r
1810 @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r
1811 procedures.\r
1812 @param Offset Offset of the next 8 bytes of Dynamic Processor\r
1813 State to return. (multiple of 8).\r
1814\r
1815 @retval 0 Call completed without error\r
1816 @retval -1 Unimplemented procedure.\r
1817 @retval -2 Invalid argument\r
1818 @retval -3 Call completed with error.\r
1819\r
1820 @return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r
1821 Processor State returned.\r
1822 @return R10 Next 8 bytes of Dynamic Processor State.\r
1823\r
1824**/\r
1825#define PAL_MC_DYNAMIC_STATE 24\r
1826\r
1827\r
1828\r
1829//\r
1830// Values of PAL_MC_ERROR_INFO.InfoIndex.\r
1831//\r
1832#define PAL_PROCESSOR_ERROR_MAP 0\r
1833#define PAL_PROCESSOR_STATE_PARAM 1\r
1834#define PAL_STRUCTURE_SPECIFIC_ERROR 2\r
1835\r
1836/**\r
1837\r
1838 @param CoreId Bit3:0, Processor core ID (default is 0 for\r
1839 processors with a single core)\r
1840\r
1841 @param ThreadId Bit7:4, Logical thread ID (default is 0 for\r
1842 processors that execute a single thread)\r
1843\r
1844 @param InfoOfInsCache Bit11:8, Error information is\r
1845 available for 1st, 2nd, 3rd, and 4th\r
1846 level instruction caches.\r
1847\r
1848 @param InfoOfDataCache Bit15:12, Error information is\r
1849 available for 1st, 2nd, 3rd, and 4th\r
1850 level data/unified caches.\r
1851\r
1852 @param InfoOfInsTlb Bit19:16 Error information is available\r
1853 for 1st, 2nd, 3rd, and 4th level\r
1854 instruction TLB.\r
1855\r
1856 @param InfoOfDataTlb Bit23:20, Error information is available\r
1857 for 1st, 2nd, 3rd, and 4th level\r
1858 data/unified TLB\r
1859\r
1860 @param InfoOfProcessorBus Bit27:24 Error information is\r
1861 available for the 1st, 2nd, 3rd,\r
1862 and 4th level processor bus\r
1863 hierarchy.\r
1864\r
1865 @param InfoOfRegisterFile Bit31:28 Error information is\r
1866 available on register file\r
1867 structures.\r
1868\r
1869 @param InfoOfMicroArch Bit47:32, Error information is\r
1870 available on micro-architectural\r
1871 structures.\r
1872\r
1873**/\r
1874typedef struct {\r
1875 UINT64 CoreId:4;\r
1876 UINT64 ThreadId:4;\r
1877 UINT64 InfoOfInsCache:4;\r
1878 UINT64 InfoOfDataCache:4;\r
1879 UINT64 InfoOfInsTlb:4;\r
1880 UINT64 InfoOfDataTlb:4;\r
1881 UINT64 InfoOfProcessorBus:4;\r
1882 UINT64 InfoOfRegisterFile:4;\r
1883 UINT64 InfoOfMicroArch:4;\r
1884 UINT64 Reserved:16;\r
1885} PAL_MC_ERROR_INFO_LEVEL_INDEX;\r
1886\r
1887//\r
1888// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r
1889//\r
1890#define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r
1891#define PAL_ERR_INFO_TARGET_ADDRESS 1\r
1892#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r
1893#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3\r
1894#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r
1895\r
1896/**\r
1897\r
1898 @param Operation Bit3:0, Type of cache operation that caused\r
1899 the machine check: 0 - unknown or internal\r
1900 error 1 - load 2 - store 3 - instruction\r
1901 fetch or instruction prefetch 4 - data\r
1902 prefetch (both hardware and software) 5 -\r
1903 snoop (coherency check) 6 - cast out\r
1904 (explicit or implicit write-back of a cache\r
1905 line) 7 - move in (cache line fill)\r
1906\r
1907 @param FailedCacheLevel Bit5:4 Level of cache where the\r
1908 error occurred. A value of 0\r
1909 indicates the first level of cache.\r
1910\r
1911 @param FailedInDataPart Bit8, Failure located in the data\r
1912 part of the cache line.\r
1913\r
1914 @param FailedInTagPart Bit9, Failure located in the tag part\r
1915 of the cache line.\r
1916\r
1917 @param FailedInDataCache Bit10, Failure located in the data\r
1918 cache\r
1919\r
1920 @param FailedInInsCache Bit11, Failure located in the\r
1921 instruction cache.\r
1922\r
1923\r
1924 @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache\r
1925 line is held shared. 2 - cache line is held\r
1926 exclusive. 3 - cache line is modified. All other\r
1927 values are reserved.\r
1928\r
1929 @param MesiIsValid Bit15, The mesi field in the cache_check\r
1930 parameter is valid.\r
1931\r
1932 @param FailedWay Bit20:16, Failure located in the way of\r
1933 the cache indicated by this value.\r
1934\r
1935 @param WayIndexIsValid Bit21, The way and index field in the\r
1936 cache_check parameter is valid.\r
1937\r
1938 @param MultipleBitsError Bit23, A multiple-bit error was\r
1939 detected, and data was poisoned for\r
1940 the corresponding cache line during\r
1941 castout.\r
1942\r
1943 @param IndexOfCacheLineError Bit51:32, Index of the cache\r
1944 line where the error occurred.\r
1945\r
1946 @param InstructionSet Bit54, Instruction set. If this value\r
1947 is set to zero, the instruction that\r
1948 generated the machine check was an\r
1949 Intel Itanium instruction. If this bit\r
1950 is set to one, the instruction that\r
1951 generated the machine check was IA-32\r
1952 instruction.\r
1953\r
1954 @param InstructionSetIsValid Bit55, The is field in the\r
1955 cache_check parameter is valid.\r
1956\r
1957 @param PrivilegeLevel Bit57:56, Privilege level. The\r
1958 privilege level of the instruction\r
1959 bundle responsible for generating the\r
1960 machine check.\r
1961\r
1962 @param PrivilegeLevelIsValide Bit58, The pl field of the\r
1963 cache_check parameter is\r
1964 valid.\r
1965\r
1966 @param McCorrected Bit59, Machine check corrected: This bit\r
1967 is set to one to indicate that the machine\r
1968 check has been corrected.\r
1969\r
1970 @param TargetAddressIsValid Bit60, Target address is valid:\r
1971 This bit is set to one to\r
1972 indicate that a valid target\r
1973 address has been logged.\r
1974\r
1975 @param RequesterIdentifier Bit61, Requester identifier: This\r
1976 bit is set to one to indicate that\r
1977 a valid requester identifier has\r
1978 been logged.\r
1979\r
1980 @param ResponserIdentifier Bit62, Responder identifier: This\r
1981 bit is set to one to indicate that\r
1982 a valid responder identifier has\r
1983 been logged.\r
1984\r
1985 @param PreciseInsPointer Bit63, Precise instruction pointer.\r
1986 This bit is set to one to indicate\r
1987 that a valid precise instruction\r
1988 pointer has been logged.\r
1989\r
1990**/\r
1991typedef struct {\r
1992 UINT64 Operation:4;\r
1993 UINT64 FailedCacheLevel:2;\r
1994 UINT64 Reserved1:2;\r
1995 UINT64 FailedInDataPart:1;\r
1996 UINT64 FailedInTagPart:1;\r
1997 UINT64 FailedInDataCache:1;\r
1998 UINT64 FailedInInsCache:1;\r
1999 UINT64 Mesi:3;\r
2000 UINT64 MesiIsValid:1;\r
2001 UINT64 FailedWay:5;\r
2002 UINT64 WayIndexIsValid:1;\r
2003\r
2004 UINT64 Reserved2:1;\r
2005 UINT64 MultipleBitsError:1;\r
2006 UINT64 Reserved3:8;\r
2007 UINT64 IndexOfCacheLineError:20;\r
2008 UINT64 Reserved4:2;\r
2009 UINT64 InstructionSet:1;\r
2010 UINT64 InstructionSetIsValid:1;\r
2011\r
2012 UINT64 PrivilegeLevel:2;\r
2013 UINT64 PrivilegeLevelIsValide:1;\r
2014\r
2015 UINT64 McCorrected:1;\r
2016\r
2017 UINT64 TargetAddressIsValid:1;\r
2018 UINT64 RequesterIdentifier:1;\r
2019 UINT64 ResponserIdentifier:1;\r
2020 UINT64 PreciseInsPointer:1;\r
2021\r
2022} PAL_CACHE_CHECK_INFO;\r
2023\r
2024/**\r
2025\r
2026 @param FailedSlot Bit7:0, Slot number of the translation\r
2027 register where the failure occurred.\r
2028\r
2029 @param FailedSlotIsValid Bit8, The tr_slot field in the\r
2030 TLB_check parameter is valid.\r
2031\r
2032 @param TlbLevel Bit11:10, The level of the TLB where the\r
2033 error occurred. A value of 0 indicates the\r
2034 first level of TLB\r
2035\r
2036 @param FailedInDataTr Bit16, Error occurred in the data\r
2037 translation registers.\r
2038\r
2039 @param FailedInInsTr Bit17, Error occurred in the instruction\r
2040 translation registers\r
2041\r
2042 @param FailedInDataTc Bit18, Error occurred in data\r
2043 translation cache.\r
2044\r
2045 @param FailedInInsTc Bit19, Error occurred in the instruction\r
2046 translation cache.\r
2047\r
2048 @param FailedOperation Bit23:20, Type of cache operation that\r
2049 caused the machine check: 0 - unknown\r
2050 1 - TLB access due to load instruction\r
2051 2 - TLB access due to store\r
2052 instruction 3 - TLB access due to\r
2053 instruction fetch or instruction\r
2054 prefetch 4 - TLB access due to data\r
2055 prefetch (both hardware and software)\r
2056 5 - TLB shoot down access 6 - TLB\r
2057 probe instruction (probe, tpa) 7 -\r
2058 move in (VHPT fill) 8 - purge (insert\r
2059 operation that purges entries or a TLB\r
2060 purge instruction) All other values\r
2061 are reserved.\r
2062\r
2063 @param InstructionSet Bit54, Instruction set. If this value\r
2064 is set to zero, the instruction that\r
2065 generated the machine check was an\r
2066 Intel Itanium instruction. If this bit\r
2067 is set to one, the instruction that\r
2068 generated the machine check was IA-32\r
2069 instruction.\r
2070\r
2071 @param InstructionSetIsValid Bit55, The is field in the\r
2072 TLB_check parameter is valid.\r
2073\r
2074 @param PrivelegeLevel Bit57:56, Privilege level. The\r
2075 privilege level of the instruction\r
2076 bundle responsible for generating the\r
2077 machine check.\r
2078\r
2079 @param PrivelegeLevelIsValid Bit58, The pl field of the\r
2080 TLB_check parameter is valid.\r
2081\r
2082 @param McCorrected Bit59, Machine check corrected: This bit\r
2083 is set to one to indicate that the machine\r
2084 check has been corrected.\r
2085\r
2086 @param TargetAddressIsValid Bit60, Target address is valid:\r
2087 This bit is set to one to\r
2088 indicate that a valid target\r
2089 address has been logged.\r
2090\r
2091 @param RequesterIdentifier Bit61 Requester identifier: This\r
2092 bit is set to one to indicate that\r
2093 a valid requester identifier has\r
2094 been logged.\r
2095\r
2096 @param ResponserIdentifier Bit62, Responder identifier: This\r
2097 bit is set to one to indicate that\r
2098 a valid responder identifier has\r
2099 been logged.\r
2100\r
2101 @param PreciseInsPointer Bit63 Precise instruction pointer.\r
2102 This bit is set to one to indicate\r
2103 that a valid precise instruction\r
2104 pointer has been logged.\r
2105**/\r
2106typedef struct {\r
2107 UINT64 FailedSlot:8;\r
2108 UINT64 FailedSlotIsValid:1;\r
2109 UINT64 Reserved1 :1;\r
2110 UINT64 TlbLevel:2;\r
2111 UINT64 Reserved2 :4;\r
2112 UINT64 FailedInDataTr:1;\r
2113 UINT64 FailedInInsTr:1;\r
2114 UINT64 FailedInDataTc:1;\r
2115 UINT64 FailedInInsTc:1;\r
2116 UINT64 FailedOperation:4;\r
2117 UINT64 Reserved3:30;\r
2118 UINT64 InstructionSet:1;\r
2119 UINT64 InstructionSetIsValid:1;\r
2120 UINT64 PrivelegeLevel:2;\r
2121 UINT64 PrivelegeLevelIsValid:1;\r
2122 UINT64 McCorrected:1;\r
2123 UINT64 TargetAddressIsValid:1;\r
2124 UINT64 RequesterIdentifier:1;\r
2125 UINT64 ResponserIdentifier:1;\r
2126 UINT64 PreciseInsPointer:1;\r
2127} PAL_TLB_CHECK_INFO;\r
2128\r
2129/**\r
2130 PAL Procedure - PAL_MC_ERROR_INFO.\r
2131\r
2132 Return Processor Machine Check Information and Processor\r
2133 Static State for logging by SAL. It is required by IPF. The\r
2134 PAL procedure supports the Static Registers calling\r
2135 convention. It could be called at physical and virtual mode.\r
2136\r
2137 @param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r
2138 procedures.\r
2139 @param InfoIndex Unsigned 64-bit integer identifying the\r
2140 error information that is being requested.\r
2141 See PAL_MC_ERROR_INFO.InfoIndex.\r
2142 @param LevelIndex 8-byte formatted value identifying the\r
2143 structure to return error information\r
2144 on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r
2145 @param ErrorTypeIndex Unsigned 64-bit integer denoting the\r
2146 type of error information that is\r
2147 being requested for the structure\r
2148 identified in LevelIndex.\r
2149\r
2150 @retval 0 Call completed without error\r
2151 @retval -2 Invalid argument\r
2152 @retval -3 Call completed with error.\r
2153 @retval -6 Argument was valid, but no error\r
2154 information was available\r
2155\r
2156 @return R9 Error information returned. The format of this\r
2157 value is dependant on the input values passed.\r
2158 @return R10 If this value is zero, all the error information\r
2159 specified by err_type_index has been returned. If\r
2160 this value is one, more structure-specific error\r
2161 information is available and the caller needs to\r
2162 make this procedure call again with level_index\r
2163 unchanged and err_type_index, incremented.\r
2164\r
2165**/\r
2166#define PAL_MC_ERROR_INFO 25\r
2167\r
2168/**\r
2169 PAL Procedure - PAL_MC_EXPECTED.\r
2170\r
2171 Set/Reset Expected Machine Check Indicator. It is required by\r
2172 IPF. The PAL procedure supports the Static Registers calling\r
2173 convention. It could be called at physical mode.\r
2174\r
2175 @param Index Index of PAL_MC_EXPECTED within the list of PAL\r
2176 procedures.\r
2177 @param Expected Unsigned integer with a value of 0 or 1 to\r
2178 set or reset the hardware resource\r
2179 PALE_CHECK examines for expected machine\r
2180 checks.\r
2181\r
2182 @retval 0 Call completed without error\r
2183 @retval -2 Invalid argument\r
2184 @retval -3 Call completed with error.\r
2185\r
2186 @return R9 Unsigned integer denoting whether a machine check\r
2187 was previously expected.\r
2188\r
2189**/\r
2190#define PAL_MC_EXPECTED 23\r
2191\r
2192/**\r
2193 PAL Procedure - PAL_MC_REGISTER_MEM.\r
2194\r
2195 Register min-state save area with PAL for machine checks and\r
2196 inits. It is required by IPF. The PAL procedure supports the\r
2197 Static Registers calling convention. It could be called at\r
2198 physical mode.\r
2199\r
2200 @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r
2201 procedures.\r
2202 @param Address Physical address of the buffer to be\r
2203 registered with PAL.\r
2204\r
2205 @retval 0 Call completed without error\r
2206 @retval -2 Invalid argument\r
2207 @retval -3 Call completed with error.\r
2208\r
2209**/\r
2210#define PAL_MC_REGISTER_MEM 27\r
2211\r
2212/**\r
2213 PAL Procedure - PAL_MC_RESUME.\r
2214\r
2215 Restore minimal architected state and return to interrupted\r
2216 process. It is required by IPF. The PAL procedure supports the\r
2217 Static Registers calling convention. It could be called at\r
2218 physical mode.\r
2219\r
2220 @param Index Index of PAL_MC_RESUME within the list of PAL\r
2221 procedures.\r
2222 @param SetCmci Unsigned 64 bit integer denoting whether to\r
2223 set the CMC interrupt. A value of 0 indicates\r
2224 not to set the interrupt, a value of 1\r
2225 indicated to set the interrupt, and all other\r
2226 values are reserved.\r
2227 @param SavePtr Physical address of min-state save area used\r
2228 to used to restore processor state.\r
2229 @param NewContext Unsigned 64-bit integer denoting whether\r
2230 the caller is returning to a new context.\r
2231 A value of 0 indicates the caller is\r
2232 returning to the interrupted context, a\r
2233 value of 1 indicates that the caller is\r
2234 returning to a new context.\r
2235\r
2236 @retval -2 Invalid argument\r
2237 @retval -3 Call completed with error.\r
2238\r
2239**/\r
2240#define PAL_MC_RESUME 26\r
2241\r
2242/**\r
2243 PAL Procedure - PAL_HALT.\r
2244\r
2245 Enter the low-power HALT state or an implementation-dependent\r
2246 low-power state. It is optinal. The PAL procedure supports the\r
2247 Static Registers calling convention. It could be called at\r
2248 physical mode.\r
2249\r
2250 @param Index Index of PAL_HALT within the list of PAL\r
2251 procedures.\r
2252 @param HaltState Unsigned 64-bit integer denoting low power\r
2253 state requested.\r
2254 @param IoDetailPtr 8-byte aligned physical address pointer to\r
2255 information on the type of I/O\r
2256 (load/store) requested.\r
2257\r
2258 @retval 0 Call completed without error\r
2259 @retval -1 Unimplemented procedure\r
2260 @retval -2 Invalid argument\r
2261 @retval -3 Call completed with error.\r
2262\r
2263 @return R9 Value returned if a load instruction is requested\r
2264 in the io_detail_ptr\r
2265\r
2266**/\r
2267#define PAL_HALT 28\r
2268\r
2269\r
2270/**\r
2271 PAL Procedure - PAL_HALT_INFO.\r
2272\r
2273 Return the low power capabilities of the processor. It is\r
2274 required by IPF. The PAL procedure supports the\r
2275 Stacked Registers calling convention. It could be called at\r
2276 physical and virtual mode.\r
2277\r
2278 @param Index Index of PAL_HALT_INFO within the list of PAL\r
2279 procedures.\r
2280 @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r
2281 on an 8-byte boundary.\r
2282\r
2283 @retval 0 Call completed without error\r
2284 @retval -2 Invalid argument\r
2285 @retval -3 Call completed with error.\r
2286\r
2287**/\r
2288#define PAL_HALT_INFO 257\r
2289\r
2290\r
2291/**\r
2292 PAL Procedure - PAL_HALT_LIGHT.\r
2293\r
2294 Enter the low power LIGHT HALT state. It is required by\r
2295 IPF. The PAL procedure supports the Static Registers calling\r
2296 convention. It could be called at physical and virtual mode.\r
2297\r
2298 @param Index Index of PAL_HALT_LIGHT within the list of PAL\r
2299 procedures.\r
2300\r
2301 @retval 0 Call completed without error\r
2302 @retval -2 Invalid argument\r
2303 @retval -3 Call completed with error.\r
2304\r
2305**/\r
2306#define PAL_HALT_LIGHT 29\r
2307\r
2308/**\r
2309 PAL Procedure - PAL_CACHE_LINE_INIT.\r
2310\r
2311 Initialize tags and data of a cache line for processor\r
2312 testing. It is required by IPF. The PAL procedure supports the\r
2313 Static Registers calling convention. It could be called at\r
2314 physical and virtual mode.\r
2315\r
2316 @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r
2317 procedures.\r
2318 @param Address Unsigned 64-bit integer value denoting the\r
2319 physical address from which the physical page\r
2320 number is to be generated. The address must be\r
2321 an implemented physical address, bit 63 must\r
2322 be zero.\r
2323 @param DataValue 64-bit data value which is used to\r
2324 initialize the cache line.\r
2325\r
2326 @retval 0 Call completed without error\r
2327 @retval -2 Invalid argument\r
2328 @retval -3 Call completed with error.\r
2329\r
2330**/\r
2331#define PAL_CACHE_LINE_INIT 31\r
2332\r
2333/**\r
2334 PAL Procedure - PAL_CACHE_READ.\r
2335\r
2336 Read tag and data of a cache line for diagnostic testing. It\r
2337 is optional. The PAL procedure supports the\r
2338 Satcked Registers calling convention. It could be called at\r
2339 physical mode.\r
2340\r
2341 @param Index Index of PAL_CACHE_READ within the list of PAL\r
2342 procedures.\r
2343 @param LineId 8-byte formatted value describing where in the\r
2344 cache to read the data.\r
2345 @param Address 64-bit 8-byte aligned physical address from\r
2346 which to read the data. The address must be an\r
2347 implemented physical address on the processor\r
2348 model with bit 63 set to zero.\r
2349\r
2350 @retval 1 The word at address was found in the\r
2351 cache, but the line was invalid.\r
2352 @retval 0 Call completed without error\r
2353 @retval -2 Invalid argument\r
2354 @retval -3 Call completed with error.\r
2355 @retval -5 The word at address was not found in the\r
2356 cache.\r
2357 @retval -7 The operation requested is not supported\r
2358 for this cache_type and level.\r
2359\r
2360 @return R9 Right-justified value returned from the cache\r
2361 line.\r
2362 @return R10 The number of bits returned in data.\r
2363 @return R11 The status of the cache line.\r
2364\r
2365**/\r
2366#define PAL_CACHE_READ 259\r
2367\r
2368\r
2369/**\r
2370 PAL Procedure - PAL_CACHE_WRITE.\r
2371\r
2372 Write tag and data of a cache for diagnostic testing. It is\r
2373 optional. The PAL procedure supports the Satcked Registers\r
2374 calling convention. It could be called at physical mode.\r
2375\r
2376 @param Index Index of PAL_CACHE_WRITE within the list of PAL\r
2377 procedures.\r
2378 @param LineId 8-byte formatted value describing where in the\r
2379 cache to write the data.\r
2380 @param Address 64-bit 8-byte aligned physical address at\r
2381 which the data should be written. The address\r
2382 must be an implemented physical address on the\r
2383 processor model with bit 63 set to 0.\r
2384 @param Data Unsigned 64-bit integer value to write into\r
2385 the specified part of the cache.\r
2386\r
2387 @retval 0 Call completed without error\r
2388 @retval -2 Invalid argument\r
2389 @retval -3 Call completed with error.\r
2390 @retval -7 The operation requested is not supported\r
2391 for this cache_type and level.\r
2392\r
2393**/\r
2394#define PAL_CACHE_WRITE 260\r
2395\r
2396/**\r
2397 PAL Procedure - PAL_TEST_INFO.\r
2398\r
2399 Returns alignment and size requirements needed for the memory\r
2400 buffer passed to the PAL_TEST_PROC procedure as well as\r
2401 information on self-test control words for the processor self\r
2402 tests. It is required by IPF. The PAL procedure supports the\r
2403 Static Registers calling convention. It could be called at\r
2404 physical mode.\r
2405\r
2406 @param Index Index of PAL_TEST_INFO within the list of PAL\r
2407 procedures.\r
2408 @param TestPhase Unsigned integer that specifies which phase\r
2409 of the processor self-test information is\r
2410 being requested on. A value of 0 indicates\r
2411 the phase two of the processor self-test and\r
2412 a value of 1 indicates phase one of the\r
2413 processor self-test. All other values are\r
2414 reserved.\r
2415\r
2416 @retval 0 Call completed without error\r
2417 @retval -2 Invalid argument\r
2418 @retval -3 Call completed with error.\r
2419\r
2420 @return R9 Unsigned 64-bit integer denoting the number of\r
2421 bytes of main memory needed to perform the second\r
2422 phase of processor self-test.\r
2423 @return R10 Unsigned 64-bit integer denoting the alignment\r
2424 required for the memory buffer.\r
2425 @return R11 48-bit wide bit-field indicating if control of\r
2426 the processor self-tests is supported and which\r
2427 bits of the test_control field are defined for\r
2428 use.\r
2429\r
2430**/\r
2431#define PAL_TEST_INFO 37\r
2432\r
2433/**\r
2434\r
2435 @param BufferSize Indicates the size in bytes of the memory\r
2436 buffer that is passed to this procedure.\r
2437 BufferSize must be greater than or equal in\r
2438 size to the bytes_needed return value from\r
2439 PAL_TEST_INFO, otherwise this procedure will\r
2440 return with an invalid argument return\r
2441 value.\r
2442\r
2443 @param TestPhase Defines which phase of the processor\r
2444 self-tests are requested to be run. A value\r
2445 of zero indicates to run phase two of the\r
2446 processor self-tests. Phase two of the\r
2447 processor self-tests are ones that require\r
2448 external memory to execute correctly. A\r
2449 value of one indicates to run phase one of\r
2450 the processor self-tests. Phase one of the\r
2451 processor self-tests are tests run during\r
2452 PALE_RESET and do not depend on external\r
2453 memory to run correctly. When the caller\r
2454 requests to have phase one of the processor\r
2455 self-test run via this procedure call, a\r
2456 memory buffer may be needed to save and\r
2457 restore state as required by the PAL calling\r
2458 conventions. The procedure PAL_TEST_INFO\r
2459 informs the caller about the requirements of\r
2460 the memory buffer.\r
2461\r
2462**/\r
2463typedef struct {\r
2464 UINT64 BufferSize:56;\r
2465 UINT64 TestPhase:8;\r
2466} PAL_TEST_INFO_INFO;\r
2467\r
2468/**\r
2469\r
2470 @param TestControl This is an ordered implementation-specific\r
2471 control word that allows the user control\r
2472 over the length and runtime of the\r
2473 processor self-tests. This control word is\r
2474 ordered from the longest running tests up\r
2475 to the shortest running tests with bit 0\r
2476 controlling the longest running test. PAL\r
2477 may not implement all 47-bits of the\r
2478 test_control word. PAL communicates if a\r
2479 bit provides control by placing a zero in\r
2480 that bit. If a bit provides no control,\r
2481 PAL will place a one in it. PAL will have\r
2482 two sets of test_control bits for the two\r
2483 phases of the processor self-test. PAL\r
2484 provides information about implemented\r
2485 test_control bits at the hand-off from PAL\r
2486 to SAL for the firmware recovery check.\r
2487 These test_control bits provide control\r
2488 for phase one of processor self-test. It\r
2489 also provides this information via the PAL\r
2490 procedure call PAL_TEST_INFO for both the\r
2491 phase one and phase two processor tests\r
2492 depending on which information the caller\r
2493 is requesting. PAL interprets these bits\r
2494 as input parameters on two occasions. The\r
2495 first time is when SAL passes control back\r
2496 to PAL after the firmware recovery check.\r
2497 The second time is when a call to\r
2498 PAL_TEST_PROC is made. When PAL interprets\r
2499 these bits it will only interpret\r
2500 implemented test_control bits and will\r
2501 ignore the values located in the\r
2502 unimplemented test_control bits. PAL\r
2503 interprets the implemented bits such that\r
2504 if a bit contains a zero, this indicates\r
2505 to run the test. If a bit contains a one,\r
2506 this indicates to PAL to skip the test. If\r
2507 the cs bit indicates that control is not\r
2508 available, the test_control bits will be\r
2509 ignored or generate an illegal argument in\r
2510 procedure calls if the caller sets these\r
2511 bits.\r
2512\r
2513 @param ControlSupport This bit defines if an implementation\r
2514 supports control of the PAL self-tests\r
2515 via the self-test control word. If\r
2516 this bit is 0, the implementation does\r
2517 not support control of the processor\r
2518 self-tests via the self-test control\r
2519 word. If this bit is 1, the\r
2520 implementation does support control of\r
2521 the processor self-tests via the\r
2522 self-test control word. If control is\r
2523 not supported, GR37 will be ignored at\r
2524 the hand-off between SAL and PAL after\r
2525 the firmware recovery check and the\r
2526 PAL procedures related to the\r
2527 processor self-tests may return\r
2528 illegal arguments if a user tries to\r
2529 use the self-test control features.\r
2530\r
2531**/\r
2532typedef struct {\r
2533 UINT64 TestControl:47;\r
2534 UINT64 ControlSupport:1;\r
2535 UINT64 Reserved:16;\r
2536} PAL_SELF_TEST_CONTROL;\r
2537\r
2538/**\r
2539\r
2540 @param Attributes Specifies the memory attributes that are\r
2541 allowed to be used with the memory buffer\r
2542 passed to this procedure. The attributes\r
2543 parameter is a vector where each bit\r
2544 represents one of the virtual memory\r
2545 attributes defined by the architecture.See\r
2546 MEMORY_AATRIBUTES. The caller is required\r
2547 to support the cacheable attribute for the\r
2548 memory buffer, otherwise an invalid\r
2549 argument will be returned.\r
2550\r
2551\r
2552 @param TestControl Is the self-test control word\r
2553 corresponding to the test_phase passed.\r
2554 This test_control directs the coverage and\r
2555 runtime of the processor self-tests\r
2556 specified by the test_phase input\r
2557 argument. Information on if this\r
2558 feature is implemented and the number of\r
2559 bits supported can be obtained by the\r
2560 PAL_TEST_INFO procedure call. If this\r
2561 feature is implemented by the processor,\r
2562 the caller can selectively skip parts of\r
2563 the processor self-test by setting\r
2564 test_control bits to a one. If a bit has a\r
2565 zero, this test will be run. The values in\r
2566 the unimplemented bits are ignored. If\r
2567 PAL_TEST_INFO indicated that the self-test\r
2568 control word is not implemented, this\r
2569 procedure will return with an invalid\r
2570 argument status if the caller sets any of\r
2571 the test_control bits. See\r
2572 PAL_SELF_TEST_CONTROL.\r
2573**/\r
2574typedef struct {\r
2575 UINT64 Attributes:8;\r
2576 UINT64 Reserved:8;\r
2577 UINT64 TestControl:48;\r
2578} PAL_TEST_CONTROL;\r
2579\r
2580/**\r
2581 PAL Procedure - PAL_TEST_PROC.\r
2582\r
2583 Perform late processor self test. It is required by IPF. The\r
2584 PAL procedure supports the Static Registers calling\r
2585 convention. It could be called at physical mode.\r
2586\r
2587 @param Index Index of PAL_TEST_PROC within the list of PAL\r
2588 procedures.\r
2589 @param TestAddress 64-bit physical address of main memory\r
2590 area to be used by processor self-test.\r
2591 The memory region passed must be\r
2592 cacheable, bit 63 must be zero.\r
2593 @param TestInfo Input argument specifying the size of the\r
2594 memory buffer passed and the phase of the\r
2595 processor self-test that should be run. See\r
2596 PAL_TEST_INFO.\r
2597 @param TestParam Input argument specifying the self-test\r
2598 control word and the allowable memory\r
2599 attributes that can be used with the memory\r
2600 buffer. See PAL_TEST_CONTROL.\r
2601\r
2602 @retval 1 Call completed without error, but hardware\r
2603 failures occurred during self-test.\r
2604 @retval 0 Call completed without error\r
2605 @retval -2 Invalid argument\r
2606 @retval -3 Call completed with error.\r
2607\r
2608 @return R9 Formatted 8-byte value denoting the state of the\r
2609 processor after self-test\r
2610\r
2611**/\r
2612#define PAL_TEST_PROC 258\r
2613\r
2614/**\r
2615\r
2616 @param NumberOfInterruptControllers Number of interrupt\r
2617 controllers currently\r
2618 enabled on the system.\r
2619\r
2620 @param NumberOfProcessors Number of processors currently\r
2621 enabled on the system.\r
2622\r
2623**/\r
2624typedef struct {\r
2625 UINT32 NumberOfInterruptControllers;\r
2626 UINT32 NumberOfProcessors;\r
2627} PAL_PLATFORM_INFO;\r
2628\r
2629/**\r
2630 PAL Procedure - PAL_COPY_INFO.\r
2631\r
2632 Return information needed to relocate PAL procedures and PAL\r
2633 PMI code to memory. It is required by IPF. The PAL procedure\r
2634 supports the Static Registers calling convention. It could be\r
2635 called at physical mode.\r
2636\r
2637 @param Index Index of PAL_COPY_INFO within the list of PAL\r
2638 procedures.\r
2639 @param CopyType Unsigned integer denoting type of procedures\r
2640 for which copy information is requested.\r
2641 @param PlatformInfo 8-byte formatted value describing the\r
2642 number of processors and the number of\r
2643 interrupt controllers currently enabled\r
2644 on the system. See PAL_PLATFORM_INFO.\r
2645 @param McaProcStateInfo Unsigned integer denoting the number\r
2646 of bytes that SAL needs for the\r
2647 min-state save area for each\r
2648 processor.\r
2649\r
2650 @retval 0 Call completed without error\r
2651 @retval -2 Invalid argument\r
2652 @retval -3 Call completed with error.\r
2653\r
2654 @return R9 Unsigned integer denoting the number of bytes of\r
2655 PAL information that must be copied to main\r
2656 memory.\r
2657 @return R10 Unsigned integer denoting the starting alignment\r
2658 of the data to be copied.\r
2659\r
2660**/\r
2661#define PAL_COPY_INFO 30\r
2662\r
2663/**\r
2664 PAL Procedure - PAL_COPY_PAL.\r
2665\r
2666 Relocate PAL procedures and PAL PMI code to memory. It is\r
2667 required by IPF. The PAL procedure supports the Stacked\r
2668 Registers calling convention. It could be called at physical\r
2669 mode.\r
2670\r
2671 @param Index Index of PAL_COPY_PAL within the list of PAL\r
2672 procedures.\r
2673 @param TargetAddress Physical address of a memory buffer to\r
2674 copy relocatable PAL procedures and PAL\r
2675 PMI code.\r
2676 @param AllocSize Unsigned integer denoting the size of the\r
2677 buffer passed by SAL for the copy operation.\r
2678 @param CopyOption Unsigned integer indicating whether\r
2679 relocatable PAL code and PAL PMI code\r
2680 should be copied from firmware address\r
2681 space to main memory.\r
2682\r
2683 @retval 0 Call completed without error\r
2684 @retval -2 Invalid argument\r
2685 @retval -3 Call completed with error.\r
2686\r
2687 @return R9 Unsigned integer denoting the offset of PAL_PROC\r
2688 in the relocatable segment copied.\r
2689\r
2690**/\r
2691#define PAL_COPY_PAL 256\r
2692\r
2693/**\r
2694 PAL Procedure - PAL_ENTER_IA_32_ENV.\r
2695\r
2696 Enter IA-32 System environment. It is optional. The PAL\r
2697 procedure supports the Static Registers calling convention.\r
2698 It could be called at physical mode.\r
2699\r
2700 Note: Since this is a special call, it does not follow the PAL\r
2701 static register calling convention. GR28 contains the index of\r
2702 PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r
2703 input arguments including GR29-GR31 are setup by SAL to values\r
2704 as required by the IA-32 operating system defined in Table\r
2705 11-67. The registers that are designated as preserved, scratch,\r
2706 input arguments and procedure return values by the static\r
2707 procedure calling convention are not followed by this call. For\r
2708 instance, GR5 and GR6 need not be preserved since these are\r
2709 regarded as scratch by the IA-32 operating system. Note: In an\r
2710 MP system, this call must be COMPLETED on the first CPU to enter\r
2711 the IA-32 System Environment (may or may not be the BSP) prior\r
2712 to being called on the remaining processors in the MP system.\r
2713\r
2714 @param Index GR28 contains the index of the\r
2715 PAL_ENTER_IA_32_ENV call within the list of PAL\r
2716 procedures.\r
2717\r
2718\r
2719 @retval The status is returned in GR4.\r
2720 -1 - Un-implemented procedure 0 JMPE detected\r
2721 at privilege level\r
2722\r
2723 0 - 1 SAL allocated buffer for IA-32 System\r
2724 Environment operation is too small\r
2725\r
2726 2 - IA-32 Firmware Checksum Error\r
2727\r
2728 3 - SAL allocated buffer for IA-32 System\r
2729 Environment operation is not properly aligned\r
2730\r
2731 4 - Error in SAL MP Info Table\r
2732\r
2733 5 - Error in SAL Memory Descriptor Table\r
2734\r
2735 6 - Error in SAL System Table\r
2736\r
2737 7 - Inconsistent IA-32 state\r
2738\r
2739 8 - IA-32 Firmware Internal Error\r
2740\r
2741 9 - IA-32 Soft Reset (Note: remaining register\r
2742 state is undefined for this termination\r
2743 reason)\r
2744\r
2745 10 - Machine Check Error\r
2746\r
2747 11 - Error in SAL I/O Intercept Table\r
2748\r
2749 12 - Processor exit due to other processor in\r
2750 MP system terminating the IA32 system\r
2751 environment. (Note: remaining register state\r
2752 is undefined for this termination reason.)\r
2753\r
2754 13 - Itanium architecture-based state\r
2755 corruption by either SAL PMI handler or I/O\r
2756 Intercept callback function.\r
2757\r
2758\r
2759**/\r
2760#define PAL_ENTER_IA_32_ENV 33\r
2761\r
2762/**\r
2763 PAL Procedure - PAL_PMI_ENTRYPOINT.\r
2764\r
2765 Register PMI memory entrypoints with processor. It is required\r
2766 by IPF. The PAL procedure supports the Stacked Registers\r
2767 calling convention. It could be called at physical mode.\r
2768\r
2769 @param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
2770 PAL procedures.\r
2771 @param SalPmiEntry 256-byte aligned physical address of SAL\r
2772 PMI entrypoint in memory.\r
2773\r
2774 @retval 0 Call completed without error\r
2775 @retval -2 Invalid argument\r
2776 @retval -3 Call completed with error.\r
2777\r
2778**/\r
2779#define PAL_PMI_ENTRYPOINT 32\r
2780\r
2781\r
2782/**\r
2783\r
2784 The ASCII brand identification string will be copied to the\r
2785 address specified in the address input argument. The processor\r
2786 brand identification string is defined to be a maximum of 128\r
2787 characters long; 127 bytes will contain characters and the 128th\r
2788 byte is defined to be NULL (0). A processor may return less than\r
2789 the 127 ASCII characters as long as the string is null\r
2790 terminated. The string length will be placed in the brand_info\r
2791 return argument.\r
2792\r
2793**/\r
2794#define PAL_BRAND_INFO_ID_REQUEST 0\r
2795\r
2796/**\r
2797 PAL Procedure - PAL_BRAND_INFO.\r
2798\r
2799 Provides processor branding information. It is optional by\r
2800 IPF. The PAL procedure supports the Stacked Registers calling\r
2801 convention. It could be called at physical and Virtual mode.\r
2802\r
2803 @param Index Index of PAL_BRAND_INFO within the list of PAL\r
2804 procedures.\r
2805 @param InfoRequest Unsigned 64-bit integer specifying the\r
2806 information that is being requested. (See\r
2807 PAL_BRAND_INFO_ID_REQUEST)\r
2808 @param Address Unsigned 64-bit integer specifying the\r
2809 address of the 128-byte block to which the\r
2810 processor brand string shall be written.\r
2811\r
2812 @retval 0 Call completed without error\r
2813 @retval -1 Unimplemented procedure\r
2814 @retval -2 Invalid argument\r
2815 @retval -3 Call completed with error.\r
2816 @retval -6 Input argument is not implemented.\r
2817\r
2818 @return R9 Brand information returned. The format of this\r
2819 value is dependent on the input values passed.\r
2820\r
2821**/\r
2822#define PAL_BRAND_INFO 274\r
2823\r
2824/**\r
2825 PAL Procedure - PAL_GET_HW_POLICY.\r
2826\r
2827 Returns the current hardware resource sharing policy of the\r
2828 processor. It is optional by IPF. The PAL procedure supports\r
2829 the Static Registers calling convention. It could be called at\r
2830 physical and Virtual mode.\r
2831\r
2832\r
2833 @param Index Index of PAL_GET_HW_POLICY within the list of PAL\r
2834 procedures.\r
2835 @param ProcessorNumber Unsigned 64-bit integer that specifies\r
2836 for which logical processor\r
2837 information is being requested. This\r
2838 input argument must be zero for the\r
2839 first call to this procedure and can\r
2840 be a maximum value of one less than\r
2841 the number of logical processors\r
2842 impacted by the hardware resource\r
2843 sharing policy, which is returned by\r
2844 the R10 return value.\r
2845\r
2846 @retval 0 Call completed without error\r
2847 @retval -1 Unimplemented procedure\r
2848 @retval -2 Invalid argument\r
2849 @retval -3 Call completed with error.\r
2850 @retval -9 Call requires PAL memory buffer.\r
2851\r
2852 @return R9 Unsigned 64-bit integer representing the current\r
2853 hardware resource sharing policy.\r
2854 @return R10 Unsigned 64-bit integer that returns the number\r
2855 of logical processors impacted by the policy\r
2856 input argument.\r
2857 @return R11 Unsigned 64-bit integer containing the logical\r
2858 address of one of the logical processors\r
2859 impacted by policy modification.\r
2860\r
2861**/\r
2862#define PAL_GET_HW_POLICY 48\r
2863\r
2864\r
2865//\r
2866// Value of PAL_SET_HW_POLICY.Policy\r
2867//\r
2868#define PAL_SET_HW_POLICY_PERFORMANCE 0\r
2869#define PAL_SET_HW_POLICY_FAIRNESS 1\r
2870#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r
2871#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r
2872\r
2873/**\r
2874 PAL Procedure - PAL_SET_HW_POLICY.\r
2875\r
2876 Sets the current hardware resource sharing policy of the\r
2877 processor. It is optional by IPF. The PAL procedure supports\r
2878 the Static Registers calling convention. It could be called at\r
2879 physical and Virtual mode.\r
2880\r
2881 @param Index Index of PAL_SET_HW_POLICY within the list of PAL\r
2882 procedures.\r
2883 @param Policy Unsigned 64-bit integer specifying the hardware\r
2884 resource sharing policy the caller is setting.\r
2885 See Value of PAL_SET_HW_POLICY.Policy above.\r
2886\r
2887 @retval 1 Call completed successfully but could not\r
2888 change the hardware policy since a\r
2889 competing logical processor is set in\r
2890 exclusive high priority.\r
2891 @retval 0 Call completed without error\r
2892 @retval -1 Unimplemented procedure\r
2893 @retval -2 Invalid argument\r
2894 @retval -3 Call completed with error.\r
2895 @retval -9 Call requires PAL memory buffer.\r
2896\r
2897**/\r
2898#define PAL_SET_HW_POLICY 49\r
2899\r
2900\r
2901/**\r
2902\r
2903 @param Mode Bit2:0, Indicates the mode of operation for this\r
2904 procedure: 0 - Query mode 1 - Error inject mode\r
2905 (err_inj should also be specified) 2 - Cancel\r
2906 outstanding trigger. All other fields in\r
2907 PAL_MC_ERROR_TYPE_INFO,\r
2908 PAL_MC_ERROR_STRUCTURE_INFO and\r
2909 PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r
2910 values are reserved.\r
2911\r
2912 @param ErrorInjection Bit5:3, indicates the mode of error\r
2913 injection: 0 - Error inject only (no\r
2914 error consumption) 1 - Error inject\r
2915 and consume All other values are\r
2916 reserved.\r
2917\r
2918\r
2919 @param ErrorSeverity Bit7:6, indicates the severity desired\r
2920 for error injection/query. Definitions\r
2921 of the different error severity types\r
2922 0 - Corrected error 1 - Recoverable\r
2923 error 2 - Fatal error 3 - Reserved\r
2924\r
2925\r
2926 @param ErrorStructure Bit12:8, Indicates the structure\r
2927 identification for error\r
2928 injection/query: 0 - Any structure\r
2929 (cannot be used during query mode).\r
2930 When selected, the structure type used\r
2931 for error injection is determined by\r
2932 PAL. 1 - Cache 2 - TLB 3 - Register\r
2933 file 4 - Bus/System interconnect 5-15\r
2934 - Reserved 16-31 - Processor\r
2935 specific error injection\r
2936 capabilities.ErrorDataBuffer is used\r
2937 to specify error types. Please refer\r
2938 to the processor specific\r
2939 documentation for additional details.\r
2940\r
2941 @param StructureHierarchy Bit15:13, Indicates the structure\r
2942 hierarchy for error\r
2943 injection/query: 0 - Any level of\r
2944 hierarchy (cannot be used during\r
2945 query mode). When selected, the\r
2946 structure hierarchy used for error\r
2947 injection is determined by PAL. 1\r
2948 - Error structure hierarchy\r
2949 level-1 2 - Error structure\r
2950 hierarchy level-2 3 - Error\r
2951 structure hierarchy level-3 4 -\r
2952 Error structure hierarchy level-4\r
2953 All other values are reserved.\r
2954 Reserved 63:16 Reserved\r
2955\r
2956**/\r
2957typedef struct {\r
2958 UINT64 Mode:3;\r
2959 UINT64 ErrorInjection:3;\r
2960 UINT64 ErrorSeverity:2;\r
2961 UINT64 ErrorStructure:5;\r
2962 UINT64 StructureHierarchy:3;\r
2963 UINT64 Reserved:48;\r
2964} PAL_MC_ERROR_TYPE_INFO;\r
2965\r
2966/**\r
2967\r
2968 @param StructInfoIsValid Bit0 When 1, indicates that the\r
2969 structure information fields\r
2970 (c_t,cl_p,cl_id) are valid and\r
2971 should be used for error injection.\r
2972 When 0, the structure information\r
2973 fields are ignored, and the values\r
2974 of these fields used for error\r
2975 injection are\r
2976 implementation-specific.\r
2977\r
2978 @param CacheType Bit2:1 Indicates which cache should be used\r
2979 for error injection: 0 - Reserved 1 -\r
2980 Instruction cache 2 - Data or unified cache\r
2981 3 - Reserved\r
2982\r
2983\r
2984 @param PortionOfCacheLine Bit5:3 Indicates the portion of the\r
2985 cache line where the error should\r
2986 be injected: 0 - Reserved 1 - Tag\r
2987 2 - Data 3 - mesi All other\r
2988 values are reserved.\r
2989\r
2990 @param Mechanism Bit8:6 Indicates which mechanism is used to\r
2991 identify the cache line to be used for error\r
2992 injection: 0 - Reserved 1 - Virtual address\r
2993 provided in the inj_addr field of the buffer\r
2994 pointed to by err_data_buffer should be used\r
2995 to identify the cache line for error\r
2996 injection. 2 - Physical address provided in\r
2997 the inj_addr field of the buffer pointed to\r
2998 by err_data_buffershould be used to identify\r
2999 the cache line for error injection. 3 - way\r
3000 and index fields provided in err_data_buffer\r
3001 should be used to identify the cache line\r
3002 for error injection. All other values are\r
3003 reserved.\r
3004\r
3005 @param DataPoisonOfCacheLine Bit9 When 1, indicates that a\r
3006 multiple bit, non-correctable\r
3007 error should be injected in the\r
3008 cache line specified by cl_id.\r
3009 If this injected error is not\r
3010 consumed, it may eventually\r
3011 cause a data-poisoning event\r
3012 resulting in a corrected error\r
3013 signal, when the associated\r
3014 cache line is cast out (implicit\r
3015 or explicit write-back of the\r
3016 cache line). The error severity\r
3017 specified by err_sev in\r
3018 err_type_info must be set to 0\r
3019 (corrected error) when this bit\r
3020 is set.\r
3021\r
3022\r
3023 @param TrigerInfoIsValid Bit32 When 1, indicates that the\r
3024 trigger information fields (trigger,\r
3025 trigger_pl) are valid and should be\r
3026 used for error injection. When 0,\r
3027 the trigger information fields are\r
3028 ignored and error injection is\r
3029 performed immediately.\r
3030\r
3031 @param Triger Bit36:33 Indicates the operation type to be\r
3032 used as the error trigger condition. The\r
3033 address corresponding to the trigger is\r
3034 specified in the trigger_addr field of the\r
3035 buffer pointed to by err_data_buffer: 0 -\r
3036 Instruction memory access. The trigger match\r
3037 conditions for this operation type are similar\r
3038 to the IBR address breakpoint match conditions\r
3039 1 - Data memory access. The trigger match\r
3040 conditions for this operation type are similar\r
3041 to the DBR address breakpoint match conditions\r
3042 All other values are reserved.\r
3043\r
3044 @param PrivilegeOfTriger Bit39:37 Indicates the privilege\r
3045 level of the context during which\r
3046 the error should be injected: 0 -\r
3047 privilege level 0 1 - privilege\r
3048 level 1 2 - privilege level 2 3 -\r
3049 privilege level 3 All other values\r
3050 are reserved. If the implementation\r
3051 does not support privilege level\r
3052 qualifier for triggers (i.e. if\r
3053 trigger_pl is 0 in the capabilities\r
3054 vector), this field is ignored and\r
3055 triggers can be taken at any\r
3056 privilege level.\r
3057\r
3058**/\r
3059typedef struct {\r
3060 UINT64 StructInfoIsValid:1;\r
3061 UINT64 CacheType:2;\r
3062 UINT64 PortionOfCacheLine:3;\r
3063 UINT64 Mechanism:3;\r
3064 UINT64 DataPoisonOfCacheLine:1;\r
3065 UINT64 Reserved1:22;\r
3066 UINT64 TrigerInfoIsValid:1;\r
3067 UINT64 Triger:4;\r
3068 UINT64 PrivilegeOfTriger:3;\r
3069 UINT64 Reserved2:24;\r
3070} PAL_MC_ERROR_STRUCT_INFO;\r
3071\r
3072/**\r
3073\r
3074 Buffer Pointed to by err_data_buffer - TLB\r
3075\r
3076**/\r
3077typedef struct {\r
3078 UINT64 TrigerAddress;\r
3079 UINT64 VirtualPageNumber:52;\r
3080 UINT64 Reserved1:8;\r
3081 UINT64 RegionId:24;\r
3082 UINT64 Reserved2:40;\r
3083} PAL_MC_ERROR_DATA_BUFFER_TLB;\r
3084\r
3085/**\r
3086 PAL Procedure - PAL_MC_ERROR_INJECT.\r
3087\r
3088 Injects the requested processor error or returns information\r
3089 on the supported injection capabilities for this particular\r
3090 processor implementation. It is optional by IPF. The PAL\r
3091 procedure supports the Stacked Registers calling convention.\r
3092 It could be called at physical and Virtual mode.\r
3093\r
3094 @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r
3095 procedures.\r
3096 @param ErrorTypeInfo Unsigned 64-bit integer specifying the\r
3097 first level error information which\r
3098 identifies the error structure and\r
3099 corresponding structure hierarchy, and\r
3100 the error severity.\r
3101 @param ErrorStructInfo Unsigned 64-bit integer identifying\r
3102 the optional structure specific\r
3103 information that provides the second\r
3104 level details for the requested error.\r
3105 @param ErrorDataBuffer 64-bit physical address of a buffer\r
3106 providing additional parameters for\r
3107 the requested error. The address of\r
3108 this buffer must be 8-byte aligned.\r
3109\r
3110 @retval 0 Call completed without error\r
3111 @retval -1 Unimplemented procedure\r
3112 @retval -2 Invalid argument\r
3113 @retval -3 Call completed with error.\r
3114 @retval -4 Call completed with error; the requested\r
3115 error could not be injected due to failure in\r
3116 locating the target location in the specified\r
3117 structure.\r
3118 @retval -5 Argument was valid, but requested error\r
3119 injection capability is not supported.\r
3120 @retval -9 Call requires PAL memory buffer.\r
3121\r
3122 @return R9 64-bit vector specifying the supported error\r
3123 injection capabilities for the input argument\r
3124 combination of struct_hier, err_struct and\r
3125 err_sev fields in ErrorTypeInfo.\r
3126 @return R10 64-bit vector specifying the architectural\r
3127 resources that are used by the procedure.\r
3128\r
3129**/\r
3130#define PAL_MC_ERROR_INJECT 276\r
3131\r
3132\r
3133//\r
3134// Types of PAL_GET_PSTATE.Type\r
3135//\r
3136#define PAL_GET_PSTATE_RECENT 0\r
3137#define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r
3138#define PAL_GET_PSTATE_AVERAGE 2\r
3139#define PAL_GET_PSTATE_NOW 3\r
3140\r
3141/**\r
3142 PAL Procedure - PAL_GET_PSTATE.\r
3143\r
3144 Returns the performance index of the processor. It is optional\r
3145 by IPF. The PAL procedure supports the Stacked Registers\r
3146 calling convention. It could be called at physical and Virtual\r
3147 mode.\r
3148\r
3149 @param Index Index of PAL_GET_PSTATE within the list of PAL\r
3150 procedures.\r
3151 @param Type Type of performance_index value to be returned\r
3152 by this procedure.See PAL_GET_PSTATE.Type above.\r
3153\r
3154 @retval 1 Call completed without error, but accuracy\r
3155 of performance index has been impacted by a\r
3156 thermal throttling event, or a\r
3157 hardware-initiated event.\r
3158 @retval 0 Call completed without error\r
3159 @retval -1 Unimplemented procedure\r
3160 @retval -2 Invalid argument\r
3161 @retval -3 Call completed with error.\r
3162 @retval -9 Call requires PAL memory buffer.\r
3163\r
3164 @return R9 Unsigned integer denoting the processor\r
3165 performance for the time duration since the last\r
3166 PAL_GET_PSTATE procedure call was made. The\r
3167 value returned is between 0 and 100, and is\r
3168 relative to the performance index of the highest\r
3169 available P-state.\r
3170\r
3171**/\r
3172#define PAL_GET_PSTATE 262\r
3173\r
3174/**\r
3175\r
3176 Layout of PAL_PSTATE_INFO.PStateBuffer\r
3177\r
3178**/\r
3179typedef struct {\r
3180 UINT32 PerformanceIndex:7;\r
3181 UINT32 Reserved1:5;\r
3182 UINT32 TypicalPowerDissipation:20;\r
3183 UINT32 TransitionLatency1;\r
3184 UINT32 TransitionLatency2;\r
3185 UINT32 Reserved2;\r
3186} PAL_PSTATE_INFO_BUFFER;\r
3187\r
3188\r
3189/**\r
3190 PAL Procedure - PAL_PSTATE_INFO.\r
3191\r
3192 Returns information about the P-states supported by the\r
3193 processor. It is optional by IPF. The PAL procedure supports\r
3194 the Static Registers calling convention. It could be called\r
3195 at physical and Virtual mode.\r
3196\r
3197 @param Index Index of PAL_PSTATE_INFO within the list of PAL\r
3198 procedures.\r
3199 @param PStateBuffer 64-bit pointer to a 256-byte buffer\r
3200 aligned on an 8-byte boundary. See\r
3201 PAL_PSTATE_INFO_BUFFER above.\r
3202\r
3203 @retval 0 Call completed without error\r
3204 @retval -1 Unimplemented procedure\r
3205 @retval -2 Invalid argument\r
3206 @retval -3 Call completed with error.\r
3207\r
3208 @return R9 Unsigned integer denoting the number of P-states\r
3209 supported. The maximum value of this field is 16.\r
3210 @return R10 Dependency domain information\r
3211\r
3212**/\r
3213#define PAL_PSTATE_INFO 44\r
3214\r
3215\r
3216/**\r
3217 PAL Procedure - PAL_SET_PSTATE.\r
3218\r
3219 To request a processor transition to a given P-state. It is\r
3220 optional by IPF. The PAL procedure supports the Stacked\r
3221 Registers calling convention. It could be called at physical\r
3222 and Virtual mode.\r
3223\r
3224 @param Index Index of PAL_SET_PSTATE within the list of PAL\r
3225 procedures.\r
3226 @param PState Unsigned integer denoting the processor\r
3227 P-state being requested.\r
3228 @param ForcePState Unsigned integer denoting whether the\r
3229 P-state change should be forced for the\r
3230 logical processor.\r
3231\r
3232 @retval 1 Call completed without error, but\r
3233 transition request was not accepted\r
3234 @retval 0 Call completed without error\r
3235 @retval -1 Unimplemented procedure\r
3236 @retval -2 Invalid argument\r
3237 @retval -3 Call completed with error.\r
3238 @retval -9 Call requires PAL memory buffer.\r
3239\r
3240**/\r
3241#define PAL_SET_PSTATE 263\r
3242\r
3243/**\r
3244 PAL Procedure - PAL_SHUTDOWN.\r
3245\r
3246 Put the logical processor into a low power state which can be\r
3247 exited only by a reset event. It is optional by IPF. The PAL\r
3248 procedure supports the Static Registers calling convention. It\r
3249 could be called at physical mode.\r
3250\r
3251 @param Index Index of PAL_SHUTDOWN within the list of PAL\r
3252 procedures.\r
3253 @param NotifyPlatform 8-byte aligned physical address\r
3254 pointer providing details on how to\r
3255 optionally notify the platform that\r
3256 the processor is entering a shutdown\r
3257 state.\r
3258\r
3259 @retval -1 Unimplemented procedure\r
3260 @retval -2 Invalid argument\r
3261 @retval -3 Call completed with error.\r
3262 @retval -9 Call requires PAL memory buffer.\r
3263\r
3264**/\r
3265#define PAL_SHUTDOWN 45\r
3266\r
3267/**\r
3268\r
3269 Layout of PAL_MEMORY_BUFFER.ControlWord\r
3270\r
3271**/\r
3272typedef struct {\r
3273 UINT64 Registration:1;\r
3274 UINT64 ProbeInterrupt:1;\r
3275 UINT64 Reserved:62;\r
3276} PAL_MEMORY_CONTROL_WORD;\r
3277\r
3278/**\r
3279 PAL Procedure - PAL_MEMORY_BUFFER.\r
3280\r
3281 Provides cacheable memory to PAL for exclusive use during\r
3282 runtime. It is optional by IPF. The PAL procedure supports the\r
3283 Static Registers calling convention. It could be called at\r
3284 physical mode.\r
3285\r
3286 @param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r
3287 procedures.\r
3288 @param BaseAddress Physical address of the memory buffer\r
3289 allocated for PAL use.\r
3290 @param AllocSize Unsigned integer denoting the size of the\r
3291 memory buffer.\r
3292 @param ControlWord Formatted bit vector that provides control\r
3293 options for this procedure. See\r
3294 PAL_MEMORY_CONTROL_WORD above.\r
3295\r
3296 @retval 1 Call has not completed a buffer relocation\r
3297 due to a pending interrupt\r
3298 @retval 0 Call completed without error\r
3299 @retval -1 Unimplemented procedure\r
3300 @retval -2 Invalid argument\r
3301 @retval -3 Call completed with error.\r
3302 @retval -9 Call requires PAL memory buffer.\r
3303\r
3304 @return R9 Returns the minimum size of the memory buffer\r
3305 required if the alloc_size input argument was\r
3306 not large enough.\r
3307\r
3308**/\r
3309#define PAL_MEMORY_BUFFER 277\r
3310\r
3311\r
3312/**\r
3313 PAL Procedure - PAL_VP_CREATE.\r
3314\r
3315 Initializes a new vpd for the operation of a new virtual\r
3316 processor in the virtual environment. It is optional by IPF.\r
3317 The PAL procedure supports the Stacked Registers calling\r
3318 convention. It could be called at Virtual mode.\r
3319\r
3320 @param Index Index of PAL_VP_CREATE within the list of PAL\r
3321 procedures.\r
3322 @param Vpd 64-bit host virtual pointer to the Virtual\r
3323 Processor Descriptor (VPD).\r
3324 @param HostIva 64-bit host virtual pointer to the host IVT\r
3325 for the virtual processor\r
3326 @param OptionalHandler 64-bit non-zero host-virtual pointer\r
3327 to an optional handler for\r
3328 virtualization intercepts.\r
3329\r
3330 @retval 0 Call completed without error\r
3331 @retval -1 Unimplemented procedure\r
3332 @retval -2 Invalid argument\r
3333 @retval -3 Call completed with error.\r
3334 @retval -9 Call requires PAL memory buffer.\r
3335\r
3336**/\r
3337#define PAL_VP_CREATE 265\r
3338\r
3339/**\r
3340\r
3341 Virtual Environment Information Parameter\r
3342\r
3343**/\r
3344typedef struct {\r
3345 UINT64 Reserved1:8;\r
3346 UINT64 Opcode:1;\r
3347 UINT64 Reserved:53;\r
3348} PAL_VP_ENV_INFO_RETURN;\r
3349\r
3350/**\r
3351 PAL Procedure - PAL_VP_ENV_INFO.\r
3352\r
3353 Returns the parameters needed to enter a virtual environment.\r
3354 It is optional by IPF. The PAL procedure supports the Stacked\r
3355 Registers calling convention. It could be called at Virtual\r
3356 mode.\r
3357\r
3358 @param Index Index of PAL_VP_ENV_INFO within the list of PAL\r
3359 procedures.\r
3360 @param Vpd 64-bit host virtual pointer to the Virtual\r
3361 Processor Descriptor (VPD).\r
3362 @param HostIva 64-bit host virtual pointer to the host IVT\r
3363 for the virtual processor\r
3364 @param OptionalHandler 64-bit non-zero host-virtual pointer\r
3365 to an optional handler for\r
3366 virtualization intercepts.\r
3367\r
3368 @retval 0 Call completed without error\r
3369 @retval -1 Unimplemented procedure\r
3370 @retval -2 Invalid argument\r
3371 @retval -3 Call completed with error.\r
3372 @retval -9 Call requires PAL memory buffer.\r
3373\r
3374 @return R9 Unsigned integer denoting the number of bytes\r
3375 required by the PAL virtual environment buffer\r
3376 during PAL_VP_INIT_ENV\r
3377 @return R10 64-bit vector of virtual environment\r
3378 information. See PAL_VP_ENV_INFO_RETURN.\r
3379\r
3380\r
3381**/\r
3382#define PAL_VP_ENV_INFO 266\r
3383\r
3384/**\r
3385 PAL Procedure - PAL_VP_EXIT_ENV.\r
3386\r
3387 Allows a logical processor to exit a virtual environment.\r
3388 It is optional by IPF. The PAL procedure supports the Stacked\r
3389 Registers calling convention. It could be called at Virtual\r
3390 mode.\r
3391\r
3392 @param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r
3393 procedures.\r
3394 @param Iva Optional 64-bit host virtual pointer to the IVT\r
3395 when this procedure is done\r
3396\r
3397 @retval 0 Call completed without error\r
3398 @retval -1 Unimplemented procedure\r
3399 @retval -2 Invalid argument\r
3400 @retval -3 Call completed with error.\r
3401 @retval -9 Call requires PAL memory buffer.\r
3402\r
3403**/\r
3404#define PAL_VP_EXIT_ENV 267\r
3405\r
3406\r
3407\r
3408/**\r
3409 PAL Procedure - PAL_VP_INIT_ENV.\r
3410\r
3411 Allows a logical processor to enter a virtual environment. It\r
3412 is optional by IPF. The PAL procedure supports the Stacked\r
3413 Registers calling convention. It could be called at Virtual\r
3414 mode.\r
3415\r
3416 @param Index Index of PAL_VP_INIT_ENV within the list of PAL\r
3417 procedures.\r
3418 @param ConfigOptions 64-bit vector of global configuration\r
3419 settings.\r
3420 @param PhysicalBase Host physical base address of a block of\r
3421 contiguous physical memory for the PAL\r
3422 virtual environment buffer 1) This\r
3423 memory area must be allocated by the VMM\r
3424 and be 4K aligned. The first logical\r
3425 processor to enter the environment will\r
3426 initialize the physical block for\r
3427 virtualization operations.\r
3428 @param VirtualBase Host virtual base address of the\r
3429 corresponding physical memory block for\r
3430 the PAL virtual environment buffer : The\r
3431 VMM must maintain the host virtual to host\r
3432 physical data and instruction translations\r
3433 in TRs for addresses within the allocated\r
3434 address space. Logical processors in this\r
3435 virtual environment will use this address\r
3436 when transitioning to virtual mode\r
3437 operations.\r
3438\r
3439 @retval 0 Call completed without error\r
3440 @retval -1 Unimplemented procedure\r
3441 @retval -2 Invalid argument\r
3442 @retval -3 Call completed with error.\r
3443 @retval -9 Call requires PAL memory buffer.\r
3444\r
3445 @return R9 Virtualization Service Address - VSA specifies\r
3446 the virtual base address of the PAL\r
3447 virtualization services in this virtual\r
3448 environment.\r
3449\r
3450\r
3451**/\r
3452#define PAL_VP_INIT_ENV 268\r
3453\r
3454\r
3455/**\r
3456 PAL Procedure - PAL_VP_REGISTER.\r
3457\r
3458 Register a different host IVT and/or a different optional\r
3459 virtualization intercept handler for the virtual processor\r
3460 specified by vpd. It is optional by IPF. The PAL procedure\r
3461 supports the Stacked Registers calling convention. It could be\r
3462 called at Virtual mode.\r
3463\r
3464 @param Index Index of PAL_VP_REGISTER within the list of PAL\r
3465 procedures.\r
3466 @param Vpd 64-bit host virtual pointer to the Virtual\r
3467 Processor Descriptor (VPD) host_iva 64-bit host\r
3468 virtual pointer to the host IVT for the virtual\r
3469 processor\r
3470 @param OptionalHandler 64-bit non-zero host-virtual pointer\r
3471 to an optional handler for\r
3472 virtualization intercepts.\r
3473\r
3474 @retval 0 Call completed without error\r
3475 @retval -1 Unimplemented procedure\r
3476 @retval -2 Invalid argument\r
3477 @retval -3 Call completed with error.\r
3478 @retval -9 Call requires PAL memory buffer.\r
3479\r
3480**/\r
3481#define PAL_VP_REGISTER 269\r
3482\r
3483\r
3484/**\r
3485 PAL Procedure - PAL_VP_RESTORE.\r
3486\r
3487 Restores virtual processor state for the specified vpd on the\r
3488 logical processor. It is optional by IPF. The PAL procedure\r
3489 supports the Stacked Registers calling convention. It could be\r
3490 called at Virtual mode.\r
3491\r
3492 @param Index Index of PAL_VP_RESTORE within the list of PAL\r
3493 procedures.\r
3494 @param Vpd 64-bit host virtual pointer to the Virtual\r
3495 Processor Descriptor (VPD) host_iva 64-bit host\r
3496 virtual pointer to the host IVT for the virtual\r
3497 processor\r
3498 @param PalVector Vector specifies PAL procedure\r
3499 implementation-specific state to be\r
3500 restored.\r
3501\r
3502 @retval 0 Call completed without error\r
3503 @retval -1 Unimplemented procedure\r
3504 @retval -2 Invalid argument\r
3505 @retval -3 Call completed with error.\r
3506 @retval -9 Call requires PAL memory buffer.\r
3507\r
3508**/\r
3509#define PAL_VP_RESTORE 270\r
3510\r
3511/**\r
3512 PAL Procedure - PAL_VP_SAVE.\r
3513\r
3514 Saves virtual processor state for the specified vpd on the\r
3515 logical processor. It is optional by IPF. The PAL procedure\r
3516 supports the Stacked Registers calling convention. It could be\r
3517 called at Virtual mode.\r
3518\r
3519 @param Index Index of PAL_VP_SAVE within the list of PAL\r
3520 procedures.\r
3521 @param Vpd 64-bit host virtual pointer to the Virtual\r
3522 Processor Descriptor (VPD) host_iva 64-bit host\r
3523 virtual pointer to the host IVT for the virtual\r
3524 processor\r
3525 @param PalVector Vector specifies PAL procedure\r
3526 implementation-specific state to be\r
3527 restored.\r
3528\r
3529 @retval 0 Call completed without error\r
3530 @retval -1 Unimplemented procedure\r
3531 @retval -2 Invalid argument\r
3532 @retval -3 Call completed with error.\r
3533 @retval -9 Call requires PAL memory buffer.\r
3534\r
3535**/\r
3536#define PAL_VP_SAVE 271\r
3537\r
3538\r
3539/**\r
3540 PAL Procedure - PAL_VP_TERMINATE.\r
3541\r
3542 Terminates operation for the specified virtual processor. It\r
3543 is optional by IPF. The PAL procedure supports the Stacked\r
3544 Registers calling convention. It could be called at Virtual\r
3545 mode.\r
3546\r
3547 @param Index Index of PAL_VP_TERMINATE within the list of PAL\r
3548 procedures.\r
3549 @param Vpd 64-bit host virtual pointer to the Virtual\r
3550 Processor Descriptor (VPD)\r
3551 @param Iva Optional 64-bit host virtual pointer to the IVT\r
3552 when this procedure is done.\r
3553\r
3554 @retval 0 Call completed without error\r
3555 @retval -1 Unimplemented procedure\r
3556 @retval -2 Invalid argument\r
3557 @retval -3 Call completed with error.\r
3558 @retval -9 Call requires PAL memory buffer.\r
3559\r
3560**/\r
3561#define PAL_VP_TERMINATE 272\r
3562\r
3563#endif\r
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