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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.3 standard.\r | |
3 | \r | |
9df063a0 HT |
4 | Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials \r | |
a7ed1e2e | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
af2dc6a7 | 8 | http://opensource.org/licenses/bsd-license.php. \r |
a7ed1e2e | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
a7ed1e2e | 13 | **/\r |
14 | \r | |
42eedea9 | 15 | #ifndef _PCI23_H_\r |
16 | #define _PCI23_H_\r | |
a7ed1e2e | 17 | \r |
bc14bdb3 | 18 | #include <IndustryStandard/Pci22.h>\r |
19 | \r | |
20 | ///\r | |
af2dc6a7 | 21 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r |
bc14bdb3 | 22 | ///\r |
179d85c8 | 23 | ///@{\r |
24 | #define PCI_CLASS_MASS_STORAGE_ATA 0x05\r | |
25 | #define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20\r | |
26 | #define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30\r | |
27 | ///@}\r | |
28 | \r | |
29 | ///\r | |
af2dc6a7 | 30 | /// PCI_CLASS_SERIAL, Base Class 0Ch.\r |
179d85c8 | 31 | ///\r |
32 | ///@{\r | |
33 | #define PCI_IF_EHCI 0x20\r | |
34 | #define PCI_CLASS_SERIAL_IB 0x06\r | |
35 | ///@}\r | |
a7ed1e2e | 36 | \r |
bc14bdb3 | 37 | ///\r |
38 | /// defined in PCI Express Spec.\r | |
39 | ///\r | |
a7ed1e2e | 40 | #define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r |
a7ed1e2e | 41 | \r |
a2461f6b | 42 | ///\r |
af2dc6a7 | 43 | /// PCI Capability List IDs and records.\r |
a2461f6b | 44 | ///\r |
bc14bdb3 | 45 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r |
46 | \r | |
766f4bc1 | 47 | #pragma pack(1)\r |
bc14bdb3 | 48 | ///\r |
427987f5 | 49 | /// PCI-X Capabilities List, \r |
af2dc6a7 | 50 | /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r |
bc14bdb3 | 51 | ///\r |
52 | typedef struct {\r | |
53 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
54 | UINT16 CommandReg;\r | |
55 | UINT32 StatusReg;\r | |
56 | } EFI_PCI_CAPABILITY_PCIX;\r | |
57 | \r | |
427987f5 | 58 | ///\r |
59 | /// PCI-X Bridge Capabilities List, \r | |
af2dc6a7 | 60 | /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r |
bc14bdb3 | 61 | ///\r |
62 | typedef struct {\r | |
63 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
64 | UINT16 SecStatusReg;\r | |
65 | UINT32 StatusReg;\r | |
66 | UINT32 SplitTransCtrlRegUp;\r | |
67 | UINT32 SplitTransCtrlRegDn;\r | |
68 | } EFI_PCI_CAPABILITY_PCIX_BRDG;\r | |
69 | \r | |
766f4bc1 | 70 | #pragma pack()\r |
71 | \r | |
bc14bdb3 | 72 | #define PCI_CODE_TYPE_EFI_IMAGE 0x03\r |
a7ed1e2e | 73 | \r |
74 | #endif\r |