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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.3 standard.\r | |
3 | \r | |
bc14bdb3 | 4 | Copyright (c) 2006 - 2008, Intel Corporation \r |
a7ed1e2e | 5 | All rights reserved. This program and the accompanying materials \r |
6 | are licensed and made available under the terms and conditions of the BSD License \r | |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
a7ed1e2e | 13 | **/\r |
14 | \r | |
42eedea9 | 15 | #ifndef _PCI23_H_\r |
16 | #define _PCI23_H_\r | |
a7ed1e2e | 17 | \r |
bc14bdb3 | 18 | #include <IndustryStandard/Pci22.h>\r |
19 | \r | |
20 | ///\r | |
21 | /// Definitions of PCI class bytes and manipulation macros.\r | |
22 | ///\r | |
23 | #define PCI_IF_EHCI 0x20\r | |
a7ed1e2e | 24 | \r |
bc14bdb3 | 25 | ///\r |
26 | /// defined in PCI Express Spec.\r | |
27 | ///\r | |
a7ed1e2e | 28 | #define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r |
a7ed1e2e | 29 | \r |
a2461f6b | 30 | ///\r |
31 | /// PCI Capability List IDs and records\r | |
32 | ///\r | |
bc14bdb3 | 33 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07\r |
34 | \r | |
766f4bc1 | 35 | #pragma pack(1)\r |
bc14bdb3 | 36 | ///\r |
427987f5 | 37 | /// PCI-X Capabilities List, \r |
38 | /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b\r | |
bc14bdb3 | 39 | ///\r |
40 | typedef struct {\r | |
41 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
42 | UINT16 CommandReg;\r | |
43 | UINT32 StatusReg;\r | |
44 | } EFI_PCI_CAPABILITY_PCIX;\r | |
45 | \r | |
427987f5 | 46 | ///\r |
47 | /// PCI-X Bridge Capabilities List, \r | |
48 | /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b\r | |
bc14bdb3 | 49 | ///\r |
50 | typedef struct {\r | |
51 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
52 | UINT16 SecStatusReg;\r | |
53 | UINT32 StatusReg;\r | |
54 | UINT32 SplitTransCtrlRegUp;\r | |
55 | UINT32 SplitTransCtrlRegDn;\r | |
56 | } EFI_PCI_CAPABILITY_PCIX_BRDG;\r | |
57 | \r | |
766f4bc1 | 58 | #pragma pack()\r |
59 | \r | |
bc14bdb3 | 60 | #define PCI_CODE_TYPE_EFI_IMAGE 0x03\r |
a7ed1e2e | 61 | \r |
62 | #endif\r |