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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 3.0 standard.\r | |
3 | \r | |
826a66d4 | 4 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
9df063a0 | 5 | This program and the accompanying materials \r |
a7ed1e2e | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
a7ed1e2e | 13 | **/\r |
14 | \r | |
842f5579 A |
15 | #ifndef __PCI30_H__\r |
16 | #define __PCI30_H__\r | |
a7ed1e2e | 17 | \r |
bc14bdb3 | 18 | \r |
19 | #include <IndustryStandard/Pci23.h>\r | |
20 | \r | |
21 | ///\r | |
826a66d4 | 22 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r |
bc14bdb3 | 23 | ///\r |
826a66d4 | 24 | ///@{\r |
a7ed1e2e | 25 | #define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r |
bc14bdb3 | 26 | #define PCI_IF_MASS_STORAGE_SATA 0x00\r |
27 | #define PCI_IF_MASS_STORAGE_AHCI 0x01\r | |
826a66d4 | 28 | ///@}\r |
bc14bdb3 | 29 | \r |
826a66d4 RN |
30 | ///\r |
31 | /// PCI_CLASS_WIRELESS, Base Class 0Dh.\r | |
32 | ///\r | |
33 | ///@{\r | |
34 | #define PCI_SUBCLASS_ETHERNET_80211A 0x20\r | |
35 | #define PCI_SUBCLASS_ETHERNET_80211B 0x21\r | |
36 | ///@}\r | |
37 | \r | |
38 | /**\r | |
98642032 | 39 | Macro that checks whether device is a SATA controller.\r |
40 | \r | |
41 | @param _p Specified device.\r | |
42 | \r | |
43 | @retval TRUE Device is a SATA controller.\r | |
44 | @retval FALSE Device is not a SATA controller.\r | |
45 | \r | |
46 | **/\r | |
47 | #define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r | |
48 | \r | |
bc14bdb3 | 49 | ///\r |
50 | /// PCI Capability List IDs and records\r | |
51 | ///\r | |
52 | #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r | |
a7ed1e2e | 53 | \r |
766f4bc1 | 54 | #pragma pack(1)\r |
55 | \r | |
bc14bdb3 | 56 | ///\r |
427987f5 | 57 | /// PCI Data Structure Format\r |
58 | /// Section 5.1.2, PCI Firmware Specification, Revision 3.0\r | |
bc14bdb3 | 59 | ///\r |
a7ed1e2e | 60 | typedef struct {\r |
bc14bdb3 | 61 | UINT32 Signature; ///< "PCIR"\r |
a7ed1e2e | 62 | UINT16 VendorId;\r |
63 | UINT16 DeviceId;\r | |
64 | UINT16 DeviceListOffset;\r | |
65 | UINT16 Length;\r | |
66 | UINT8 Revision;\r | |
67 | UINT8 ClassCode[3];\r | |
68 | UINT16 ImageLength;\r | |
69 | UINT16 CodeRevision;\r | |
70 | UINT8 CodeType;\r | |
71 | UINT8 Indicator;\r | |
72 | UINT16 MaxRuntimeImageLength;\r | |
73 | UINT16 ConfigUtilityCodeHeaderOffset;\r | |
74 | UINT16 DMTFCLPEntryPointOffset;\r | |
75 | } PCI_3_0_DATA_STRUCTURE;\r | |
76 | \r | |
766f4bc1 | 77 | #pragma pack()\r |
78 | \r | |
a7ed1e2e | 79 | #endif\r |