]>
Commit | Line | Data |
---|---|---|
826a66d4 RN |
1 | /** @file\r |
2 | The file lists the PCI class codes only defined in PCI code and ID assignment specification\r | |
3 | revision 1.3.\r | |
4 | \r | |
5 | Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>\r | |
6 | This program and the accompanying materials \r | |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __PCI_CODE_ID_H__\r | |
17 | #define __PCI_CODE_ID_H__\r | |
18 | \r | |
19 | \r | |
20 | ///\r | |
21 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r | |
22 | ///\r | |
23 | ///@{\r | |
24 | #define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00\r | |
25 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11\r | |
26 | #define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12\r | |
27 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13\r | |
28 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21\r | |
29 | #define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02\r | |
30 | #define PCI_CLASS_MASS_STORAGE_SAS 0x07\r | |
31 | #define PCI_IF_MASS_STORAGE_SAS 0x00\r | |
32 | #define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01\r | |
33 | #define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08\r | |
34 | #define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00\r | |
35 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01\r | |
36 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02\r | |
37 | ///@}\r | |
38 | \r | |
39 | ///\r | |
40 | /// PCI_CLASS_NETWORK, Base Class 02h.\r | |
41 | ///\r | |
42 | ///@{\r | |
43 | #define PCI_CLASS_NETWORK_INFINIBAND 0x07\r | |
44 | ///@}\r | |
45 | \r | |
46 | ///\r | |
47 | /// PCI_CLASS_MEDIA, Base Class 04h.\r | |
48 | ///\r | |
49 | ///@{\r | |
50 | #define PCI_CLASS_MEDIA_MIXED_MODE 0x03\r | |
51 | ///@}\r | |
52 | \r | |
53 | ///\r | |
54 | /// PCI_CLASS_BRIDGE, Base Class 06h.\r | |
55 | ///\r | |
56 | ///@{\r | |
57 | #define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B\r | |
58 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00\r | |
59 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01\r | |
60 | ///@}\r | |
61 | \r | |
62 | ///\r | |
63 | /// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.\r | |
64 | ///\r | |
65 | ///@{\r | |
66 | #define PCI_IF_HPET 0x03\r | |
67 | #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\r | |
68 | #define PCI_SUBCLASS_IOMMU 0x06\r | |
69 | ///@}\r | |
70 | \r | |
71 | ///\r | |
72 | /// PCI_CLASS_PROCESSOR, Base Class 0Bh.\r | |
73 | ///\r | |
74 | ///@{\r | |
75 | #define PCI_SUBCLASS_PROC_OTHER 0x80\r | |
76 | ///@}\r | |
77 | \r | |
78 | ///\r | |
79 | /// PCI_CLASS_SERIAL, Base Class 0Ch.\r | |
80 | ///\r | |
81 | ///@{\r | |
82 | #define PCI_IF_XHCI 0x30\r | |
83 | #define PCI_CLASS_SERIAL_OTHER 0x80\r | |
84 | ///@}\r | |
85 | \r | |
86 | ///\r | |
87 | /// PCI_CLASS_SATELLITE, Base Class 0Fh.\r | |
88 | ///\r | |
89 | ///@{\r | |
90 | #define PCI_SUBCLASS_SATELLITE_OTHER 0x80\r | |
91 | ///@}\r | |
92 | \r | |
93 | ///\r | |
94 | /// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.\r | |
95 | ///\r | |
96 | ///@{\r | |
97 | #define PCI_CLASS_PROCESSING_ACCELERATOR 0x12\r | |
98 | ///@}\r | |
99 | \r | |
100 | #endif\r |