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533403e6 | 1 | /** @file\r |
2 | Support for the latest PCI standard.\r | |
3 | \r | |
a1d20250 | 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r |
9df063a0 | 5 | This program and the accompanying materials \r |
533403e6 | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _PCIEXPRESS21_H_\r | |
16 | #define _PCIEXPRESS21_H_\r | |
17 | \r | |
18 | #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r | |
19 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r | |
20 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r | |
21 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r | |
22 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r | |
23 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r | |
24 | \r | |
25 | //\r | |
26 | // for SR-IOV\r | |
27 | //\r | |
28 | #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r | |
29 | #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r | |
30 | #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r | |
31 | #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r | |
32 | \r | |
33 | typedef struct {\r | |
34 | UINT32 CapabilityHeader;\r | |
35 | UINT32 Capability;\r | |
36 | UINT16 Control;\r | |
37 | UINT16 Status;\r | |
38 | UINT16 InitialVFs;\r | |
39 | UINT16 TotalVFs;\r | |
40 | UINT16 NumVFs;\r | |
41 | UINT8 FunctionDependencyLink;\r | |
42 | UINT8 Reserved0;\r | |
43 | UINT16 FirstVFOffset;\r | |
44 | UINT16 VFStride;\r | |
45 | UINT16 Reserved1;\r | |
46 | UINT16 VFDeviceID;\r | |
47 | UINT32 SupportedPageSize;\r | |
48 | UINT32 SystemPageSize;\r | |
49 | UINT32 VFBar[6];\r | |
50 | UINT32 VFMigrationStateArrayOffset;\r | |
51 | } SR_IOV_CAPABILITY_REGISTER;\r | |
52 | \r | |
53 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r | |
54 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r | |
55 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r | |
56 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r | |
57 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r | |
58 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r | |
59 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r | |
60 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r | |
61 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r | |
62 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r | |
63 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r | |
64 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r | |
65 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r | |
66 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r | |
67 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r | |
68 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r | |
69 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r | |
70 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r | |
71 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r | |
72 | \r | |
a1d20250 JC |
73 | typedef struct {\r |
74 | UINT32 CapabilityId:16;\r | |
75 | UINT32 CapabilityVersion:4;\r | |
76 | UINT32 NextCapabilityOffset:12;\r | |
77 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r | |
78 | \r | |
79 | #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r | |
80 | \r | |
81 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r | |
82 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r | |
83 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r | |
84 | \r | |
85 | typedef struct {\r | |
86 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
87 | UINT32 UncorrectableErrorStatus;\r | |
88 | UINT32 UncorrectableErrorMask;\r | |
89 | UINT32 UncorrectableErrorSeverity;\r | |
90 | UINT32 CorrectableErrorStatus;\r | |
91 | UINT32 CorrectableErrorMask;\r | |
92 | UINT32 AdvancedErrorCapabilitiesAndControl;\r | |
93 | UINT32 HeaderLog;\r | |
94 | UINT32 RootErrorCommand;\r | |
95 | UINT32 RootErrorStatus;\r | |
96 | UINT16 ErrorSourceIdentification;\r | |
97 | UINT16 CorrectableErrorSourceIdentification;\r | |
98 | UINT32 TlpPrefixLog[4];\r | |
99 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r | |
100 | \r | |
101 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r | |
102 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009\r | |
103 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r | |
104 | \r | |
105 | typedef struct {\r | |
106 | UINT32 VcResourceCapability:24;\r | |
107 | UINT32 PortArbTableOffset:8;\r | |
108 | UINT32 VcResourceControl;\r | |
109 | UINT16 Reserved1;\r | |
110 | UINT16 VcResourceStatus;\r | |
111 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r | |
112 | \r | |
113 | typedef struct {\r | |
114 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
115 | UINT32 ExtendedVcCount:3;\r | |
116 | UINT32 PortVcCapability1:29;\r | |
117 | UINT32 PortVcCapability2:24;\r | |
118 | UINT32 VcArbTableOffset:8;\r | |
119 | UINT16 PortVcControl;\r | |
120 | UINT16 PortVcStatus;\r | |
121 | PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r | |
122 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r | |
123 | \r | |
124 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r | |
125 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r | |
126 | \r | |
127 | typedef struct {\r | |
128 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
129 | UINT64 SerialNumber;\r | |
130 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r | |
131 | \r | |
132 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r | |
133 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r | |
134 | \r | |
135 | typedef struct {\r | |
136 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
137 | UINT32 ElementSelfDescription;\r | |
138 | UINT32 Reserved;\r | |
139 | UINT32 LinkEntry[1];\r | |
140 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r | |
141 | \r | |
142 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r | |
143 | \r | |
144 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r | |
145 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r | |
146 | \r | |
147 | typedef struct {\r | |
148 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
149 | UINT32 RootComplexLinkCapabilities;\r | |
150 | UINT16 RootComplexLinkControl;\r | |
151 | UINT16 RootComplexLinkStatus;\r | |
152 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r | |
153 | \r | |
154 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r | |
155 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r | |
156 | \r | |
157 | typedef struct {\r | |
158 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
159 | UINT32 DataSelect:8;\r | |
160 | UINT32 Reserved:24;\r | |
161 | UINT32 Data;\r | |
162 | UINT32 PowerBudgetCapability:1;\r | |
163 | UINT32 Reserved2:7;\r | |
164 | UINT32 Reserved3:24;\r | |
165 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r | |
166 | \r | |
167 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r | |
168 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r | |
169 | \r | |
170 | typedef struct {\r | |
171 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
172 | UINT16 AcsCapability;\r | |
173 | UINT16 AcsControl;\r | |
174 | UINT8 EgressControlVectorArray[1];\r | |
175 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r | |
176 | \r | |
177 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r | |
178 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r | |
179 | \r | |
180 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r | |
181 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r | |
182 | \r | |
183 | typedef struct {\r | |
184 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
185 | UINT32 AssociationBitmap;\r | |
186 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r | |
187 | \r | |
188 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r | |
189 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1\r | |
190 | \r | |
191 | typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r | |
192 | \r | |
193 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r | |
194 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r | |
195 | \r | |
196 | typedef struct {\r | |
197 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
198 | UINT32 VendorSpecificHeader;\r | |
199 | UINT8 VendorSpecific[1];\r | |
200 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r | |
201 | \r | |
202 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r | |
203 | \r | |
204 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r | |
205 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r | |
206 | \r | |
207 | typedef struct {\r | |
208 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
209 | UINT16 VendorId;\r | |
210 | UINT16 DeviceId;\r | |
211 | UINT32 RcrbCapabilities;\r | |
212 | UINT32 RcrbControl;\r | |
213 | UINT32 Reserved;\r | |
214 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r | |
215 | \r | |
216 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r | |
217 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r | |
218 | \r | |
219 | typedef struct {\r | |
220 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
221 | UINT16 MultiCastCapability;\r | |
222 | UINT16 MulticastControl;\r | |
223 | UINT64 McBaseAddress;\r | |
224 | UINT64 McReceiveAddress;\r | |
225 | UINT64 McBlockAll;\r | |
226 | UINT64 McBlockUntranslated;\r | |
227 | UINT64 McOverlayBar;\r | |
228 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r | |
229 | \r | |
230 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r | |
231 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1\r | |
232 | \r | |
233 | typedef struct {\r | |
234 | UINT32 ResizableBarCapability;\r | |
235 | UINT16 ResizableBarControl;\r | |
236 | UINT16 Reserved;\r | |
237 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r | |
238 | \r | |
239 | typedef struct {\r | |
240 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
241 | PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r | |
242 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r | |
243 | \r | |
e1c9edd6 JC |
244 | #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)\r |
245 | \r | |
a1d20250 JC |
246 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r |
247 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r | |
248 | \r | |
249 | typedef struct {\r | |
250 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
251 | UINT16 AriCapability;\r | |
252 | UINT16 AriControl;\r | |
253 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r | |
254 | \r | |
255 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r | |
256 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r | |
257 | \r | |
258 | typedef struct {\r | |
259 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
260 | UINT32 DpaCapability;\r | |
261 | UINT32 DpaLatencyIndicator;\r | |
262 | UINT16 DpaStatus;\r | |
263 | UINT16 DpaControl;\r | |
264 | UINT8 DpaPowerAllocationArray[1];\r | |
265 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r | |
266 | \r | |
267 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r | |
268 | \r | |
269 | \r | |
270 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r | |
271 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r | |
272 | \r | |
273 | typedef struct {\r | |
274 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
275 | UINT16 MaxSnoopLatency;\r | |
276 | UINT16 MaxNoSnoopLatency;\r | |
277 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r | |
278 | \r | |
279 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r | |
280 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r | |
281 | \r | |
282 | typedef struct {\r | |
283 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
284 | UINT32 TphRequesterCapability;\r | |
285 | UINT32 TphRequesterControl;\r | |
286 | UINT16 TphStTable[1];\r | |
287 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r | |
288 | \r | |
e1c9edd6 JC |
289 | #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r |
290 | \r | |
533403e6 | 291 | #endif\r |