[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Sal.h

/** @file\r
  Main SAL API's defined in SAL 3.0 specification. \r
\r
  Copyright (c) 2006, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef __SAL_API_H__\r
#define __SAL_API_H__\r
\r
//\r
// FIT Types \r
// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
//\r
#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
#define EFI_SAL_FIT_PAL_B_TYPE      0x01\r
//\r
// type from 0x02 to 0x0E is reserved.\r
//\r
#define EFI_SAL_FIT_PAL_A_TYPE  0x0F\r
//\r
// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
//\r
#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
#define EFI_SAL_FIT_UNUSED_TYPE   0x7F\r
\r
//\r
// EFI_SAL_STATUS \r
//\r
typedef UINTN EFI_SAL_STATUS;\r
\r
#define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)\r
#define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)\r
#define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)\r
#define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)\r
#define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)\r
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
#define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)\r
#define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)\r
\r
//\r
//  Return values from SAL\r
//\r
typedef struct {\r
  EFI_SAL_STATUS  Status; // register r8\r
  UINTN           r9;\r
  UINTN           r10;\r
  UINTN           r11;\r
} SAL_RETURN_REGS;\r
\r
//\r
//  Delivery Mode of IPF CPU.\r
//\r
typedef enum {\r
  EFI_DELIVERY_MODE_INT,\r
  EFI_DELIVERY_MODE_MPreserved1,\r
  EFI_DELIVERY_MODE_PMI,\r
  EFI_DELIVERY_MODE_MPreserved2,\r
  EFI_DELIVERY_MODE_NMI,\r
  EFI_DELIVERY_MODE_INIT,\r
  EFI_DELIVERY_MODE_MPreserved3,\r
  EFI_DELIVERY_MODE_ExtINT\r
} EFI_DELIVERY_MODE;\r
\r
typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
  (\r
    IN UINT64 FunctionId,\r
    IN UINT64 Arg2,\r
    IN UINT64 Arg3,\r
    IN UINT64 Arg4,\r
    IN UINT64 Arg5,\r
    IN UINT64 Arg6,\r
    IN UINT64 Arg7,\r
    IN UINT64 Arg8\r
  );\r
\r
//\r
// SAL Procedure FunctionId definition\r
//\r
#define EFI_SAL_SET_VECTORS             0x01000000\r
#define EFI_SAL_GET_STATE_INFO          0x01000001\r
#define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002\r
#define EFI_SAL_CLEAR_STATE_INFO        0x01000003\r
#define EFI_SAL_MC_RENDEZ               0x01000004\r
#define EFI_SAL_MC_SET_PARAMS           0x01000005\r
#define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006\r
#define EFI_SAL_CACHE_FLUSH             0x01000008\r
#define EFI_SAL_CACHE_INIT              0x01000009\r
#define EFI_SAL_PCI_CONFIG_READ         0x01000010\r
#define EFI_SAL_PCI_CONFIG_WRITE        0x01000011\r
#define EFI_SAL_FREQ_BASE               0x01000012\r
#define EFI_SAL_PHYSICAL_ID_INFO        0x01000013\r
#define EFI_SAL_UPDATE_PAL              0x01000020\r
\r
#define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff\r
#define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021\r
\r
//\r
// SAL Procedure parameter definitions\r
// Not much point in using typedefs or enums because all params\r
// are UINT64 and the entry point is common\r
//\r
// EFI_SAL_SET_VECTORS\r
//\r
#define EFI_SAL_SET_MCA_VECTOR          0x0\r
#define EFI_SAL_SET_INIT_VECTOR         0x1\r
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2\r
\r
typedef struct {\r
  UINT64  Length : 32;\r
  UINT64  ChecksumValid : 1;\r
  UINT64  Reserved1 : 7;\r
  UINT64  ByteChecksum : 8;\r
  UINT64  Reserved2 : 16;\r
} SAL_SET_VECTORS_CS_N;\r
\r
//\r
// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
// EFI_SAL_CLEAR_STATE_INFO\r
//\r
#define EFI_SAL_MCA_STATE_INFO  0x0\r
#define EFI_SAL_INIT_STATE_INFO 0x1\r
#define EFI_SAL_CMC_STATE_INFO  0x2\r
#define EFI_SAL_CP_STATE_INFO   0x3\r
\r
//\r
// EFI_SAL_MC_SET_PARAMS\r
//\r
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
#define EFI_SAL_MC_SET_CPE_PARAM    0x3\r
\r
#define EFI_SAL_MC_SET_INTR_PARAM   0x1\r
#define EFI_SAL_MC_SET_MEM_PARAM    0x2\r
\r
//\r
// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
//\r
#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
\r
//\r
// EFI_SAL_CACHE_FLUSH\r
//\r
#define EFI_SAL_FLUSH_I_CACHE       0x01\r
#define EFI_SAL_FLUSH_D_CACHE       0x02\r
#define EFI_SAL_FLUSH_BOTH_CACHE    0x03\r
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
\r
//\r
// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
//\r
#define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1\r
#define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2\r
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
\r
typedef struct {\r
  UINT64  Register : 8;\r
  UINT64  Function : 3;\r
  UINT64  Device : 5;\r
  UINT64  Bus : 8;\r
  UINT64  Segment : 8;\r
  UINT64  Reserved : 32;\r
} SAL_PCI_ADDRESS;\r
\r
//\r
// EFI_SAL_FREQ_BASE\r
//\r
#define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0\r
#define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1\r
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2\r
\r
//\r
// EFI_SAL_UPDATE_PAL\r
//\r
#define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)\r
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)\r
#define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)\r
#define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)\r
#define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)\r
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)\r
#define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)\r
#define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)\r
\r
typedef struct {\r
  UINT32  Size;\r
  UINT32  MmddyyyyDate;\r
  UINT16  Version;\r
  UINT8   Type;\r
  UINT8   Reserved[5];\r
  UINT64  FwVendorId;\r
} SAL_UPDATE_PAL_DATA_BLOCK;\r
\r
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
  struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
  struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;\r
  UINT8                             StoreChecksum;\r
  UINT8                             Reserved[15];\r
} SAL_UPDATE_PAL_INFO_BLOCK;\r
\r
//\r
// SAL System Table Definitions\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT32  Signature;\r
  UINT32  Length;\r
  UINT16  SalRevision;\r
  UINT16  EntryCount;\r
  UINT8   CheckSum;\r
  UINT8   Reserved[7];\r
  UINT16  SalAVersion;\r
  UINT16  SalBVersion;\r
  UINT8   OemId[32];\r
  UINT8   ProductId[32];\r
  UINT8   Reserved2[8];\r
} SAL_SYSTEM_TABLE_HEADER;\r
#pragma pack()\r
\r
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
#define EFI_SAL_REVISION            0x0300\r
//\r
// SAL System Types\r
//\r
#define EFI_SAL_ST_ENTRY_POINT        0\r
#define EFI_SAL_ST_MEMORY_DESCRIPTOR  1\r
#define EFI_SAL_ST_PLATFORM_FEATURES  2\r
#define EFI_SAL_ST_TR_USAGE           3\r
#define EFI_SAL_ST_PTC                4\r
#define EFI_SAL_ST_AP_WAKEUP          5\r
\r
//\r
// SAL System Type Sizes\r
//\r
#define EFI_SAL_ST_ENTRY_POINT_SIZE        48\r
#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32\r
#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16\r
#define EFI_SAL_ST_TR_USAGE_SIZE           32\r
#define EFI_SAL_ST_PTC_SIZE                16\r
#define EFI_SAL_ST_AP_WAKEUP_SIZE          16\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   Type; //  Type == 0\r
  UINT8   Reserved[7];\r
  UINT64  PalProcEntry;\r
  UINT64  SalProcEntry;\r
  UINT64  SalGlobalDataPointer;\r
  UINT64  Reserved2[2];\r
} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8 Type;                     // Type == 2\r
  UINT8 PlatformFeatures;\r
  UINT8 Reserved[14];\r
} SAL_ST_PLATFORM_FEATURES;\r
#pragma pack()\r
\r
#define SAL_PLAT_FEAT_BUS_LOCK      0x01\r
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   Type;                   // Type == 3\r
  UINT8   TRType;\r
  UINT8   TRNumber;\r
  UINT8   Reserved[5];\r
  UINT64  VirtualAddress;\r
  UINT64  EncodedPageSize;\r
  UINT64  Reserved1;\r
} SAL_ST_TR_DECRIPTOR;\r
#pragma pack()\r
\r
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
#define EFI_SAL_ST_TR_USAGE_DATA        01\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT64  NumberOfProcessors;\r
  UINT64  LocalIDRegister;\r
} SAL_COHERENCE_DOMAIN_INFO;\r
#pragma pack()\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                     Type; // Type == 4\r
  UINT8                     Reserved[3];\r
  UINT32                    NumberOfDomains;\r
  SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
#pragma pack()\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   Type;                   // Type == 5\r
  UINT8   WakeUpType;\r
  UINT8   Reserved[6];\r
  UINT64  ExternalInterruptVector;\r
} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
#pragma pack()\r
//\r
// FIT Entry\r
//\r
#define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24\r
#define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32\r
#define EFI_SAL_FIT_PALB_TYPE   01\r
\r
typedef struct {\r
  UINT64  Address;\r
  UINT8   Size[3];\r
  UINT8   Reserved;\r
  UINT16  Revision;\r
  UINT8   Type : 7;\r
  UINT8   CheckSumValid : 1;\r
  UINT8   CheckSum;\r
} EFI_SAL_FIT_ENTRY;\r
\r
//\r
//  SAL Common Record Header\r
//\r
typedef struct {\r
  UINT16  Length;\r
  UINT8   Data[1024];\r
} SAL_OEM_DATA;\r
\r
typedef struct {\r
  UINT8 Seconds;\r
  UINT8 Minutes;\r
  UINT8 Hours;\r
  UINT8 Reserved;\r
  UINT8 Day;\r
  UINT8 Month;\r
  UINT8 Year;\r
  UINT8 Century;\r
} SAL_TIME_STAMP;\r
\r
typedef struct {\r
  UINT64          RecordId;\r
  UINT16          Revision;\r
  UINT8           ErrorSeverity;\r
  UINT8           ValidationBits;\r
  UINT32          RecordLength;\r
  SAL_TIME_STAMP  TimeStamp;\r
  UINT8           OemPlatformId[16];\r
} SAL_RECORD_HEADER;\r
\r
typedef struct {\r
  GUID  		Guid;\r
  UINT16    Revision;\r
  UINT8     ErrorRecoveryInfo;\r
  UINT8     Reserved;\r
  UINT32    SectionLength;\r
} SAL_SEC_HEADER;\r
\r
//\r
// SAL Processor Record\r
//\r
#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define CHECK_INFO_VALID_BIT_MASK   0x1\r
#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
#define TARGER_ID_VALID_BIT_MASK    0x8\r
#define PRECISE_IP_VALID_BIT_MASK   0x10\r
\r
typedef struct {\r
  UINT64  InfoValid : 1;\r
  UINT64  ReqValid : 1;\r
  UINT64  RespValid : 1;\r
  UINT64  TargetValid : 1;\r
  UINT64  IpValid : 1;\r
  UINT64  Reserved : 59;\r
  UINT64  Info;\r
  UINT64  Req;\r
  UINT64  Resp;\r
  UINT64  Target;\r
  UINT64  Ip;\r
} MOD_ERROR_INFO;\r
\r
typedef struct {\r
  UINT8 CpuidInfo[40];\r
  UINT8 Reserved;\r
} CPUID_INFO;\r
\r
typedef struct {\r
  UINT64  FrLow;\r
  UINT64  FrHigh;\r
} FR_STRUCT;\r
\r
#define MIN_STATE_VALID_BIT_MASK  0x1\r
#define BR_VALID_BIT_MASK         0x2\r
#define CR_VALID_BIT_MASK         0x4\r
#define AR_VALID_BIT_MASK         0x8\r
#define RR_VALID_BIT_MASK         0x10\r
#define FR_VALID_BIT_MASK         0x20\r
\r
typedef struct {\r
  UINT64    ValidFieldBits;\r
  UINT8     MinStateInfo[1024];\r
  UINT64    Br[8];\r
  UINT64    Cr[128];\r
  UINT64    Ar[128];\r
  UINT64    Rr[8];\r
  FR_STRUCT Fr[128];\r
} PSI_STATIC_STRUCT;\r
\r
#define PROC_ERROR_MAP_VALID_BIT_MASK       0x1\r
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
#define PROC_CR_LID_VALID_BIT_MASK          0x4\r
#define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8\r
#define CPU_INFO_VALID_BIT_MASK             0x1000000\r
\r
typedef struct {\r
  SAL_SEC_HEADER    SectionHeader;\r
  UINT64            ValidationBits;\r
  UINT64            ProcErrorMap;\r
  UINT64            ProcStateParameter;\r
  UINT64            ProcCrLid;\r
  MOD_ERROR_INFO    CacheError[15];\r
  MOD_ERROR_INFO    TlbError[15];\r
  MOD_ERROR_INFO    BusError[15];\r
  MOD_ERROR_INFO    RegFileCheck[15];\r
  MOD_ERROR_INFO    MsCheck[15];\r
  CPUID_INFO        CpuInfo;\r
  PSI_STATIC_STRUCT PsiValidData;\r
} SAL_PROCESSOR_ERROR_RECORD;\r
\r
//\r
//  Sal Platform memory Error Record\r
//\r
#define SAL_MEMORY_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1\r
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2\r
#define MEMORY_ADDR_BIT_MASK                              0x4\r
#define MEMORY_NODE_VALID_BIT_MASK                        0x8\r
#define MEMORY_CARD_VALID_BIT_MASK                        0x10\r
#define MEMORY_MODULE_VALID_BIT_MASK                      0x20\r
#define MEMORY_BANK_VALID_BIT_MASK                        0x40\r
#define MEMORY_DEVICE_VALID_BIT_MASK                      0x80\r
#define MEMORY_ROW_VALID_BIT_MASK                         0x100\r
#define MEMORY_COLUMN_VALID_BIT_MASK                      0x200\r
#define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400\r
#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800\r
#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000\r
#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000\r
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000\r
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000\r
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          MemErrorStatus;\r
  UINT64          MemPhysicalAddress;\r
  UINT64          MemPhysicalAddressMask;\r
  UINT16          MemNode;\r
  UINT16          MemCard;\r
  UINT16          MemModule;\r
  UINT16          MemBank;\r
  UINT16          MemDevice;\r
  UINT16          MemRow;\r
  UINT16          MemColumn;\r
  UINT16          MemBitPosition;\r
  UINT64          ModRequestorId;\r
  UINT64          ModResponderId;\r
  UINT64          ModTargetId;\r
  UINT64          BusSpecificData;\r
  UINT8           MemPlatformOemId[16];\r
} SAL_MEMORY_ERROR_RECORD;\r
\r
//\r
//  PCI BUS Errors\r
//\r
#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1\r
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2\r
#define PCI_BUS_ID_VALID_BIT_MASK               0x4\r
#define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8\r
#define PCI_BUS_DATA_VALID_BIT_MASK             0x10\r
#define PCI_BUS_CMD_VALID_BIT_MASK              0x20\r
#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40\r
#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80\r
#define PCI_BUS_TARGET_VALID_BIT_MASK           0x100\r
#define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200\r
#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400\r
\r
typedef struct {\r
  UINT8 BusNumber;\r
  UINT8 SegmentNumber;\r
} PCI_BUS_ID;\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          PciBusErrorStatus;\r
  UINT16          PciBusErrorType;\r
  PCI_BUS_ID      PciBusId;\r
  UINT32          Reserved;\r
  UINT64          PciBusAddress;\r
  UINT64          PciBusData;\r
  UINT64          PciBusCommand;\r
  UINT64          PciBusRequestorId;\r
  UINT64          PciBusResponderId;\r
  UINT64          PciBusTargetId;\r
  UINT8           PciBusOemId[16];\r
} SAL_PCI_BUS_ERROR_RECORD;\r
\r
//\r
//  PCI Component Errors\r
//\r
#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1\r
#define PCI_COMP_INFO_VALID_BIT_MASK            0x2\r
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4\r
#define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8\r
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10\r
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
\r
typedef struct {\r
  UINT16  VendorId;\r
  UINT16  DeviceId;\r
  UINT8   ClassCode[3];\r
  UINT8   FunctionNumber;\r
  UINT8   DeviceNumber;\r
  UINT8   BusNumber;\r
  UINT8   SegmentNumber;\r
  UINT8   Reserved[5];\r
} PCI_COMP_INFO;\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          PciComponentErrorStatus;\r
  PCI_COMP_INFO   PciComponentInfo;\r
  UINT32          PciComponentMemNum;\r
  UINT32          PciComponentIoNum;\r
  UINT8           PciBusOemId[16];\r
} SAL_PCI_COMPONENT_ERROR_RECORD;\r
\r
//\r
//  Sal Device Errors Info.\r
//\r
#define SAL_DEVICE_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define SEL_RECORD_ID_VALID_BIT_MASK      0x1;\r
#define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;\r
#define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;\r
#define SEL_EVM_REV_VALID_BIT_MASK        0x8;\r
#define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;\r
#define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;\r
#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
#define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;\r
#define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;\r
#define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT16          SelRecordId;\r
  UINT8           SelRecordType;\r
  UINT32          TimeStamp;\r
  UINT16          GeneratorId;\r
  UINT8           EvmRevision;\r
  UINT8           SensorType;\r
  UINT8           SensorNum;\r
  UINT8           EventDirType;\r
  UINT8           Data1;\r
  UINT8           Data2;\r
  UINT8           Data3;\r
} SAL_DEVICE_ERROR_RECORD;\r
\r
//\r
//  Sal SMBIOS Device Errors Info.\r
//\r
#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1\r
#define SMBIOS_LENGTH_VALID_BIT_MASK      0x2\r
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4\r
#define SMBIOS_DATA_VALID_BIT_MASK        0x8\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT8           SmbiosEventType;\r
  UINT8           SmbiosLength;\r
  UINT8           SmbiosBcdTimeStamp[6];\r
} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
\r
//\r
//  Sal Platform Specific Errors Info.\r
//\r
#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
  }\r
\r
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1\r
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2\r
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4\r
#define PLATFORM_TARGET_VALID_BIT_MASK          0x8\r
#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10\r
#define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20\r
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          PlatformErrorStatus;\r
  UINT64          PlatformRequestorId;\r
  UINT64          PlatformResponderId;\r
  UINT64          PlatformTargetId;\r
  UINT64          PlatformBusSpecificData;\r
  UINT8           OemComponentId[16];\r
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
\r
//\r
// Union of all the possible Sal Record Types\r
//\r
typedef union {\r
  SAL_RECORD_HEADER                   *RecordHeader;\r
  SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;\r
  SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;\r
  SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;\r
  SAL_DEVICE_ERROR_RECORD             *ImpiRecord;\r
  SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;\r
  SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;\r
  SAL_MEMORY_ERROR_RECORD             *MemoryRecord;\r
  UINT8                               *Raw;\r
} SAL_ERROR_RECORDS_POINTERS;\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
540dfc26	1	/** @file\r
	2	Main SAL API's defined in SAL 3.0 specification. \r
	3	\r
	4	Copyright (c) 2006, Intel Corporation \r
	5	All rights reserved. This program and the accompanying materials \r
	6	are licensed and made available under the terms and conditions of the BSD License \r
	7	which accompanies this distribution. The full text of the license may be found at \r
	8	http://opensource.org/licenses/bsd-license.php \r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	\r
540dfc26	13	**/\r
	14	\r
	15	#ifndef __SAL_API_H__\r
	16	#define __SAL_API_H__\r
	17	\r
	18	//\r
	19	// FIT Types \r
	20	// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
	21	//\r
	22	#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
	23	#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
	24	//\r
	25	// type from 0x02 to 0x0E is reserved.\r
	26	//\r
	27	#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
	28	//\r
	29	// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
	30	//\r
	31	#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
	32	#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
	33	\r
	34	//\r
	35	// EFI_SAL_STATUS \r
	36	//\r
	37	typedef UINTN EFI_SAL_STATUS;\r
	38	\r
	39	#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
	40	#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
	41	#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
	42	#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
	43	#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
	44	#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
	45	#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
	46	#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
	47	\r
	48	//\r
	49	// Return values from SAL\r
	50	//\r
	51	typedef struct {\r
	52	EFI_SAL_STATUS Status; // register r8\r
	53	UINTN r9;\r
	54	UINTN r10;\r
	55	UINTN r11;\r
	56	} SAL_RETURN_REGS;\r
	57	\r
	58	//\r
	59	// Delivery Mode of IPF CPU.\r
	60	//\r
	61	typedef enum {\r
	62	EFI_DELIVERY_MODE_INT,\r
	63	EFI_DELIVERY_MODE_MPreserved1,\r
	64	EFI_DELIVERY_MODE_PMI,\r
	65	EFI_DELIVERY_MODE_MPreserved2,\r
	66	EFI_DELIVERY_MODE_NMI,\r
	67	EFI_DELIVERY_MODE_INIT,\r
	68	EFI_DELIVERY_MODE_MPreserved3,\r
	69	EFI_DELIVERY_MODE_ExtINT\r
	70	} EFI_DELIVERY_MODE;\r
	71	\r
	72	typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
	73	(\r
	74	IN UINT64 FunctionId,\r
	75	IN UINT64 Arg2,\r
	76	IN UINT64 Arg3,\r
77	IN UINT64 Arg4,\r
78	IN UINT64 Arg5,\r
79	IN UINT64 Arg6,\r
80	IN UINT64 Arg7,\r
81	IN UINT64 Arg8\r
82	);\r
83	\r
84	//\r
85	// SAL Procedure FunctionId definition\r
86	//\r
87	#define EFI_SAL_SET_VECTORS 0x01000000\r
88	#define EFI_SAL_GET_STATE_INFO 0x01000001\r
89	#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
90	#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
91	#define EFI_SAL_MC_RENDEZ 0x01000004\r
92	#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
93	#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
94	#define EFI_SAL_CACHE_FLUSH 0x01000008\r
95	#define EFI_SAL_CACHE_INIT 0x01000009\r
96	#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
97	#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
98	#define EFI_SAL_FREQ_BASE 0x01000012\r
9c8403b3	99	#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
540dfc26	100	#define EFI_SAL_UPDATE_PAL 0x01000020\r
	101	\r
	102	#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
	103	#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
	104	\r
	105	//\r
	106	// SAL Procedure parameter definitions\r
	107	// Not much point in using typedefs or enums because all params\r
	108	// are UINT64 and the entry point is common\r
	109	//\r
	110	// EFI_SAL_SET_VECTORS\r
	111	//\r
	112	#define EFI_SAL_SET_MCA_VECTOR 0x0\r
	113	#define EFI_SAL_SET_INIT_VECTOR 0x1\r
	114	#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
	115	\r
	116	typedef struct {\r
	117	UINT64 Length : 32;\r
	118	UINT64 ChecksumValid : 1;\r
	119	UINT64 Reserved1 : 7;\r
	120	UINT64 ByteChecksum : 8;\r
	121	UINT64 Reserved2 : 16;\r
	122	} SAL_SET_VECTORS_CS_N;\r
	123	\r
	124	//\r
	125	// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
	126	// EFI_SAL_CLEAR_STATE_INFO\r
	127	//\r
	128	#define EFI_SAL_MCA_STATE_INFO 0x0\r
	129	#define EFI_SAL_INIT_STATE_INFO 0x1\r
	130	#define EFI_SAL_CMC_STATE_INFO 0x2\r
	131	#define EFI_SAL_CP_STATE_INFO 0x3\r
	132	\r
	133	//\r
	134	// EFI_SAL_MC_SET_PARAMS\r
	135	//\r
	136	#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
	137	#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
	138	#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
	139	\r
	140	#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
	141	#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
	142	\r
	143	//\r
	144	// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
	145	//\r
	146	#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
	147	\r
	148	//\r
	149	// EFI_SAL_CACHE_FLUSH\r
	150	//\r
	151	#define EFI_SAL_FLUSH_I_CACHE 0x01\r
	152	#define EFI_SAL_FLUSH_D_CACHE 0x02\r
	153	#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
	154	#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
	155	\r
	156	//\r
	157	// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
	158	//\r
	159	#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
	160	#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
	161	#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
	162	\r
	163	typedef struct {\r
164	UINT64 Register : 8;\r
165	UINT64 Function : 3;\r
166	UINT64 Device : 5;\r
167	UINT64 Bus : 8;\r
168	UINT64 Segment : 8;\r
169	UINT64 Reserved : 32;\r
170	} SAL_PCI_ADDRESS;\r
171	\r
172	//\r
173	// EFI_SAL_FREQ_BASE\r
174	//\r
175	#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
176	#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
177	#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
178	\r
179	//\r
180	// EFI_SAL_UPDATE_PAL\r
181	//\r
182	#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
183	#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
184	#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
185	#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
186	#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
187	#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
188	#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
189	#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
190	\r
191	typedef struct {\r
192	UINT32 Size;\r
193	UINT32 MmddyyyyDate;\r
194	UINT16 Version;\r
195	UINT8 Type;\r
196	UINT8 Reserved[5];\r
197	UINT64 FwVendorId;\r
198	} SAL_UPDATE_PAL_DATA_BLOCK;\r
199	\r
200	typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
201	struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
202	struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
203	UINT8 StoreChecksum;\r
204	UINT8 Reserved[15];\r
205	} SAL_UPDATE_PAL_INFO_BLOCK;\r
206	\r
207	//\r
208	// SAL System Table Definitions\r
209	//\r
210	#pragma pack(1)\r
211	typedef struct {\r
212	UINT32 Signature;\r
213	UINT32 Length;\r
214	UINT16 SalRevision;\r
215	UINT16 EntryCount;\r
216	UINT8 CheckSum;\r
217	UINT8 Reserved[7];\r
218	UINT16 SalAVersion;\r
219	UINT16 SalBVersion;\r
220	UINT8 OemId[32];\r
221	UINT8 ProductId[32];\r
222	UINT8 Reserved2[8];\r
223	} SAL_SYSTEM_TABLE_HEADER;\r
224	#pragma pack()\r
225	\r
226	#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
227	#define EFI_SAL_REVISION 0x0300\r
228	//\r
229	// SAL System Types\r
230	//\r
231	#define EFI_SAL_ST_ENTRY_POINT 0\r
232	#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
233	#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
234	#define EFI_SAL_ST_TR_USAGE 3\r
235	#define EFI_SAL_ST_PTC 4\r
236	#define EFI_SAL_ST_AP_WAKEUP 5\r
237	\r
809177f5	238	//\r
	239	// SAL System Type Sizes\r
	240	//\r
	241	#define EFI_SAL_ST_ENTRY_POINT_SIZE 48\r
	242	#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32\r
	243	#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16\r
	244	#define EFI_SAL_ST_TR_USAGE_SIZE 32\r
	245	#define EFI_SAL_ST_PTC_SIZE 16\r
	246	#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
	247	\r
540dfc26	248	#pragma pack(1)\r
	249	typedef struct {\r
	250	UINT8 Type; // Type == 0\r
	251	UINT8 Reserved[7];\r
	252	UINT64 PalProcEntry;\r
	253	UINT64 SalProcEntry;\r
	254	UINT64 SalGlobalDataPointer;\r
	255	UINT64 Reserved2[2];\r
	256	} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
	257	\r
540dfc26	258	#pragma pack(1)\r
	259	typedef struct {\r
	260	UINT8 Type; // Type == 2\r
	261	UINT8 PlatformFeatures;\r
	262	UINT8 Reserved[14];\r
	263	} SAL_ST_PLATFORM_FEATURES;\r
	264	#pragma pack()\r
	265	\r
	266	#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
	267	#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
	268	#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
	269	\r
	270	#pragma pack(1)\r
	271	typedef struct {\r
	272	UINT8 Type; // Type == 3\r
	273	UINT8 TRType;\r
	274	UINT8 TRNumber;\r
	275	UINT8 Reserved[5];\r
	276	UINT64 VirtualAddress;\r
	277	UINT64 EncodedPageSize;\r
	278	UINT64 Reserved1;\r
	279	} SAL_ST_TR_DECRIPTOR;\r
	280	#pragma pack()\r
	281	\r
	282	#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
	283	#define EFI_SAL_ST_TR_USAGE_DATA 01\r
	284	\r
	285	#pragma pack(1)\r
	286	typedef struct {\r
	287	UINT64 NumberOfProcessors;\r
	288	UINT64 LocalIDRegister;\r
	289	} SAL_COHERENCE_DOMAIN_INFO;\r
	290	#pragma pack()\r
	291	\r
	292	#pragma pack(1)\r
	293	typedef struct {\r
	294	UINT8 Type; // Type == 4\r
	295	UINT8 Reserved[3];\r
	296	UINT32 NumberOfDomains;\r
	297	SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
	298	} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
	299	#pragma pack()\r
	300	\r
	301	#pragma pack(1)\r
	302	typedef struct {\r
	303	UINT8 Type; // Type == 5\r
	304	UINT8 WakeUpType;\r
	305	UINT8 Reserved[6];\r
	306	UINT64 ExternalInterruptVector;\r
	307	} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
	308	#pragma pack()\r
	309	//\r
	310	// FIT Entry\r
	311	//\r
	312	#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
	313	#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
	314	#define EFI_SAL_FIT_PALB_TYPE 01\r
	315	\r
	316	typedef struct {\r
	317	UINT64 Address;\r
	318	UINT8 Size[3];\r
	319	UINT8 Reserved;\r
	320	UINT16 Revision;\r
	321	UINT8 Type : 7;\r
322	UINT8 CheckSumValid : 1;\r
323	UINT8 CheckSum;\r
324	} EFI_SAL_FIT_ENTRY;\r
325	\r
326	//\r
327	// SAL Common Record Header\r
328	//\r
329	typedef struct {\r
330	UINT16 Length;\r
331	UINT8 Data[1024];\r
332	} SAL_OEM_DATA;\r
333	\r
334	typedef struct {\r
335	UINT8 Seconds;\r
336	UINT8 Minutes;\r
337	UINT8 Hours;\r
338	UINT8 Reserved;\r
339	UINT8 Day;\r
340	UINT8 Month;\r
341	UINT8 Year;\r
342	UINT8 Century;\r
343	} SAL_TIME_STAMP;\r
344	\r
345	typedef struct {\r
346	UINT64 RecordId;\r
347	UINT16 Revision;\r
348	UINT8 ErrorSeverity;\r
349	UINT8 ValidationBits;\r
350	UINT32 RecordLength;\r
351	SAL_TIME_STAMP TimeStamp;\r
352	UINT8 OemPlatformId[16];\r
353	} SAL_RECORD_HEADER;\r
354	\r
355	typedef struct {\r
356	GUID Guid;\r
357	UINT16 Revision;\r
358	UINT8 ErrorRecoveryInfo;\r
359	UINT8 Reserved;\r
360	UINT32 SectionLength;\r
361	} SAL_SEC_HEADER;\r
362	\r
363	//\r
364	// SAL Processor Record\r
365	//\r
366	#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
367	{ \\r
368	0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
369	}\r
370	\r
371	#define CHECK_INFO_VALID_BIT_MASK 0x1\r
372	#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
373	#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
374	#define TARGER_ID_VALID_BIT_MASK 0x8\r
375	#define PRECISE_IP_VALID_BIT_MASK 0x10\r
376	\r
377	typedef struct {\r
378	UINT64 InfoValid : 1;\r
379	UINT64 ReqValid : 1;\r
380	UINT64 RespValid : 1;\r
381	UINT64 TargetValid : 1;\r
382	UINT64 IpValid : 1;\r
383	UINT64 Reserved : 59;\r
384	UINT64 Info;\r
385	UINT64 Req;\r
386	UINT64 Resp;\r
387	UINT64 Target;\r
388	UINT64 Ip;\r
389	} MOD_ERROR_INFO;\r
390	\r
391	typedef struct {\r
392	UINT8 CpuidInfo[40];\r
393	UINT8 Reserved;\r
394	} CPUID_INFO;\r
395	\r
396	typedef struct {\r
397	UINT64 FrLow;\r
398	UINT64 FrHigh;\r
399	} FR_STRUCT;\r
400	\r
401	#define MIN_STATE_VALID_BIT_MASK 0x1\r
402	#define BR_VALID_BIT_MASK 0x2\r
403	#define CR_VALID_BIT_MASK 0x4\r
404	#define AR_VALID_BIT_MASK 0x8\r
405	#define RR_VALID_BIT_MASK 0x10\r
406	#define FR_VALID_BIT_MASK 0x20\r
407	\r
408	typedef struct {\r
409	UINT64 ValidFieldBits;\r
410	UINT8 MinStateInfo[1024];\r
411	UINT64 Br[8];\r
412	UINT64 Cr[128];\r
413	UINT64 Ar[128];\r
414	UINT64 Rr[8];\r
415	FR_STRUCT Fr[128];\r
416	} PSI_STATIC_STRUCT;\r
417	\r
418	#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
419	#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
420	#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
421	#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
422	#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
423	\r
424	typedef struct {\r
425	SAL_SEC_HEADER SectionHeader;\r
426	UINT64 ValidationBits;\r
427	UINT64 ProcErrorMap;\r
428	UINT64 ProcStateParameter;\r
429	UINT64 ProcCrLid;\r
430	MOD_ERROR_INFO CacheError[15];\r
431	MOD_ERROR_INFO TlbError[15];\r
432	MOD_ERROR_INFO BusError[15];\r
433	MOD_ERROR_INFO RegFileCheck[15];\r
434	MOD_ERROR_INFO MsCheck[15];\r
435	CPUID_INFO CpuInfo;\r
436	PSI_STATIC_STRUCT PsiValidData;\r
437	} SAL_PROCESSOR_ERROR_RECORD;\r
438	\r
439	//\r
440	// Sal Platform memory Error Record\r
441	//\r
442	#define SAL_MEMORY_ERROR_RECORD_INFO \\r
443	{ \\r
444	0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
445	}\r
446	\r
447	#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
448	#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
449	#define MEMORY_ADDR_BIT_MASK 0x4\r
450	#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
451	#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
452	#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
453	#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
454	#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
455	#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
456	#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
457	#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
458	#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
459	#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
460	#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
461	#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
462	#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
463	#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
464	\r
465	typedef struct {\r
466	SAL_SEC_HEADER SectionHeader;\r
467	UINT64 ValidationBits;\r
468	UINT64 MemErrorStatus;\r
469	UINT64 MemPhysicalAddress;\r
470	UINT64 MemPhysicalAddressMask;\r
471	UINT16 MemNode;\r
472	UINT16 MemCard;\r
473	UINT16 MemModule;\r
474	UINT16 MemBank;\r
475	UINT16 MemDevice;\r
476	UINT16 MemRow;\r
477	UINT16 MemColumn;\r
478	UINT16 MemBitPosition;\r
479	UINT64 ModRequestorId;\r
480	UINT64 ModResponderId;\r
481	UINT64 ModTargetId;\r
482	UINT64 BusSpecificData;\r
483	UINT8 MemPlatformOemId[16];\r
484	} SAL_MEMORY_ERROR_RECORD;\r
485	\r
486	//\r
487	// PCI BUS Errors\r
488	//\r
489	#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
490	{ \\r
491	0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
492	}\r
493	\r
494	#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
495	#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
496	#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
497	#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
498	#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
499	#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
500	#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
501	#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
502	#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
503	#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
504	#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
505	\r
506	typedef struct {\r
507	UINT8 BusNumber;\r
508	UINT8 SegmentNumber;\r
509	} PCI_BUS_ID;\r
510	\r
511	typedef struct {\r
512	SAL_SEC_HEADER SectionHeader;\r
513	UINT64 ValidationBits;\r
514	UINT64 PciBusErrorStatus;\r
515	UINT16 PciBusErrorType;\r
516	PCI_BUS_ID PciBusId;\r
517	UINT32 Reserved;\r
518	UINT64 PciBusAddress;\r
519	UINT64 PciBusData;\r
520	UINT64 PciBusCommand;\r
521	UINT64 PciBusRequestorId;\r
522	UINT64 PciBusResponderId;\r
523	UINT64 PciBusTargetId;\r
524	UINT8 PciBusOemId[16];\r
525	} SAL_PCI_BUS_ERROR_RECORD;\r
526	\r
527	//\r
528	// PCI Component Errors\r
529	//\r
530	#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
531	{ \\r
532	0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
533	}\r
534	\r
535	#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
536	#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
537	#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
538	#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
539	#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
540	#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
541	\r
542	typedef struct {\r
543	UINT16 VendorId;\r
544	UINT16 DeviceId;\r
545	UINT8 ClassCode[3];\r
546	UINT8 FunctionNumber;\r
547	UINT8 DeviceNumber;\r
548	UINT8 BusNumber;\r
549	UINT8 SegmentNumber;\r
550	UINT8 Reserved[5];\r
551	} PCI_COMP_INFO;\r
552	\r
553	typedef struct {\r
554	SAL_SEC_HEADER SectionHeader;\r
555	UINT64 ValidationBits;\r
556	UINT64 PciComponentErrorStatus;\r
557	PCI_COMP_INFO PciComponentInfo;\r
558	UINT32 PciComponentMemNum;\r
559	UINT32 PciComponentIoNum;\r
560	UINT8 PciBusOemId[16];\r
561	} SAL_PCI_COMPONENT_ERROR_RECORD;\r
562	\r
563	//\r
564	// Sal Device Errors Info.\r
565	//\r
566	#define SAL_DEVICE_ERROR_RECORD_INFO \\r
567	{ \\r
568	0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
569	}\r
570	\r
571	#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
572	#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
573	#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
574	#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
575	#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
576	#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
577	#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
578	#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
579	#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
580	#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
581	\r
582	typedef struct {\r
583	SAL_SEC_HEADER SectionHeader;\r
584	UINT64 ValidationBits;\r
585	UINT16 SelRecordId;\r
586	UINT8 SelRecordType;\r
587	UINT32 TimeStamp;\r
588	UINT16 GeneratorId;\r
589	UINT8 EvmRevision;\r
590	UINT8 SensorType;\r
591	UINT8 SensorNum;\r
592	UINT8 EventDirType;\r
593	UINT8 Data1;\r
594	UINT8 Data2;\r
595	UINT8 Data3;\r
596	} SAL_DEVICE_ERROR_RECORD;\r
597	\r
598	//\r
599	// Sal SMBIOS Device Errors Info.\r
600	//\r
601	#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
602	{ \\r
603	0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
604	}\r
605	\r
606	#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
607	#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
608	#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
609	#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
610	\r
611	typedef struct {\r
612	SAL_SEC_HEADER SectionHeader;\r
613	UINT64 ValidationBits;\r
614	UINT8 SmbiosEventType;\r
615	UINT8 SmbiosLength;\r
616	UINT8 SmbiosBcdTimeStamp[6];\r
617	} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
618	\r
619	//\r
620	// Sal Platform Specific Errors Info.\r
621	//\r
622	#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
623	{ \\r
624	0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
625	}\r
626	\r
627	#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
628	#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
629	#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
630	#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
631	#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
632	#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
633	#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
634	#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
635	\r
636	typedef struct {\r
637	SAL_SEC_HEADER SectionHeader;\r
638	UINT64 ValidationBits;\r
639	UINT64 PlatformErrorStatus;\r
640	UINT64 PlatformRequestorId;\r
641	UINT64 PlatformResponderId;\r
642	UINT64 PlatformTargetId;\r
643	UINT64 PlatformBusSpecificData;\r
644	UINT8 OemComponentId[16];\r
645	} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
646	\r
647	//\r
648	// Union of all the possible Sal Record Types\r
649	//\r
650	typedef union {\r
651	SAL_RECORD_HEADER *RecordHeader;\r
652	SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
653	SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
654	SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
655	SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
656	SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
657	SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
658	SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
659	UINT8 *Raw;\r
660	} SAL_ERROR_RECORDS_POINTERS;\r
661	\r
662	#pragma pack()\r
663	\r
664	#endif\r