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1 | /** @file\r |
2 | This file contains definitions for SPD LPDDR.\r | |
3 | \r | |
4 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | @par Revision Reference:\r | |
14 | - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2\r | |
15 | http://www.jedec.org/standards-documents/docs/spd412m-2\r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef _SDRAM_SPD_LPDDR_H_\r | |
19 | #define _SDRAM_SPD_LPDDR_H_\r | |
20 | \r | |
21 | #pragma pack (push, 1)\r | |
22 | \r | |
23 | typedef union {\r | |
24 | struct {\r | |
25 | UINT8 BytesUsed : 4; ///< Bits 3:0\r | |
26 | UINT8 BytesTotal : 3; ///< Bits 6:4\r | |
27 | UINT8 CrcCoverage : 1; ///< Bits 7:7\r | |
28 | } Bits;\r | |
29 | UINT8 Data;\r | |
30 | } SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;\r | |
31 | \r | |
32 | typedef union {\r | |
33 | struct {\r | |
34 | UINT8 Minor : 4; ///< Bits 3:0\r | |
35 | UINT8 Major : 4; ///< Bits 7:4\r | |
36 | } Bits;\r | |
37 | UINT8 Data;\r | |
38 | } SPD_LPDDR_REVISION_STRUCT;\r | |
39 | \r | |
40 | typedef union {\r | |
41 | struct {\r | |
42 | UINT8 Type : 8; ///< Bits 7:0\r | |
43 | } Bits;\r | |
44 | UINT8 Data;\r | |
45 | } SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;\r | |
46 | \r | |
47 | typedef union {\r | |
48 | struct {\r | |
49 | UINT8 ModuleType : 4; ///< Bits 3:0\r | |
50 | UINT8 HybridMedia : 3; ///< Bits 6:4\r | |
51 | UINT8 Hybrid : 1; ///< Bits 7:7\r | |
52 | } Bits;\r | |
53 | UINT8 Data;\r | |
54 | } SPD_LPDDR_MODULE_TYPE_STRUCT;\r | |
55 | \r | |
56 | typedef union {\r | |
57 | struct {\r | |
58 | UINT8 Density : 4; ///< Bits 3:0\r | |
59 | UINT8 BankAddress : 2; ///< Bits 5:4\r | |
60 | UINT8 BankGroup : 2; ///< Bits 7:6\r | |
61 | } Bits;\r | |
62 | UINT8 Data;\r | |
63 | } SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;\r | |
64 | \r | |
65 | typedef union {\r | |
66 | struct {\r | |
67 | UINT8 ColumnAddress : 3; ///< Bits 2:0\r | |
68 | UINT8 RowAddress : 3; ///< Bits 5:3\r | |
69 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
70 | } Bits;\r | |
71 | UINT8 Data;\r | |
72 | } SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;\r | |
73 | \r | |
74 | typedef union {\r | |
75 | struct {\r | |
76 | UINT8 SignalLoading : 2; ///< Bits 1:0\r | |
77 | UINT8 ChannelsPerDie : 2; ///< Bits 3:2\r | |
78 | UINT8 DieCount : 3; ///< Bits 6:4\r | |
79 | UINT8 SdramPackageType : 1; ///< Bits 7:7\r | |
80 | } Bits;\r | |
81 | UINT8 Data;\r | |
82 | } SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;\r | |
83 | \r | |
84 | typedef union {\r | |
85 | struct {\r | |
86 | UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r | |
87 | UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r | |
88 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
89 | } Bits;\r | |
90 | UINT8 Data;\r | |
91 | } SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;\r | |
92 | \r | |
93 | typedef union {\r | |
94 | struct {\r | |
95 | UINT8 Reserved : 8; ///< Bits 7:0\r | |
96 | } Bits;\r | |
97 | UINT8 Data;\r | |
98 | } SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;\r | |
99 | \r | |
100 | typedef union {\r | |
101 | struct {\r | |
102 | UINT8 Reserved : 5; ///< Bits 4:0\r | |
103 | UINT8 SoftPPR : 1; ///< Bits 5:5\r | |
104 | UINT8 PostPackageRepair : 2; ///< Bits 7:6\r | |
105 | } Bits;\r | |
106 | UINT8 Data;\r | |
107 | } SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r | |
108 | \r | |
109 | typedef union {\r | |
110 | struct {\r | |
111 | UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r | |
112 | UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r | |
113 | UINT8 OperationAt1_10 : 1; ///< Bits 2:2\r | |
114 | UINT8 EndurantAt1_10 : 1; ///< Bits 3:3\r | |
115 | UINT8 OperationAtTBD2V : 1; ///< Bits 4:4\r | |
116 | UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5\r | |
117 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
118 | } Bits;\r | |
119 | UINT8 Data;\r | |
120 | } SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;\r | |
121 | \r | |
122 | typedef union {\r | |
123 | struct {\r | |
124 | UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r | |
125 | UINT8 RankCount : 3; ///< Bits 5:3\r | |
126 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
127 | } Bits;\r | |
128 | UINT8 Data;\r | |
129 | } SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;\r | |
130 | \r | |
131 | typedef union {\r | |
132 | struct {\r | |
133 | UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r | |
134 | UINT8 BusWidthExtension : 2; ///< Bits 4:3\r | |
135 | UINT8 NumberofChannels : 3; ///< Bits 7:5\r | |
136 | } Bits;\r | |
137 | UINT8 Data;\r | |
138 | } SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r | |
139 | \r | |
140 | typedef union {\r | |
141 | struct {\r | |
142 | UINT8 Reserved : 7; ///< Bits 6:0\r | |
143 | UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r | |
144 | } Bits;\r | |
145 | UINT8 Data;\r | |
146 | } SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;\r | |
147 | \r | |
148 | typedef union {\r | |
149 | struct {\r | |
150 | UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r | |
151 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
152 | } Bits;\r | |
153 | UINT8 Data;\r | |
154 | } SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;\r | |
155 | \r | |
156 | typedef union {\r | |
157 | struct {\r | |
158 | UINT8 ChipSelectLoading : 3; ///< Bits 2:0\r | |
159 | UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3\r | |
160 | UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6\r | |
161 | } Bits;\r | |
162 | UINT8 Data;\r | |
163 | } SPD_LPDDR_SIGNAL_LOADING_STRUCT;\r | |
164 | \r | |
165 | typedef union {\r | |
166 | struct {\r | |
167 | UINT8 Fine : 2; ///< Bits 1:0\r | |
168 | UINT8 Medium : 2; ///< Bits 3:2\r | |
169 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
170 | } Bits;\r | |
171 | UINT8 Data;\r | |
172 | } SPD_LPDDR_TIMEBASE_STRUCT;\r | |
173 | \r | |
174 | typedef union {\r | |
175 | struct {\r | |
176 | UINT8 tCKmin : 8; ///< Bits 7:0\r | |
177 | } Bits;\r | |
178 | UINT8 Data;\r | |
179 | } SPD_LPDDR_TCK_MIN_MTB_STRUCT;\r | |
180 | \r | |
181 | typedef union {\r | |
182 | struct {\r | |
183 | UINT8 tCKmax : 8; ///< Bits 7:0\r | |
184 | } Bits;\r | |
185 | UINT8 Data;\r | |
186 | } SPD_LPDDR_TCK_MAX_MTB_STRUCT;\r | |
187 | \r | |
188 | typedef union {\r | |
189 | struct {\r | |
190 | UINT32 Cl3 : 1; ///< Bits 0:0\r | |
191 | UINT32 Cl6 : 1; ///< Bits 1:1\r | |
192 | UINT32 Cl8 : 1; ///< Bits 2:2\r | |
193 | UINT32 Cl9 : 1; ///< Bits 3:3\r | |
194 | UINT32 Cl10 : 1; ///< Bits 4:4\r | |
195 | UINT32 Cl11 : 1; ///< Bits 5:5\r | |
196 | UINT32 Cl12 : 1; ///< Bits 6:6\r | |
197 | UINT32 Cl14 : 1; ///< Bits 7:7\r | |
198 | UINT32 Cl16 : 1; ///< Bits 8:8\r | |
199 | UINT32 Reserved0 : 1; ///< Bits 9:9\r | |
200 | UINT32 Cl20 : 1; ///< Bits 10:10\r | |
201 | UINT32 Cl22 : 1; ///< Bits 11:11\r | |
202 | UINT32 Cl24 : 1; ///< Bits 12:12\r | |
203 | UINT32 Reserved1 : 1; ///< Bits 13:13\r | |
204 | UINT32 Cl28 : 1; ///< Bits 14:14\r | |
205 | UINT32 Reserved2 : 1; ///< Bits 15:15\r | |
206 | UINT32 Cl32 : 1; ///< Bits 16:16\r | |
207 | UINT32 Reserved3 : 1; ///< Bits 17:17\r | |
208 | UINT32 Cl36 : 1; ///< Bits 18:18\r | |
209 | UINT32 Reserved4 : 1; ///< Bits 19:19\r | |
210 | UINT32 Cl40 : 1; ///< Bits 20:20\r | |
211 | UINT32 Reserved5 : 11; ///< Bits 31:21\r | |
212 | } Bits;\r | |
213 | UINT32 Data;\r | |
214 | UINT16 Data16[2];\r | |
215 | UINT8 Data8[4];\r | |
216 | } SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;\r | |
217 | \r | |
218 | typedef union {\r | |
219 | struct {\r | |
220 | UINT8 tAAmin : 8; ///< Bits 7:0\r | |
221 | } Bits;\r | |
222 | UINT8 Data;\r | |
223 | } SPD_LPDDR_TAA_MIN_MTB_STRUCT;\r | |
224 | \r | |
225 | typedef union {\r | |
226 | struct {\r | |
227 | UINT8 ReadLatencyMode : 2; ///< Bits 1:0\r | |
228 | UINT8 WriteLatencySet : 2; ///< Bits 3:2\r | |
229 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
230 | } Bits;\r | |
231 | UINT8 Data;\r | |
232 | } SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;\r | |
233 | \r | |
234 | typedef union {\r | |
235 | struct {\r | |
236 | UINT8 tRCDmin : 8; ///< Bits 7:0\r | |
237 | } Bits;\r | |
238 | UINT8 Data;\r | |
239 | } SPD_LPDDR_TRCD_MIN_MTB_STRUCT;\r | |
240 | \r | |
241 | typedef union {\r | |
242 | struct {\r | |
243 | UINT8 tRPab : 8; ///< Bits 7:0\r | |
244 | } Bits;\r | |
245 | UINT8 Data;\r | |
246 | } SPD_LPDDR_TRP_AB_MTB_STRUCT;\r | |
247 | \r | |
248 | typedef union {\r | |
249 | struct {\r | |
250 | UINT8 tRPpb : 8; ///< Bits 7:0\r | |
251 | } Bits;\r | |
252 | UINT8 Data;\r | |
253 | } SPD_LPDDR_TRP_PB_MTB_STRUCT;\r | |
254 | \r | |
255 | typedef union {\r | |
256 | struct {\r | |
257 | UINT16 tRFCab : 16; ///< Bits 15:0\r | |
258 | } Bits;\r | |
259 | UINT16 Data;\r | |
260 | UINT8 Data8[2];\r | |
261 | } SPD_LPDDR_TRFC_AB_MTB_STRUCT;\r | |
262 | \r | |
263 | typedef union {\r | |
264 | struct {\r | |
265 | UINT16 tRFCpb : 16; ///< Bits 15:0\r | |
266 | } Bits;\r | |
267 | UINT16 Data;\r | |
268 | UINT8 Data8[2];\r | |
269 | } SPD_LPDDR_TRFC_PB_MTB_STRUCT;\r | |
270 | \r | |
271 | typedef union {\r | |
272 | struct {\r | |
273 | UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r | |
274 | UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r | |
275 | UINT8 PackageRankMap : 2; ///< Bits 7:6\r | |
276 | } Bits;\r | |
277 | UINT8 Data;\r | |
278 | } SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r | |
279 | \r | |
280 | typedef union {\r | |
281 | struct {\r | |
282 | INT8 tRPpbFine : 8; ///< Bits 7:0\r | |
283 | } Bits;\r | |
284 | INT8 Data;\r | |
285 | } SPD_LPDDR_TRP_PB_FTB_STRUCT;\r | |
286 | \r | |
287 | typedef union {\r | |
288 | struct {\r | |
289 | INT8 tRPabFine : 8; ///< Bits 7:0\r | |
290 | } Bits;\r | |
291 | INT8 Data;\r | |
292 | } SPD_LPDDR_TRP_AB_FTB_STRUCT;\r | |
293 | \r | |
294 | typedef union {\r | |
295 | struct {\r | |
296 | INT8 tRCDminFine : 8; ///< Bits 7:0\r | |
297 | } Bits;\r | |
298 | INT8 Data;\r | |
299 | } SPD_LPDDR_TRCD_MIN_FTB_STRUCT;\r | |
300 | \r | |
301 | typedef union {\r | |
302 | struct {\r | |
303 | INT8 tAAminFine : 8; ///< Bits 7:0\r | |
304 | } Bits;\r | |
305 | INT8 Data;\r | |
306 | } SPD_LPDDR_TAA_MIN_FTB_STRUCT;\r | |
307 | \r | |
308 | typedef union {\r | |
309 | struct {\r | |
310 | INT8 tCKmaxFine : 8; ///< Bits 7:0\r | |
311 | } Bits;\r | |
312 | INT8 Data;\r | |
313 | } SPD_LPDDR_TCK_MAX_FTB_STRUCT;\r | |
314 | \r | |
315 | typedef union {\r | |
316 | struct {\r | |
317 | INT8 tCKminFine : 8; ///< Bits 7:0\r | |
318 | } Bits;\r | |
319 | INT8 Data;\r | |
320 | } SPD_LPDDR_TCK_MIN_FTB_STRUCT;\r | |
321 | \r | |
322 | typedef union {\r | |
323 | struct {\r | |
324 | UINT16 ContinuationCount : 7; ///< Bits 6:0\r | |
325 | UINT16 ContinuationParity : 1; ///< Bits 7:7\r | |
326 | UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r | |
327 | } Bits;\r | |
328 | UINT16 Data;\r | |
329 | UINT8 Data8[2];\r | |
330 | } SPD_LPDDR_MANUFACTURER_ID_CODE;\r | |
331 | \r | |
332 | typedef struct {\r | |
333 | UINT8 Location; ///< Module Manufacturing Location\r | |
334 | } SPD_LPDDR_MANUFACTURING_LOCATION;\r | |
335 | \r | |
336 | typedef struct {\r | |
337 | UINT8 Year; ///< Year represented in BCD (00h = 2000)\r | |
338 | UINT8 Week; ///< Year represented in BCD (47h = week 47)\r | |
339 | } SPD_LPDDR_MANUFACTURING_DATE;\r | |
340 | \r | |
341 | typedef union {\r | |
342 | UINT32 Data;\r | |
343 | UINT16 SerialNumber16[2];\r | |
344 | UINT8 SerialNumber8[4];\r | |
345 | } SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;\r | |
346 | \r | |
347 | typedef struct {\r | |
348 | SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r | |
349 | SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r | |
350 | SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r | |
351 | SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r | |
352 | } SPD_LPDDR_UNIQUE_MODULE_ID;\r | |
353 | \r | |
354 | typedef union {\r | |
355 | struct {\r | |
356 | UINT8 FrontThickness : 4; ///< Bits 3:0\r | |
357 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
358 | } Bits;\r | |
359 | UINT8 Data;\r | |
360 | } SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;\r | |
361 | \r | |
362 | typedef union {\r | |
363 | struct {\r | |
364 | UINT8 Height : 5; ///< Bits 4:0\r | |
365 | UINT8 RawCardExtension : 3; ///< Bits 7:5\r | |
366 | } Bits;\r | |
367 | UINT8 Data;\r | |
368 | } SPD_LPDDR_MODULE_NOMINAL_HEIGHT;\r | |
369 | \r | |
370 | typedef union {\r | |
371 | struct {\r | |
372 | UINT8 Card : 5; ///< Bits 4:0\r | |
373 | UINT8 Revision : 2; ///< Bits 6:5\r | |
374 | UINT8 Extension : 1; ///< Bits 7:7\r | |
375 | } Bits;\r | |
376 | UINT8 Data;\r | |
377 | } SPD_LPDDR_REFERENCE_RAW_CARD;\r | |
378 | \r | |
379 | typedef union {\r | |
380 | UINT16 Crc[1];\r | |
381 | UINT8 Data8[2];\r | |
382 | } SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;\r | |
383 | \r | |
384 | typedef struct {\r | |
385 | SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r | |
386 | SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision\r | |
387 | SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r | |
388 | SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r | |
389 | SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r | |
390 | SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r | |
391 | SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type\r | |
392 | SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r | |
393 | SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r | |
394 | SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r | |
395 | UINT8 Reserved0; ///< 10 Reserved\r | |
396 | SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r | |
397 | SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r | |
398 | SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r | |
399 | SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r | |
400 | SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r | |
401 | SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading\r | |
402 | SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r | |
403 | SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r | |
404 | SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r | |
405 | SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r | |
406 | SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r | |
407 | SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options\r | |
408 | SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)\r | |
409 | SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks\r | |
410 | SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank\r | |
411 | SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks\r | |
412 | SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank\r | |
413 | UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved\r | |
414 | SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r | |
415 | UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved\r | |
416 | SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank\r | |
417 | SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks\r | |
418 | SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r | |
419 | SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r | |
420 | SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)\r | |
421 | SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r | |
422 | SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r | |
423 | } SPD_LPDDR_BASE_SECTION;\r | |
424 | \r | |
425 | typedef struct {\r | |
426 | SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r | |
427 | SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r | |
428 | SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r | |
429 | UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved\r | |
430 | SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r | |
431 | } SPD_LPDDR_MODULE_LPDIMM;\r | |
432 | \r | |
433 | typedef struct {\r | |
434 | SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types\r | |
435 | } SPD_LPDDR_MODULE_SPECIFIC;\r | |
436 | \r | |
437 | typedef struct {\r | |
438 | UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r | |
439 | } SPD_LPDDR_MODULE_PART_NUMBER;\r | |
440 | \r | |
441 | typedef struct {\r | |
442 | UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r | |
443 | } SPD_LPDDR_MANUFACTURER_SPECIFIC;\r | |
444 | \r | |
445 | typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code\r | |
446 | typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping\r | |
447 | \r | |
448 | typedef struct {\r | |
449 | SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r | |
450 | SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r | |
451 | SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r | |
452 | SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r | |
453 | SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r | |
454 | SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r | |
455 | UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved\r | |
456 | } SPD_LPDDR_MANUFACTURING_DATA;\r | |
457 | \r | |
458 | typedef struct {\r | |
459 | UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable\r | |
460 | } SPD_LPDDR_END_USER_SECTION;\r | |
461 | \r | |
462 | ///\r | |
463 | /// LPDDR Serial Presence Detect structure\r | |
464 | ///\r | |
465 | typedef struct {\r | |
466 | SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r | |
467 | SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r | |
468 | UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters\r | |
469 | SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r | |
470 | SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r | |
471 | } SPD_LPDDR;\r | |
472 | \r | |
473 | #pragma pack (pop)\r | |
474 | #endif\r |