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a7ed1e2e | 1 | /** @file\r |
b219e2cd | 2 | This file declares the SMBus definitions defined in SmBus Specification V2.0\r |
992f22b9 | 3 | and defined in PI1.0 specification volume 5.\r |
a7ed1e2e | 4 | \r |
9095d37b | 5 | Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a7ed1e2e | 7 | \r |
a7ed1e2e | 8 | **/\r |
9 | \r | |
10 | #ifndef _SMBUS_H_\r | |
11 | #define _SMBUS_H_\r | |
12 | \r | |
1bc5d021 | 13 | ///\r |
14 | /// UDID of SMBUS device.\r | |
15 | ///\r | |
a7ed1e2e | 16 | typedef struct {\r |
2f88bd3a MK |
17 | UINT32 VendorSpecificId;\r |
18 | UINT16 SubsystemDeviceId;\r | |
19 | UINT16 SubsystemVendorId;\r | |
20 | UINT16 Interface;\r | |
21 | UINT16 DeviceId;\r | |
22 | UINT16 VendorId;\r | |
23 | UINT8 VendorRevision;\r | |
24 | UINT8 DeviceCapabilities;\r | |
a7ed1e2e | 25 | } EFI_SMBUS_UDID;\r |
26 | \r | |
1bc5d021 | 27 | ///\r |
4135253b | 28 | /// Smbus Device Address\r |
1bc5d021 | 29 | ///\r |
a7ed1e2e | 30 | typedef struct {\r |
992f22b9 LG |
31 | ///\r |
32 | /// The SMBUS hardware address to which the SMBUS device is preassigned or allocated.\r | |
33 | ///\r | |
2f88bd3a | 34 | UINTN SmbusDeviceAddress : 7;\r |
a7ed1e2e | 35 | } EFI_SMBUS_DEVICE_ADDRESS;\r |
36 | \r | |
27a57d47 LG |
37 | typedef struct {\r |
38 | ///\r | |
39 | /// The SMBUS hardware address to which the SMBUS device is preassigned or\r | |
40 | /// allocated. Type EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute().\r | |
41 | ///\r | |
2f88bd3a | 42 | EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;\r |
27a57d47 LG |
43 | ///\r |
44 | /// The SMBUS Unique Device Identifier (UDID) as defined in EFI_SMBUS_UDID.\r | |
45 | /// Type EFI_SMBUS_UDID is defined in EFI_PEI_SMBUS2_PPI.ArpDevice().\r | |
46 | ///\r | |
2f88bd3a | 47 | EFI_SMBUS_UDID SmbusDeviceUdid;\r |
27a57d47 LG |
48 | } EFI_SMBUS_DEVICE_MAP;\r |
49 | \r | |
4135253b | 50 | ///\r |
51 | /// Smbus Operations\r | |
52 | ///\r | |
992f22b9 | 53 | typedef enum _EFI_SMBUS_OPERATION {\r |
a7ed1e2e | 54 | EfiSmbusQuickRead,\r |
55 | EfiSmbusQuickWrite,\r | |
56 | EfiSmbusReceiveByte,\r | |
57 | EfiSmbusSendByte,\r | |
58 | EfiSmbusReadByte,\r | |
59 | EfiSmbusWriteByte,\r | |
60 | EfiSmbusReadWord,\r | |
61 | EfiSmbusWriteWord,\r | |
62 | EfiSmbusReadBlock,\r | |
63 | EfiSmbusWriteBlock,\r | |
64 | EfiSmbusProcessCall,\r | |
65 | EfiSmbusBWBRProcessCall\r | |
66 | } EFI_SMBUS_OPERATION;\r | |
67 | \r | |
992f22b9 LG |
68 | ///\r |
69 | /// EFI_SMBUS_DEVICE_COMMAND\r | |
70 | ///\r | |
2f88bd3a | 71 | typedef UINTN EFI_SMBUS_DEVICE_COMMAND;\r |
992f22b9 | 72 | \r |
a7ed1e2e | 73 | #endif\r |