[mirror_edk2.git] / MdePkg / Include / IndustryStandard / TpmPtp.h

/** @file\r
  Platform TPM Profile Specification definition for TPM2.0.\r
  It covers both FIFO and CRB interface.\r
\r
Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _TPM_PTP_H_\r
#define _TPM_PTP_H_\r
\r
//\r
// PTP FIFO definition\r
//\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in PTP specification Chapter 5\r
//\r
typedef struct {\r
  ///\r
  /// Used to gain ownership for this particular port.\r
  ///\r
  UINT8                             Access;             // 0\r
  UINT8                             Reserved1[7];       // 1\r
  ///\r
  /// Controls interrupts.\r
  ///\r
  UINT32                            IntEnable;          // 8\r
  ///\r
  /// SIRQ vector to be used by the TPM.\r
  ///\r
  UINT8                             IntVector;          // 0ch\r
  UINT8                             Reserved2[3];       // 0dh\r
  ///\r
  /// What caused interrupt.\r
  ///\r
  UINT32                            IntSts;             // 10h\r
  ///\r
  /// Shows which interrupts are supported by that particular TPM.\r
  ///\r
  UINT32                            InterfaceCapability;// 14h\r
  ///\r
  /// Status Register. Provides status of the TPM.\r
  ///\r
  UINT8                             Status;             // 18h\r
  ///\r
  /// Number of consecutive writes that can be done to the TPM.\r
  ///\r
  UINT16                            BurstCount;         // 19h\r
  ///\r
  /// Additional Status Register.\r
  ///\r
  UINT8                             StatusEx;           // 1Bh\r
  UINT8                             Reserved3[8];\r
  ///\r
  /// Read or write FIFO, depending on transaction.\r
  ///\r
  UINT32                            DataFifo;           // 24h\r
  UINT8                             Reserved4[8];       // 28h\r
  ///\r
  /// Used to identify the Interface types supported by the TPM.\r
  ///\r
  UINT32                            InterfaceId;        // 30h\r
  UINT8                             Reserved5[0x4c];    // 34h\r
  ///\r
  /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r
  ///\r
  UINT32                            XDataFifo;          // 80h\r
  UINT8                             Reserved6[0xe7c];   // 84h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16                            Vid;                // 0f00h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16                            Did;                // 0f02h\r
  ///\r
  /// Revision ID\r
  ///\r
  UINT8                             Rid;                // 0f04h\r
  UINT8                             Reserved[0xfb];     // 0f05h\r
} PTP_FIFO_REGISTERS;\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
typedef PTP_FIFO_REGISTERS  *PTP_FIFO_REGISTERS_PTR;\r
\r
//\r
// Define bits of FIFO Interface Identifier Register\r
//\r
typedef union {\r
  struct {\r
    UINT32   InterfaceType:4;\r
    UINT32   InterfaceVersion:4;\r
    UINT32   CapLocality:1;\r
    UINT32   Reserved1:2;\r
    UINT32   CapDataXferSizeSupport:2;\r
    UINT32   CapFIFO:1;\r
    UINT32   CapCRB:1;\r
    UINT32   CapIFRes:2;\r
    UINT32   InterfaceSelector:2;\r
    UINT32   IntfSelLock:1;\r
    UINT32   Reserved2:4;\r
    UINT32   Reserved3:8;\r
  } Bits;\r
  UINT32   Uint32;\r
} PTP_FIFO_INTERFACE_IDENTIFIER;\r
\r
//\r
// Define bits of FIFO Interface Capability Register\r
//\r
typedef union {\r
  struct {\r
    UINT32   DataAvailIntSupport:1;\r
    UINT32   StsValidIntSupport:1;\r
    UINT32   LocalityChangeIntSupport:1;\r
    UINT32   InterruptLevelHigh:1;\r
    UINT32   InterruptLevelLow:1;\r
    UINT32   InterruptEdgeRising:1;\r
    UINT32   InterruptEdgeFalling:1;\r
    UINT32   CommandReadyIntSupport:1;\r
    UINT32   BurstCountStatic:1;\r
    UINT32   DataTransferSizeSupport:2;\r
    UINT32   Reserved:17;\r
    UINT32   InterfaceVersion:3;\r
    UINT32   Reserved2:1;\r
  } Bits;\r
  UINT32   Uint32;\r
} PTP_FIFO_INTERFACE_CAPABILITY;\r
\r
///\r
/// InterfaceVersion\r
///\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12  0x0\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13  0x2\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP     0x3\r
\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
#define PTP_FIFO_VALID                BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
#define PTP_FIFO_ACC_ACTIVE           BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
#define PTP_FIFO_ACC_SEIZED           BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
#define PTP_FIFO_ACC_SEIZE            BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
#define PTP_FIFO_ACC_PENDIND          BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
#define PTP_FIFO_ACC_RQUUSE           BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
#define PTP_FIFO_ACC_ESTABLISH        BIT0\r
\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
#define PTP_FIFO_STS_VALID            BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
#define PTP_FIFO_STS_READY            BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
#define PTP_FIFO_STS_GO               BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
#define PTP_FIFO_STS_DATA             BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
#define PTP_FIFO_STS_EXPECT           BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
#define PTP_FIFO_STS_SELFTEST_DONE    BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
#define PTP_FIFO_STS_RETRY            BIT1\r
\r
///\r
/// TPM Family Identifier.\r
/// 00: TPM 1.2 Family\r
/// 01: TPM 2.0 Family\r
///\r
#define PTP_FIFO_STS_EX_TPM_FAMILY    (BIT2 | BIT3)\r
#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET    (2)\r
#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12    (0)\r
#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20    (BIT2)\r
///\r
/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r
/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r
///\r
#define PTP_FIFO_STS_EX_CANCEL        BIT0\r
\r
\r
//\r
// PTP CRB definition\r
//\r
\r
//\r
// Set structure alignment to 1-byte\r
//\r
#pragma pack (1)\r
\r
//\r
// Register set map as specified in PTP specification Chapter 5\r
//\r
typedef struct {\r
  ///\r
  /// Used to determine current state of Locality of the TPM.\r
  ///\r
  UINT32                            LocalityState;             // 0\r
  UINT8                             Reserved1[4];              // 4\r
  ///\r
  /// Used to gain control of the TPM by this Locality.\r
  ///\r
  UINT32                            LocalityControl;           // 8\r
  ///\r
  /// Used to determine whether Locality has been granted or Seized.\r
  ///\r
  UINT32                            LocalityStatus;            // 0ch\r
  UINT8                             Reserved2[0x20];           // 10h\r
  ///\r
  /// Used to identify the Interface types supported by the TPM.\r
  ///\r
  UINT32                            InterfaceId;               // 30h\r
  ///\r
  /// Vendor ID\r
  ///\r
  UINT16                            Vid;                       // 34h\r
  ///\r
  /// Device ID\r
  ///\r
  UINT16                            Did;                       // 36h\r
  ///\r
  /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r
  ///\r
  UINT64                            CrbControlExtension;       // 38h\r
  ///\r
  /// Register used to initiate transactions for the CRB interface.\r
  ///\r
  UINT32                            CrbControlRequest;         // 40h\r
  ///\r
  /// Register used by the TPM to provide status of the CRB interface.\r
  ///\r
  UINT32                            CrbControlStatus;          // 44h\r
  ///\r
  /// Register used by software to cancel command processing.\r
  ///\r
  UINT32                            CrbControlCancel;          // 48h\r
  ///\r
  /// Register used to indicate presence of command or response data in the CRB buffer.\r
  ///\r
  UINT32                            CrbControlStart;           // 4Ch\r
  ///\r
  /// Register used to configure and respond to interrupts.\r
  ///\r
  UINT32                            CrbInterruptEnable;        // 50h\r
  UINT32                            CrbInterruptStatus;        // 54h\r
  ///\r
  /// Size of the Command buffer.\r
  ///\r
  UINT32                            CrbControlCommandSize;     // 58h\r
  ///\r
  /// Command buffer start address\r
  ///\r
  UINT32                            CrbControlCommandAddressLow;   // 5Ch\r
  UINT32                            CrbControlCommandAddressHigh;  // 60h\r
  ///\r
  /// Size of the Response buffer\r
  ///\r
  UINT32                            CrbControlResponseSize;    // 64h\r
  ///\r
  /// Address of the start of the Response buffer\r
  ///\r
  UINT64                            CrbControlResponseAddrss;  // 68h\r
  UINT8                             Reserved4[0x10];           // 70h\r
  ///\r
  /// Command/Response Data may be defined as large as 3968 (0xF80).\r
  ///\r
  UINT8                             CrbDataBuffer[0xF80];      // 80h\r
} PTP_CRB_REGISTERS;\r
\r
//\r
// Define pointer types used to access CRB registers on PTP\r
//\r
typedef PTP_CRB_REGISTERS  *PTP_CRB_REGISTERS_PTR;\r
\r
//\r
// Define bits of CRB Interface Identifier Register\r
//\r
typedef union {\r
  struct {\r
    UINT32   InterfaceType:4;\r
    UINT32   InterfaceVersion:4;\r
    UINT32   CapLocality:1;\r
    UINT32   CapCRBIdleBypass:1;\r
    UINT32   Reserved1:1;\r
    UINT32   CapDataXferSizeSupport:2;\r
    UINT32   CapFIFO:1;\r
    UINT32   CapCRB:1;\r
    UINT32   CapIFRes:2;\r
    UINT32   InterfaceSelector:2;\r
    UINT32   IntfSelLock:1;\r
    UINT32   Reserved2:4;\r
    UINT32   Rid:8;\r
  } Bits;\r
  UINT32   Uint32;\r
} PTP_CRB_INTERFACE_IDENTIFIER;\r
\r
///\r
/// InterfaceType\r
///\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO  0x0\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB   0x1\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS   0xF\r
\r
///\r
/// InterfaceVersion\r
///\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO  0x0\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB   0x1\r
\r
///\r
/// InterfaceSelector\r
///\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO  0x0\r
#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB   0x1\r
\r
//\r
// Define bits of Locality State Register\r
//\r
\r
///\r
/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r
///\r
#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS       BIT7\r
\r
///\r
/// 000 - Locality 0\r
/// 001 - Locality 1\r
/// 010 - Locality 2\r
/// 011 - Locality 3\r
/// 100 - Locality 4\r
///\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK       (BIT2 | BIT3 | BIT4)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0          (0)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1          (BIT2)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2          (BIT3)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3          (BIT2 | BIT3)\r
#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4          (BIT4)\r
\r
///\r
/// A 0 indicates to the host that no locality is assigned.\r
/// A 1 indicates a locality has been assigned.\r
///\r
#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED          BIT1\r
\r
///\r
/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r
/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r
///\r
#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED            BIT0\r
\r
//\r
// Define bits of Locality Control Register\r
//\r
\r
///\r
/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT  BIT3\r
\r
///\r
/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_SEIZE                    BIT2\r
\r
///\r
/// Writes (1): The active Locality is done with the TPM.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH               BIT1\r
\r
///\r
/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r
///\r
#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS           BIT0\r
\r
//\r
// Define bits of Locality Status Register\r
//\r
\r
///\r
/// 0: A higher locality has not initiated a Seize arbitration process.\r
/// 1: A higher locality has Seized the TPM from this locality.\r
///\r
#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED               BIT1\r
\r
///\r
/// 0: Locality has not been granted to the TPM.\r
/// 1: Locality has been granted access to the TPM\r
///\r
#define PTP_CRB_LOCALITY_STATUS_GRANTED                   BIT0\r
\r
//\r
// Define bits of CRB Control Area Request Register\r
//\r
\r
///\r
/// Used by Software to indicate transition the TPM to and from the Idle state\r
/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle\r
/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r
/// TPM SHALL complete this transition within TIMEOUT_C.\r
///\r
#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE              BIT1\r
\r
///\r
/// Used by Software to request the TPM transition to the Ready State.\r
/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.\r
/// 0: Cleared to 0 by TPM to acknowledge the request.\r
/// TPM SHALL complete this transition within TIMEOUT_C.\r
///\r
#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY        BIT0\r
\r
//\r
// Define bits of CRB Control Area Status Register\r
//\r
\r
///\r
/// Used by TPM to indicate it is in the Idle State\r
/// 1: Set by TPM when in the Idle State\r
/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r
/// SHALL be cleared by TIMEOUT_C.\r
///\r
#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE              BIT1\r
\r
///\r
/// Used by the TPM to indicate current status.\r
/// 1: Set by TPM to indicate a FATAL Error\r
/// 0: Indicates TPM is operational\r
///\r
#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS            BIT0\r
\r
//\r
// Define bits of CRB Control Cancel Register\r
//\r
\r
///\r
/// Used by software to cancel command processing Reads return correct value\r
/// Writes (0000 0001h): Cancel a command\r
/// Writes (0000 0000h): Clears field when command has been cancelled\r
///\r
#define PTP_CRB_CONTROL_CANCEL                            BIT0\r
\r
//\r
// Define bits of CRB Control Start Register\r
//\r
\r
///\r
/// When set by software, indicates a command is ready for processing.\r
/// Writes (0000 0001h): TPM transitions to Command Execution\r
/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r
///\r
#define PTP_CRB_CONTROL_START                             BIT0\r
\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
//\r
// Default TimeOut value\r
//\r
#define PTP_TIMEOUT_A               (750 * 1000)   // 750ms\r
#define PTP_TIMEOUT_B               (2000 * 1000)  // 2s\r
#define PTP_TIMEOUT_C               (200 * 1000)   // 200ms\r
#define PTP_TIMEOUT_D               (30 * 1000)    // 30ms\r
\r
#endif\r
Commit	Line	Data
fb7abaca JY	1	/** @file\r
	2	Platform TPM Profile Specification definition for TPM2.0.\r
	3	It covers both FIFO and CRB interface.\r
	4	\r
714eedc5	5	Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
9344f092	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
fb7abaca JY	7	\r
	8	**/\r
	9	\r
	10	#ifndef _TPM_PTP_H_\r
	11	#define _TPM_PTP_H_\r
	12	\r
	13	//\r
	14	// PTP FIFO definition\r
	15	//\r
	16	\r
	17	//\r
	18	// Set structure alignment to 1-byte\r
	19	//\r
	20	#pragma pack (1)\r
	21	\r
	22	//\r
	23	// Register set map as specified in PTP specification Chapter 5\r
	24	//\r
	25	typedef struct {\r
	26	///\r
	27	/// Used to gain ownership for this particular port.\r
	28	///\r
	29	UINT8 Access; // 0\r
	30	UINT8 Reserved1[7]; // 1\r
	31	///\r
	32	/// Controls interrupts.\r
	33	///\r
	34	UINT32 IntEnable; // 8\r
	35	///\r
	36	/// SIRQ vector to be used by the TPM.\r
	37	///\r
	38	UINT8 IntVector; // 0ch\r
	39	UINT8 Reserved2[3]; // 0dh\r
	40	///\r
	41	/// What caused interrupt.\r
	42	///\r
	43	UINT32 IntSts; // 10h\r
	44	///\r
	45	/// Shows which interrupts are supported by that particular TPM.\r
	46	///\r
	47	UINT32 InterfaceCapability;// 14h\r
	48	///\r
	49	/// Status Register. Provides status of the TPM.\r
	50	///\r
	51	UINT8 Status; // 18h\r
	52	///\r
	53	/// Number of consecutive writes that can be done to the TPM.\r
	54	///\r
	55	UINT16 BurstCount; // 19h\r
	56	///\r
	57	/// Additional Status Register.\r
	58	///\r
	59	UINT8 StatusEx; // 1Bh\r
	60	UINT8 Reserved3[8];\r
	61	///\r
	62	/// Read or write FIFO, depending on transaction.\r
	63	///\r
	64	UINT32 DataFifo; // 24h\r
	65	UINT8 Reserved4[8]; // 28h\r
	66	///\r
	67	/// Used to identify the Interface types supported by the TPM.\r
	68	///\r
	69	UINT32 InterfaceId; // 30h\r
	70	UINT8 Reserved5[0x4c]; // 34h\r
71	///\r
72	/// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r
73	///\r
74	UINT32 XDataFifo; // 80h\r
75	UINT8 Reserved6[0xe7c]; // 84h\r
76	///\r
77	/// Vendor ID\r
78	///\r
79	UINT16 Vid; // 0f00h\r
80	///\r
81	/// Device ID\r
82	///\r
83	UINT16 Did; // 0f02h\r
84	///\r
85	/// Revision ID\r
86	///\r
87	UINT8 Rid; // 0f04h\r
88	UINT8 Reserved[0xfb]; // 0f05h\r
89	} PTP_FIFO_REGISTERS;\r
90	\r
91	//\r
92	// Restore original structure alignment\r
93	//\r
94	#pragma pack ()\r
95	\r
96	//\r
97	// Define pointer types used to access TIS registers on PC\r
98	//\r
99	typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r
100	\r
101	//\r
102	// Define bits of FIFO Interface Identifier Register\r
103	//\r
104	typedef union {\r
105	struct {\r
106	UINT32 InterfaceType:4;\r
107	UINT32 InterfaceVersion:4;\r
108	UINT32 CapLocality:1;\r
109	UINT32 Reserved1:2;\r
110	UINT32 CapDataXferSizeSupport:2;\r
111	UINT32 CapFIFO:1;\r
112	UINT32 CapCRB:1;\r
113	UINT32 CapIFRes:2;\r
114	UINT32 InterfaceSelector:2;\r
115	UINT32 IntfSelLock:1;\r
116	UINT32 Reserved2:4;\r
117	UINT32 Reserved3:8;\r
118	} Bits;\r
119	UINT32 Uint32;\r
120	} PTP_FIFO_INTERFACE_IDENTIFIER;\r
121	\r
122	//\r
123	// Define bits of FIFO Interface Capability Register\r
124	//\r
125	typedef union {\r
126	struct {\r
127	UINT32 DataAvailIntSupport:1;\r
128	UINT32 StsValidIntSupport:1;\r
129	UINT32 LocalityChangeIntSupport:1;\r
130	UINT32 InterruptLevelHigh:1;\r
131	UINT32 InterruptLevelLow:1;\r
132	UINT32 InterruptEdgeRising:1;\r
133	UINT32 InterruptEdgeFalling:1;\r
134	UINT32 CommandReadyIntSupport:1;\r
135	UINT32 BurstCountStatic:1;\r
136	UINT32 DataTransferSizeSupport:2;\r
137	UINT32 Reserved:17;\r
138	UINT32 InterfaceVersion:3;\r
139	UINT32 Reserved2:1;\r
140	} Bits;\r
141	UINT32 Uint32;\r
142	} PTP_FIFO_INTERFACE_CAPABILITY;\r
143	\r
144	///\r
145	/// InterfaceVersion\r
146	///\r
147	#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0\r
148	#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2\r
149	#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3\r
150	\r
151	\r
152	//\r
153	// Define bits of ACCESS and STATUS registers\r
154	//\r
155	\r
156	///\r
157	/// This bit is a 1 to indicate that the other bits in this register are valid.\r
158	///\r
159	#define PTP_FIFO_VALID BIT7\r
160	///\r
161	/// Indicate that this locality is active.\r
162	///\r
163	#define PTP_FIFO_ACC_ACTIVE BIT5\r
164	///\r
165	/// Set to 1 to indicate that this locality had the TPM taken away while\r
166	/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
167	///\r
168	#define PTP_FIFO_ACC_SEIZED BIT4\r
169	///\r
170	/// Set to 1 to indicate that TPM MUST reset the\r
171	/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
172	/// locality that is writing this bit.\r
173	///\r
174	#define PTP_FIFO_ACC_SEIZE BIT3\r
175	///\r
176	/// When this bit is 1, another locality is requesting usage of the TPM.\r
177	///\r
178	#define PTP_FIFO_ACC_PENDIND BIT2\r
179	///\r
180	/// Set to 1 to indicate that this locality is requesting to use TPM.\r
181	///\r
182	#define PTP_FIFO_ACC_RQUUSE BIT1\r
183	///\r
184	/// A value of 1 indicates that a T/OS has not been established on the platform\r
185	///\r
186	#define PTP_FIFO_ACC_ESTABLISH BIT0\r
187	\r
188	///\r
189	/// This field indicates that STS_DATA and STS_EXPECT are valid\r
190	///\r
191	#define PTP_FIFO_STS_VALID BIT7\r
192	///\r
193	/// When this bit is 1, TPM is in the Ready state,\r
194	/// indicating it is ready to receive a new command.\r
195	///\r
196	#define PTP_FIFO_STS_READY BIT6\r
197	///\r
198	/// Write a 1 to this bit to cause the TPM to execute that command.\r
199	///\r
200	#define PTP_FIFO_STS_GO BIT5\r
201	///\r
202	/// This bit indicates that the TPM has data available as a response.\r
203	///\r
204	#define PTP_FIFO_STS_DATA BIT4\r
205	///\r
206	/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
207	///\r
208	#define PTP_FIFO_STS_EXPECT BIT3\r
209	///\r
210	/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
211	///\r
212	#define PTP_FIFO_STS_SELFTEST_DONE BIT2\r
213	///\r
214	/// Writes a 1 to this bit to force the TPM to re-send the response.\r
215	///\r
216	#define PTP_FIFO_STS_RETRY BIT1\r
217	\r
218	///\r
219	/// TPM Family Identifier.\r
220	/// 00: TPM 1.2 Family\r
221	/// 01: TPM 2.0 Family\r
222	///\r
223	#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 \| BIT3)\r
224	#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)\r
225	#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)\r
226	#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)\r
227	///\r
228	/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r
229	/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r
230	///\r
231	#define PTP_FIFO_STS_EX_CANCEL BIT0\r
232	\r
233	\r
234	//\r
235	// PTP CRB definition\r
236	//\r
237	\r
238	//\r
239	// Set structure alignment to 1-byte\r
240	//\r
241	#pragma pack (1)\r
242	\r
243	//\r
244	// Register set map as specified in PTP specification Chapter 5\r
245	//\r
246	typedef struct {\r
247	///\r
248	/// Used to determine current state of Locality of the TPM.\r
249	///\r
250	UINT32 LocalityState; // 0\r
251	UINT8 Reserved1[4]; // 4\r
252	///\r
253	/// Used to gain control of the TPM by this Locality.\r
254	///\r
255	UINT32 LocalityControl; // 8\r
256	///\r
257	/// Used to determine whether Locality has been granted or Seized.\r
258	///\r
259	UINT32 LocalityStatus; // 0ch\r
260	UINT8 Reserved2[0x20]; // 10h\r
261	///\r
262	/// Used to identify the Interface types supported by the TPM.\r
263	///\r
264	UINT32 InterfaceId; // 30h\r
265	///\r
266	/// Vendor ID\r
267	///\r
268	UINT16 Vid; // 34h\r
269	///\r
270	/// Device ID\r
271	///\r
272	UINT16 Did; // 36h\r
273	///\r
274	/// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r
275	///\r
276	UINT64 CrbControlExtension; // 38h\r
277	///\r
278	/// Register used to initiate transactions for the CRB interface.\r
279	///\r
280	UINT32 CrbControlRequest; // 40h\r
281	///\r
282	/// Register used by the TPM to provide status of the CRB interface.\r
283	///\r
284	UINT32 CrbControlStatus; // 44h\r
285	///\r
286	/// Register used by software to cancel command processing.\r
287	///\r
288	UINT32 CrbControlCancel; // 48h\r
289	///\r
290	/// Register used to indicate presence of command or response data in the CRB buffer.\r
291	///\r
292	UINT32 CrbControlStart; // 4Ch\r
293	///\r
294	/// Register used to configure and respond to interrupts.\r
295	///\r
296	UINT32 CrbInterruptEnable; // 50h\r
297	UINT32 CrbInterruptStatus; // 54h\r
298	///\r
299	/// Size of the Command buffer.\r
300	///\r
301	UINT32 CrbControlCommandSize; // 58h\r
302	///\r
303	/// Command buffer start address\r
304	///\r
305	UINT32 CrbControlCommandAddressLow; // 5Ch\r
306	UINT32 CrbControlCommandAddressHigh; // 60h\r
307	///\r
308	/// Size of the Response buffer\r
309	///\r
310	UINT32 CrbControlResponseSize; // 64h\r
311	///\r
312	/// Address of the start of the Response buffer\r
313	///\r
314	UINT64 CrbControlResponseAddrss; // 68h\r
315	UINT8 Reserved4[0x10]; // 70h\r
316	///\r
317	/// Command/Response Data may be defined as large as 3968 (0xF80).\r
318	///\r
319	UINT8 CrbDataBuffer[0xF80]; // 80h\r
320	} PTP_CRB_REGISTERS;\r
321	\r
322	//\r
323	// Define pointer types used to access CRB registers on PTP\r
324	//\r
325	typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r
326	\r
327	//\r
328	// Define bits of CRB Interface Identifier Register\r
329	//\r
330	typedef union {\r
331	struct {\r
332	UINT32 InterfaceType:4;\r
333	UINT32 InterfaceVersion:4;\r
334	UINT32 CapLocality:1;\r
714eedc5 ZC	335	UINT32 CapCRBIdleBypass:1;\r
714eedc5 ZC	336	UINT32 Reserved1:1;\r
fb7abaca JY	337	UINT32 CapDataXferSizeSupport:2;\r
	338	UINT32 CapFIFO:1;\r
	339	UINT32 CapCRB:1;\r
	340	UINT32 CapIFRes:2;\r
	341	UINT32 InterfaceSelector:2;\r
	342	UINT32 IntfSelLock:1;\r
	343	UINT32 Reserved2:4;\r
	344	UINT32 Rid:8;\r
	345	} Bits;\r
	346	UINT32 Uint32;\r
	347	} PTP_CRB_INTERFACE_IDENTIFIER;\r
	348	\r
	349	///\r
	350	/// InterfaceType\r
	351	///\r
	352	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0\r
	353	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1\r
	354	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF\r
	355	\r
	356	///\r
	357	/// InterfaceVersion\r
	358	///\r
	359	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0\r
	360	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1\r
	361	\r
	362	///\r
	363	/// InterfaceSelector\r
	364	///\r
	365	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0\r
	366	#define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1\r
	367	\r
	368	//\r
	369	// Define bits of Locality State Register\r
	370	//\r
	371	\r
	372	///\r
	373	/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r
	374	///\r
	375	#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7\r
	376	\r
	377	///\r
	378	/// 000 - Locality 0\r
	379	/// 001 - Locality 1\r
	380	/// 010 - Locality 2\r
	381	/// 011 - Locality 3\r
	382	/// 100 - Locality 4\r
	383	///\r
	384	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 \| BIT3 \| BIT4)\r
	385	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)\r
	386	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)\r
	387	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)\r
	388	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 \| BIT3)\r
	389	#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)\r
	390	\r
	391	///\r
	392	/// A 0 indicates to the host that no locality is assigned.\r
	393	/// A 1 indicates a locality has been assigned.\r
	394	///\r
	395	#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1\r
	396	\r
	397	///\r
	398	/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r
	399	/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r
	400	///\r
401	#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0\r
402	\r
403	//\r
404	// Define bits of Locality Control Register\r
405	//\r
406	\r
407	///\r
408	/// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.\r
409	///\r
410	#define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3\r
411	\r
412	///\r
413	/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r
414	///\r
415	#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2\r
416	\r
417	///\r
418	/// Writes (1): The active Locality is done with the TPM.\r
419	///\r
420	#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1\r
421	\r
422	///\r
423	/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r
424	///\r
425	#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0\r
426	\r
427	//\r
428	// Define bits of Locality Status Register\r
429	//\r
430	\r
431	///\r
432	/// 0: A higher locality has not initiated a Seize arbitration process.\r
433	/// 1: A higher locality has Seized the TPM from this locality.\r
434	///\r
435	#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1\r
436	\r
437	///\r
438	/// 0: Locality has not been granted to the TPM.\r
439	/// 1: Locality has been granted access to the TPM\r
440	///\r
441	#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0\r
442	\r
443	//\r
444	// Define bits of CRB Control Area Request Register\r
445	//\r
446	\r
447	///\r
448	/// Used by Software to indicate transition the TPM to and from the Idle state\r
449	/// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle\r
450	/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r
451	/// TPM SHALL complete this transition within TIMEOUT_C.\r
452	///\r
453	#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1\r
454	\r
455	///\r
456	/// Used by Software to request the TPM transition to the Ready State.\r
457	/// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.\r
458	/// 0: Cleared to 0 by TPM to acknowledge the request.\r
459	/// TPM SHALL complete this transition within TIMEOUT_C.\r
460	///\r
461	#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0\r
462	\r
463	//\r
464	// Define bits of CRB Control Area Status Register\r
465	//\r
466	\r
467	///\r
468	/// Used by TPM to indicate it is in the Idle State\r
469	/// 1: Set by TPM when in the Idle State\r
470	/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r
471	/// SHALL be cleared by TIMEOUT_C.\r
472	///\r
473	#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1\r
474	\r
475	///\r
476	/// Used by the TPM to indicate current status.\r
477	/// 1: Set by TPM to indicate a FATAL Error\r
478	/// 0: Indicates TPM is operational\r
479	///\r
480	#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0\r
481	\r
482	//\r
483	// Define bits of CRB Control Cancel Register\r
484	//\r
485	\r
486	///\r
487	/// Used by software to cancel command processing Reads return correct value\r
488	/// Writes (0000 0001h): Cancel a command\r
489	/// Writes (0000 0000h): Clears field when command has been cancelled\r
490	///\r
491	#define PTP_CRB_CONTROL_CANCEL BIT0\r
492	\r
493	//\r
494	// Define bits of CRB Control Start Register\r
495	//\r
496	\r
497	///\r
498	/// When set by software, indicates a command is ready for processing.\r
499	/// Writes (0000 0001h): TPM transitions to Command Execution\r
500	/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r
501	///\r
502	#define PTP_CRB_CONTROL_START BIT0\r
503	\r
504	//\r
505	// Restore original structure alignment\r
506	//\r
507	#pragma pack ()\r
508	\r
509	//\r
510	// Default TimeOut value\r
511	//\r
512	#define PTP_TIMEOUT_A (750 * 1000) // 750ms\r
513	#define PTP_TIMEOUT_B (2000 * 1000) // 2s\r
514	#define PTP_TIMEOUT_C (200 * 1000) // 200ms\r
515	#define PTP_TIMEOUT_D (30 * 1000) // 30ms\r
516	\r
9095d37b	517	#endif\r