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fb3df220 | 1 | /** @file\r |
2 | PAL Call Services\r | |
3 | \r | |
c13f09d0 | 4 | Copyright (c) 2006 -2007, Intel Corporation All rights\r |
5 | reserved. This program and the accompanying materials are\r | |
6 | licensed and made available under the terms and conditions of\r | |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
fb3df220 | 9 | http://opensource.org/licenses/bsd-license.php\r |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
fb3df220 | 14 | **/\r |
15 | \r | |
16 | #ifndef __PAL_CALL_LIB_H__\r | |
17 | #define __PAL_CALL_LIB_H__\r | |
18 | \r | |
6ef95099 | 19 | #define PAL_SUCCESS 0x0\r |
20 | \r | |
c13f09d0 | 21 | //\r |
22 | // CacheType of PAL_CACHE_FLUSH.\r | |
23 | //\r | |
24 | #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r | |
25 | #define PAL_CACHE_FLUSH_DATA_ALL 2\r | |
26 | #define PAL_CACHE_FLUSH_ALL 3\r | |
27 | #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r | |
28 | \r | |
29 | \r | |
30 | //\r | |
31 | // Bitmask of Opearation of PAL_CACHE_FLUSH.\r | |
9c2369c1 | 32 | //\r |
6ef95099 | 33 | #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r |
34 | #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r | |
35 | #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r | |
4199d92d | 36 | #define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r |
c13f09d0 | 37 | \r |
38 | /**\r | |
9c2369c1 | 39 | \r |
c13f09d0 | 40 | PAL Procedure - PAL_CACHE_FLUSH.\r |
9c2369c1 | 41 | \r |
c13f09d0 | 42 | Flush the instruction or data caches. It is required by IPF.\r |
43 | The PAL procedure supports the Static Registers calling\r | |
44 | convention. It could be called at virtual mode and physical\r | |
45 | mode.\r | |
46 | \r | |
47 | @param Index Index of PAL_CACHE_FLUSH within the\r | |
48 | list of PAL procedures.\r | |
9c2369c1 | 49 | \r |
c13f09d0 | 50 | @param CacheType Unsigned 64-bit integer indicating\r |
51 | which cache to flush.\r | |
52 | \r | |
53 | @param Operation Formatted bit vector indicating the\r | |
54 | operation of this call.\r | |
55 | \r | |
56 | @param ProgressIndicator Unsigned 64-bit integer specifying\r | |
57 | the starting position of the flush\r | |
58 | operation.\r | |
9c2369c1 | 59 | \r |
c13f09d0 | 60 | @return R9 Unsigned 64-bit integer specifying the vector\r |
61 | number of the pending interrupt.\r | |
9c2369c1 | 62 | \r |
c13f09d0 | 63 | @return R10 Unsigned 64-bit integer specifying the\r |
64 | starting position of the flush operation.\r | |
9c2369c1 | 65 | \r |
c13f09d0 | 66 | @return R11 Unsigned 64-bit integer specifying the vector\r |
67 | number of the pending interrupt.\r | |
9c2369c1 | 68 | \r |
c13f09d0 | 69 | @return Status 2 - Call completed without error, but a PMI\r |
70 | was taken during the execution of this\r | |
71 | procedure.\r | |
72 | \r | |
73 | @return Status 1 - Call has not completed flushing due to\r | |
74 | a pending interrupt.\r | |
75 | \r | |
76 | @return Status 0 - Call completed without error\r | |
77 | \r | |
78 | @return Status -2 - Invalid argument\r | |
79 | \r | |
80 | @return Status -3 - Call completed with error\r | |
9c2369c1 | 81 | \r |
c13f09d0 | 82 | **/\r |
83 | #define PAL_CACHE_FLUSH 1\r | |
84 | \r | |
85 | \r | |
86 | //\r | |
87 | // Attributes of PAL_CACHE_CONFIG_INFO1\r | |
9c2369c1 | 88 | //\r |
c13f09d0 | 89 | #define PAL_CACHE_ATTR_WT 0\r |
90 | #define PAL_CACHE_ATTR_WB 1\r | |
91 | \r | |
92 | //\r | |
93 | // PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
9c2369c1 | 94 | //\r |
c13f09d0 | 95 | #define PAL_CACHE_STORE_TEMPORAL 0\r |
96 | #define PAL_CACHE_STORE_NONE_TEMPORAL 3\r | |
97 | \r | |
98 | //\r | |
99 | // PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
9c2369c1 | 100 | //\r |
c13f09d0 | 101 | #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r |
102 | #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r | |
103 | \r | |
104 | //\r | |
105 | // PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
9c2369c1 | 106 | //\r |
c13f09d0 | 107 | #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r |
108 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r | |
109 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r | |
110 | \r | |
111 | //\r | |
112 | // Detail the characteristics of a given processor controlled\r | |
113 | // cache in the cache hierarchy.\r | |
9c2369c1 | 114 | //\r |
c13f09d0 | 115 | typedef struct {\r |
116 | UINT64 IsUnified : 1;\r | |
117 | UINT64 Attributes : 2;\r | |
118 | UINT64 Associativity:8;\r | |
119 | UINT64 LineSize:8;\r | |
120 | UINT64 Stride:8;\r | |
121 | UINT64 StoreLatency:8;\r | |
122 | UINT64 StoreHint:8;\r | |
123 | UINT64 LoadHint:8;\r | |
124 | } PAL_CACHE_INFO_RETURN1;\r | |
125 | \r | |
126 | //\r | |
127 | // Detail the characteristics of a given processor controlled\r | |
128 | // cache in the cache hierarchy.\r | |
9c2369c1 | 129 | //\r |
c13f09d0 | 130 | typedef struct {\r |
131 | UINT64 CacheSize:32;\r | |
132 | UINT64 AliasBoundary:8;\r | |
133 | UINT64 TagLsBits:8;\r | |
134 | UINT64 TagMsBits:8;\r | |
135 | } PAL_CACHE_INFO_RETURN2;\r | |
136 | \r | |
137 | /**\r | |
9c2369c1 | 138 | \r |
c13f09d0 | 139 | PAL Procedure - PAL_CACHE_INFO.\r |
9c2369c1 | 140 | \r |
c13f09d0 | 141 | Return detailed instruction or data cache information. It is\r |
142 | required by IPF. The PAL procedure supports the Static\r | |
143 | Registers calling convention. It could be called at virtual\r | |
144 | mode and physical mode.\r | |
9c2369c1 | 145 | \r |
c13f09d0 | 146 | @param Index Index of PAL_CACHE_INFO within the list of\r |
147 | PAL procedures.\r | |
9c2369c1 | 148 | \r |
c13f09d0 | 149 | @param CacheLevel Unsigned 64-bit integer specifying the\r |
150 | level in the cache hierarchy for which\r | |
151 | information is requested. This value must\r | |
152 | be between 0 and one less than the value\r | |
153 | returned in the cache_levels return value\r | |
154 | from PAL_CACHE_SUMMARY.\r | |
9c2369c1 | 155 | \r |
c13f09d0 | 156 | @param CacheType Unsigned 64-bit integer with a value of 1\r |
157 | for instruction cache and 2 for data or\r | |
158 | unified cache. All other values are\r | |
159 | reserved.\r | |
9c2369c1 | 160 | \r |
c13f09d0 | 161 | @param Reserved Should be 0.\r |
9c2369c1 | 162 | \r |
163 | \r | |
c13f09d0 | 164 | @return R9 Detail the characteristics of a given\r |
165 | processor controlled cache in the cache\r | |
166 | hierarchy. See PAL_CACHE_INFO_RETURN1.\r | |
9c2369c1 | 167 | \r |
c13f09d0 | 168 | @return R10 Detail the characteristics of a given\r |
169 | processor controlled cache in the cache\r | |
170 | hierarchy. See PAL_CACHE_INFO_RETURN2.\r | |
9c2369c1 | 171 | \r |
c13f09d0 | 172 | @return R11 Reserved with 0.\r |
9c2369c1 | 173 | \r |
174 | \r | |
c13f09d0 | 175 | @return Status 0 - Call completed without error\r |
176 | \r | |
177 | @return Status -2 - Invalid argument\r | |
178 | \r | |
179 | @return Status -3 - Call completed with error\r | |
9c2369c1 | 180 | \r |
c13f09d0 | 181 | **/\r |
182 | #define PAL_CACHE_INFO 2\r | |
183 | \r | |
184 | \r | |
185 | \r | |
186 | //\r | |
187 | // Level of PAL_CACHE_INIT.\r | |
9c2369c1 | 188 | //\r |
c13f09d0 | 189 | #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r |
190 | \r | |
6ef95099 | 191 | //\r |
9c2369c1 | 192 | // CacheType\r |
6ef95099 | 193 | //\r |
194 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r | |
195 | #define PAL_CACHE_INIT_TYPE_DATA 0x2\r | |
196 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r | |
197 | \r | |
c13f09d0 | 198 | //\r |
199 | // Restrict of PAL_CACHE_INIT.\r | |
9c2369c1 | 200 | //\r |
c13f09d0 | 201 | #define PAL_CACHE_INIT_NO_RESTRICT 0\r |
202 | #define PAL_CACHE_INIT_RESTRICTED 1\r | |
203 | \r | |
204 | /**\r | |
9c2369c1 | 205 | \r |
c13f09d0 | 206 | PAL Procedure - PAL_CACHE_INIT.\r |
9c2369c1 | 207 | \r |
c13f09d0 | 208 | Initialize the instruction or data caches. It is required by\r |
209 | IPF. The PAL procedure supports the Static Registers calling\r | |
210 | convention. It could be called at physical mode.\r | |
211 | \r | |
212 | @param Index Index of PAL_CACHE_INIT within the list of PAL\r | |
213 | procedures.\r | |
9c2369c1 | 214 | \r |
c13f09d0 | 215 | @param Level Unsigned 64-bit integer containing the level of\r |
216 | cache to initialize. If the cache level can be\r | |
217 | initialized independently, only that level will\r | |
218 | be initialized. Otherwise\r | |
219 | implementation-dependent side-effects will\r | |
220 | occur.\r | |
9c2369c1 | 221 | \r |
c13f09d0 | 222 | @param CacheType Unsigned 64-bit integer with a value of 1 to\r |
223 | initialize the instruction cache, 2 to\r | |
224 | initialize the data cache, or 3 to\r | |
225 | initialize both. All other values are\r | |
226 | reserved.\r | |
227 | \r | |
228 | @param Restrict Unsigned 64-bit integer with a value of 0 or\r | |
229 | 1. All other values are reserved. If\r | |
230 | restrict is 1 and initializing the specified\r | |
231 | level and cache_type of the cache would\r | |
232 | cause side-effects, PAL_CACHE_INIT will\r | |
233 | return -4 instead of initializing the cache.\r | |
9c2369c1 | 234 | \r |
235 | \r | |
c13f09d0 | 236 | @return Status 0 - Call completed without error\r |
237 | \r | |
238 | @return Status -2 - Invalid argument\r | |
239 | \r | |
240 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 241 | \r |
c13f09d0 | 242 | @return Status -4 - Call could not initialize the specified\r |
243 | level and cache_type of the cache without\r | |
9c2369c1 | 244 | side-effects and restrict was 1.\r |
245 | \r | |
c13f09d0 | 246 | **/\r |
9c2369c1 | 247 | #define PAL_CACHE_INIT 3\r |
c13f09d0 | 248 | \r |
249 | \r | |
250 | //\r | |
251 | // PAL_CACHE_PROTECTION.Method.\r | |
9c2369c1 | 252 | //\r |
c13f09d0 | 253 | #define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r |
254 | #define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r | |
255 | #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r | |
256 | #define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r | |
257 | \r | |
258 | \r | |
259 | \r | |
260 | //\r | |
261 | // PAL_CACHE_PROTECTION.TagOrData.\r | |
9c2369c1 | 262 | //\r |
c13f09d0 | 263 | #define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r |
264 | #define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r | |
265 | #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r | |
266 | #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r | |
267 | \r | |
268 | //\r | |
269 | // 32-bit protection information structures.\r | |
9c2369c1 | 270 | //\r |
c13f09d0 | 271 | typedef struct {\r |
272 | UINT32 DataBits:8;\r | |
273 | UINT32 TagProtLsb:6;\r | |
274 | UINT32 TagProtMsb:6;\r | |
275 | UINT32 ProtBits:6;\r | |
276 | UINT32 Method:4;\r | |
277 | UINT32 TagOrData:2;\r | |
278 | } PAL_CACHE_PROTECTION;\r | |
279 | \r | |
280 | /**\r | |
9c2369c1 | 281 | \r |
c13f09d0 | 282 | PAL Procedure - PAL_CACHE_PROT_INFO.\r |
9c2369c1 | 283 | \r |
c13f09d0 | 284 | Return instruction or data cache protection information. It is\r |
285 | required by IPF. The PAL procedure supports the Static\r | |
286 | Registers calling convention. It could be called at physical\r | |
287 | mode and Virtual mode.\r | |
288 | \r | |
289 | @param Index Index of PAL_CACHE_PROT_INFO within the list of\r | |
290 | PAL procedures.\r | |
291 | \r | |
292 | @param CacheLevel Unsigned 64-bit integer specifying the level\r | |
293 | in the cache hierarchy for which information\r | |
294 | is requested. This value must be between 0\r | |
295 | and one less than the value returned in the\r | |
296 | cache_levels return value from\r | |
297 | PAL_CACHE_SUMMARY.\r | |
298 | \r | |
299 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
300 | for instruction cache and 2 for data or\r | |
301 | unified cache. All other values are\r | |
302 | reserved.\r | |
9c2369c1 | 303 | \r |
c13f09d0 | 304 | @return R9 Detail the characteristics of a given\r |
305 | processor controlled cache in the cache\r | |
306 | hierarchy. See PAL_CACHE_PROTECTION[0..1].\r | |
9c2369c1 | 307 | \r |
c13f09d0 | 308 | @return R10 Detail the characteristics of a given\r |
309 | processor controlled cache in the cache\r | |
310 | hierarchy. See PAL_CACHE_PROTECTION[2..3].\r | |
9c2369c1 | 311 | \r |
c13f09d0 | 312 | @return R11 Detail the characteristics of a given\r |
313 | processor controlled cache in the cache\r | |
314 | hierarchy. See PAL_CACHE_PROTECTION[4..5].\r | |
9c2369c1 | 315 | \r |
316 | \r | |
c13f09d0 | 317 | @return Status 0 - Call completed without error\r |
318 | \r | |
319 | @return Status -2 - Invalid argument\r | |
320 | \r | |
321 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 322 | \r |
c13f09d0 | 323 | **/\r |
324 | #define PAL_CACHE_PROT_INFO 38\r | |
325 | \r | |
326 | /**\r | |
9c2369c1 | 327 | \r |
c13f09d0 | 328 | @param ThreadId The thread identifier of the logical\r |
329 | processor for which information is being\r | |
330 | returned. This value will be unique on a per\r | |
331 | core basis.\r | |
332 | \r | |
333 | @param CoreId The core identifier of the logical processor\r | |
334 | for which information is being returned.\r | |
335 | This value will be unique on a per physical\r | |
336 | processor package basis.\r | |
337 | \r | |
338 | **/\r | |
339 | typedef struct {\r | |
340 | UINT64 ThreadId : 16;\r | |
341 | UINT64 Reserved1: 16;\r | |
342 | UINT64 CoreId: 16;\r | |
343 | UINT64 Reserved2: 16;\r | |
344 | } PAL_PCOC_N_CACHE_INFO1;\r | |
345 | \r | |
346 | /**\r | |
9c2369c1 | 347 | \r |
c13f09d0 | 348 | @param LogicalAddress Logical address: geographical address\r |
349 | of the logical processor for which\r | |
350 | information is being returned. This is\r | |
351 | the same value that is returned by the\r | |
352 | PAL_FIXED_ADDR procedure when it is\r | |
353 | called on the logical processor.\r | |
354 | \r | |
355 | **/\r | |
356 | typedef struct {\r | |
357 | UINT64 LogicalAddress : 16;\r | |
358 | UINT64 Reserved1: 16;\r | |
359 | UINT64 Reserved2: 32;\r | |
360 | } PAL_PCOC_N_CACHE_INFO2;\r | |
361 | \r | |
362 | /**\r | |
9c2369c1 | 363 | \r |
c13f09d0 | 364 | PAL Procedure - PAL_CACHE_SHARED_INFO.\r |
9c2369c1 | 365 | \r |
c13f09d0 | 366 | Returns information on which logical processors share caches.\r |
367 | It is optional. The PAL procedure supports the Static\r | |
368 | Registers calling convention. It could be called at physical\r | |
369 | mode and Virtual mode.\r | |
9c2369c1 | 370 | \r |
c13f09d0 | 371 | @param Index Index of PAL_CACHE_SHARED_INFO within the list\r |
372 | of PAL procedures.\r | |
9c2369c1 | 373 | \r |
c13f09d0 | 374 | @param CacheLevel Unsigned 64-bit integer specifying the\r |
375 | level in the cache hierarchy for which\r | |
376 | information is requested. This value must\r | |
377 | be between 0 and one less than the value\r | |
378 | returned in the cache_levels return value\r | |
379 | from PAL_CACHE_SUMMARY.\r | |
9c2369c1 | 380 | \r |
c13f09d0 | 381 | @param CacheType Unsigned 64-bit integer with a value of 1\r |
382 | for instruction cache and 2 for data or\r | |
383 | unified cache. All other values are\r | |
384 | reserved.\r | |
9c2369c1 | 385 | \r |
c13f09d0 | 386 | @param ProcNumber Unsigned 64-bit integer that specifies for\r |
387 | which logical processor information is\r | |
388 | being requested. This input argument must\r | |
389 | be zero for the first call to this\r | |
390 | procedure and can be a maximum value of\r | |
391 | one less than the number of logical\r | |
392 | processors sharing this cache, which is\r | |
393 | returned by the num_shared return value.\r | |
9c2369c1 | 394 | \r |
c13f09d0 | 395 | @return R9 Unsigned integer that returns the number of\r |
396 | logical processors that share the processor\r | |
397 | cache level and type, for which information was\r | |
398 | requested.\r | |
399 | \r | |
400 | @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r | |
401 | \r | |
402 | @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r | |
403 | \r | |
404 | @return Status 0 - Call completed without error\r | |
405 | \r | |
406 | @return Status -1 - Unimplemented procedure\r | |
407 | \r | |
408 | @return Status -2 - Invalid argument\r | |
409 | \r | |
410 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 411 | \r |
c13f09d0 | 412 | **/\r |
413 | #define PAL_CACHE_SHARED_INFO 43\r | |
414 | \r | |
415 | \r | |
416 | /**\r | |
9c2369c1 | 417 | \r |
c13f09d0 | 418 | PAL Procedure - PAL_CACHE_SUMMARY.\r |
9c2369c1 | 419 | \r |
c13f09d0 | 420 | Return a summary of the cache hierarchy. It is required by\r |
421 | IPF. The PAL procedure supports the Static Registers calling\r | |
422 | convention. It could be called at physical mode and Virtual\r | |
423 | mode.\r | |
9c2369c1 | 424 | \r |
c13f09d0 | 425 | @param Index Index of PAL_CACHE_SUMMARY within the list of\r |
426 | PAL procedures.\r | |
427 | \r | |
9c2369c1 | 428 | \r |
c13f09d0 | 429 | @return R9 CacheLevels Unsigned 64-bit integer denoting the\r |
430 | number of levels of cache\r | |
431 | implemented by the processor.\r | |
432 | Strictly, this is the number of\r | |
433 | levels for which the cache\r | |
434 | controller is integrated into the\r | |
435 | processor (the cache SRAMs may be\r | |
436 | external to the processor).\r | |
437 | \r | |
438 | @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r | |
439 | number of unique caches implemented\r | |
440 | by the processor. This has a maximum\r | |
441 | of 2*cache_levels, but may be less\r | |
442 | if any of the levels in the cache\r | |
443 | hierarchy are unified caches or do\r | |
444 | not have both instruction and data\r | |
445 | caches.\r | |
446 | \r | |
447 | @return Status 0 - Call completed without error\r | |
448 | \r | |
449 | @return Status -2 - Invalid argument\r | |
450 | \r | |
451 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 452 | \r |
c13f09d0 | 453 | **/\r |
454 | #define PAL_CACHE_SUMMARY 4\r | |
455 | \r | |
456 | \r | |
457 | //\r | |
9c2369c1 | 458 | // Virtual Memory Attributes implemented by processor.\r |
459 | //\r | |
c13f09d0 | 460 | #define PAL_MEMORY_ATTR_WB 0\r |
461 | #define PAL_MEMORY_ATTR_WC 6\r | |
462 | #define PAL_MEMORY_ATTR_UC 4\r | |
463 | #define PAL_MEMORY_ATTR_UCE 5\r | |
464 | #define PAL_MEMORY_ATTR_NATPAGE 7\r | |
465 | \r | |
466 | /**\r | |
9c2369c1 | 467 | \r |
c13f09d0 | 468 | PAL Procedure - PAL_MEM_ATTRIB.\r |
9c2369c1 | 469 | \r |
c13f09d0 | 470 | Return a list of supported memory attributes.. It is required\r |
471 | by IPF. The PAL procedure supports the Static Registers calling\r | |
472 | convention. It could be called at physical mode and Virtual\r | |
473 | mode.\r | |
9c2369c1 | 474 | \r |
c13f09d0 | 475 | @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r |
476 | procedures.\r | |
477 | \r | |
9c2369c1 | 478 | \r |
c13f09d0 | 479 | @return R9 Attributes 8-bit vector of memory attributes\r |
480 | implemented by processor. See Virtual\r | |
481 | Memory Attributes above.\r | |
482 | \r | |
483 | @return Status 0 - Call completed without error\r | |
484 | \r | |
485 | @return Status -2 - Invalid argument\r | |
486 | \r | |
487 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 488 | \r |
c13f09d0 | 489 | **/\r |
490 | \r | |
491 | #define PAL_MEM_ATTRIB 5\r | |
492 | \r | |
493 | /**\r | |
9c2369c1 | 494 | \r |
c13f09d0 | 495 | PAL Procedure - PAL_PREFETCH_VISIBILITY.\r |
9c2369c1 | 496 | \r |
c13f09d0 | 497 | Used in architected sequence to transition pages from a\r |
498 | cacheable, speculative attribute to an uncacheable attribute.\r | |
499 | It is required by IPF. The PAL procedure supports the Static\r | |
500 | Registers calling convention. It could be called at physical\r | |
501 | mode and Virtual mode.\r | |
9c2369c1 | 502 | \r |
c13f09d0 | 503 | @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r |
504 | of PAL procedures.\r | |
505 | \r | |
506 | @param TransitionType Unsigned integer specifying the type\r | |
507 | of memory attribute transition that is\r | |
508 | being performed.\r | |
9c2369c1 | 509 | \r |
c13f09d0 | 510 | @return Status 1 Call completed without error; this\r |
511 | call is not necessary on remote\r | |
512 | processors.\r | |
513 | \r | |
514 | @return Status 0 - Call completed without error\r | |
515 | \r | |
516 | @return Status -2 - Invalid argument\r | |
517 | \r | |
518 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 519 | \r |
c13f09d0 | 520 | **/\r |
521 | #define PAL_PREFETCH_VISIBILITY 41\r | |
522 | \r | |
523 | /**\r | |
9c2369c1 | 524 | \r |
c13f09d0 | 525 | PAL Procedure - PAL_PTCE_INFO.\r |
9c2369c1 | 526 | \r |
c13f09d0 | 527 | Return information needed for ptc.e instruction to purge\r |
528 | entire TC. It is required by IPF. The PAL procedure supports\r | |
529 | the Static Registers calling convention. It could be called at\r | |
530 | physical mode and Virtual mode.\r | |
9c2369c1 | 531 | \r |
c13f09d0 | 532 | @param Index Index of PAL_PTCE_INFO within the list\r |
533 | of PAL procedures.\r | |
534 | \r | |
535 | @return R9 Unsigned 64-bit integer denoting the beginning\r | |
536 | address to be used by the first PTCE instruction\r | |
537 | in the purge loop.\r | |
9c2369c1 | 538 | \r |
c13f09d0 | 539 | @return R10 Two unsigned 32-bit integers denoting the loop\r |
540 | counts of the outer (loop 1) and inner (loop 2)\r | |
541 | purge loops. count1 (loop 1) is contained in bits\r | |
542 | 63:32 of the parameter, and count2 (loop 2) is\r | |
543 | contained in bits 31:0 of the parameter.\r | |
9c2369c1 | 544 | \r |
c13f09d0 | 545 | @return R11 Two unsigned 32-bit integers denoting the loop\r |
546 | strides of the outer (loop 1) and inner (loop 2)\r | |
547 | purge loops. stride1 (loop 1) is contained in bits\r | |
548 | 63:32 of the parameter, and stride2 (loop 2) is\r | |
549 | contained in bits 31:0 of the parameter.\r | |
550 | \r | |
551 | @return Status 0 - Call completed without error\r | |
552 | \r | |
553 | @return Status -2 - Invalid argument\r | |
554 | \r | |
555 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 556 | \r |
c13f09d0 | 557 | **/\r |
558 | #define PAL_PTCE_INFO 6\r | |
559 | \r | |
560 | \r | |
561 | \r | |
562 | /**\r | |
9c2369c1 | 563 | \r |
c13f09d0 | 564 | @param NumberSets Unsigned 8-bit integer denoting the number\r |
565 | of hash sets for the specified level\r | |
566 | (1=fully associative)\r | |
567 | \r | |
568 | @param NumberWays Unsigned 8-bit integer denoting the\r | |
569 | associativity of the specified level\r | |
570 | (1=direct).\r | |
571 | \r | |
572 | @param NumberEntries Unsigned 16-bit integer denoting the\r | |
573 | number of entries in the specified TC.\r | |
574 | \r | |
575 | \r | |
576 | @param PageSizeIsOptimized Flag denoting whether the\r | |
577 | specified level is optimized for\r | |
578 | the region's preferred page size\r | |
579 | (1=optimized) tc_pages indicates\r | |
580 | which page sizes are usable by\r | |
581 | this translation cache.\r | |
582 | \r | |
583 | @param TcIsUnified Flag denoting whether the specified TC is\r | |
584 | unified (1=unified).\r | |
585 | \r | |
586 | @param EntriesReduction Flag denoting whether installed\r | |
587 | translation registers will reduce\r | |
588 | the number of entries within the\r | |
589 | specified TC.\r | |
590 | \r | |
591 | **/\r | |
592 | typedef struct {\r | |
593 | UINT64 NumberSets:8;\r | |
594 | UINT64 NumberWays:8;\r | |
595 | UINT64 NumberEntries:16;\r | |
596 | UINT64 PageSizeIsOptimized:1;\r | |
597 | UINT64 TcIsUnified:1;\r | |
598 | UINT64 EntriesReduction:1;\r | |
599 | } PAL_TC_INFO;\r | |
600 | \r | |
601 | /**\r | |
9c2369c1 | 602 | \r |
c13f09d0 | 603 | PAL Procedure - PAL_VM_INFO.\r |
9c2369c1 | 604 | \r |
c13f09d0 | 605 | Return detailed information about virtual memory features\r |
606 | supported in the processor. It is required by IPF. The PAL\r | |
607 | procedure supports the Static Registers calling convention. It\r | |
608 | could be called at physical mode and Virtual mode.\r | |
9c2369c1 | 609 | \r |
c13f09d0 | 610 | @param Index Index of PAL_VM_INFO within the list\r |
611 | of PAL procedures.\r | |
9c2369c1 | 612 | \r |
c13f09d0 | 613 | @param TcLevel Unsigned 64-bit integer specifying the level\r |
614 | in the TLB hierarchy for which information is\r | |
615 | required. This value must be between 0 and one\r | |
616 | less than the value returned in the\r | |
617 | vm_info_1.num_tc_levels return value from\r | |
618 | PAL_VM_SUMMARY.\r | |
9c2369c1 | 619 | \r |
c13f09d0 | 620 | @param TcType Unsigned 64-bit integer with a value of 1 for\r |
621 | instruction translation cache and 2 for data\r | |
622 | or unified translation cache. All other values\r | |
623 | are reserved.\r | |
624 | \r | |
625 | @return R9 8-byte formatted value returning information\r | |
626 | about the specified TC. See PAL_TC_INFO above.\r | |
627 | \r | |
628 | @return R10 64-bit vector containing a bit for each page\r | |
629 | size supported in the specified TC, where bit\r | |
630 | position n indicates a page size of 2**n.\r | |
631 | \r | |
632 | @return Status 0 - Call completed without error\r | |
633 | \r | |
634 | @return Status -2 - Invalid argument\r | |
635 | \r | |
636 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 637 | \r |
c13f09d0 | 638 | **/\r |
639 | #define PAL_VM_INFO 7\r | |
640 | \r | |
641 | \r | |
642 | /**\r | |
9c2369c1 | 643 | \r |
c13f09d0 | 644 | PAL Procedure - PAL_VM_PAGE_SIZE.\r |
9c2369c1 | 645 | \r |
c13f09d0 | 646 | Return virtual memory TC and hardware walker page sizes\r |
647 | supported in the processor. It is required by IPF. The PAL\r | |
648 | procedure supports the Static Registers calling convention. It\r | |
649 | could be called at physical mode and Virtual mode.\r | |
9c2369c1 | 650 | \r |
c13f09d0 | 651 | @param Index Index of PAL_VM_PAGE_SIZE within the list\r |
652 | of PAL procedures.\r | |
9c2369c1 | 653 | \r |
c13f09d0 | 654 | \r |
655 | @return R9 64-bit vector containing a bit for each\r | |
656 | architected page size that is supported for\r | |
657 | TLB insertions and region registers.\r | |
658 | \r | |
659 | @return R10 64-bit vector containing a bit for each\r | |
660 | architected page size supported for TLB purge\r | |
661 | operations.\r | |
662 | \r | |
663 | @return Status 0 - Call completed without error\r | |
664 | \r | |
665 | @return Status -2 - Invalid argument\r | |
666 | \r | |
667 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 668 | \r |
c13f09d0 | 669 | **/\r |
670 | #define PAL_VM_PAGE_SIZE 34\r | |
671 | \r | |
672 | /**\r | |
9c2369c1 | 673 | \r |
c13f09d0 | 674 | @param WalkerPresent 1-bit flag indicating whether a hardware\r |
675 | TLB walker is implemented (1 = walker\r | |
676 | present).\r | |
677 | \r | |
678 | @param WidthOfPhysicalAddress Unsigned 7-bit integer\r | |
679 | denoting the number of bits of\r | |
680 | physical address implemented.\r | |
681 | \r | |
682 | @param WidthOfKey Unsigned 8-bit integer denoting the number\r | |
683 | of bits mplemented in the PKR.key field.\r | |
684 | \r | |
685 | @param MaxPkrIndex Unsigned 8-bit integer denoting the\r | |
686 | maximum PKR index (number of PKRs-1).\r | |
687 | \r | |
688 | @param HashTagId Unsigned 8-bit integer which uniquely\r | |
689 | identifies the processor hash and tag\r | |
690 | algorithm.\r | |
691 | \r | |
692 | @param MaxDtrIndex Unsigned 8 bit integer denoting the\r | |
693 | maximum data translation register index\r | |
694 | (number of dtr entries - 1).\r | |
695 | \r | |
696 | @param MaxItrIndex Unsigned 8 bit integer denoting the\r | |
697 | maximum instruction translation register\r | |
698 | index (number of itr entries - 1).\r | |
699 | \r | |
700 | @param NumberOfUniqueTc Unsigned 8-bit integer denoting the\r | |
701 | number of unique TCs implemented.\r | |
702 | This is a maximum of\r | |
703 | 2*num_tc_levels.\r | |
704 | \r | |
705 | @param NumberOfTcLevels Unsigned 8-bit integer denoting the\r | |
706 | number of TC levels.\r | |
707 | \r | |
708 | **/\r | |
709 | typedef struct {\r | |
710 | UINT64 WalkerPresent:1;\r | |
711 | UINT64 WidthOfPhysicalAddress: 7;\r | |
712 | UINT64 WidthOfKey:8;\r | |
713 | UINT64 MaxPkrIndex:8;\r | |
714 | UINT64 HashTagId:8;\r | |
715 | UINT64 MaxDtrIndex:8;\r | |
716 | UINT64 MaxItrIndex:8;\r | |
717 | UINT64 NumberOfUniqueTc:8;\r | |
718 | UINT64 NumberOfTcLevels:8;\r | |
719 | } PAL_VM_INFO1;\r | |
720 | \r | |
721 | /**\r | |
9c2369c1 | 722 | \r |
c13f09d0 | 723 | @param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r |
724 | is the total number of virtual\r | |
725 | address bits - 1.\r | |
726 | \r | |
727 | @param WidthOfRid Unsigned 8-bit integer denoting the number\r | |
728 | of bits implemented in the RR.rid field.\r | |
729 | \r | |
730 | @param MaxPurgedTlbs Unsigned 16 bit integer denoting the\r | |
731 | maximum number of concurrent outstanding\r | |
732 | TLB purges allowed by the processor. A\r | |
733 | value of 0 indicates one outstanding\r | |
734 | purge allowed. A value of 216-1\r | |
735 | indicates no limit on outstanding\r | |
736 | purges. All other values indicate the\r | |
737 | actual number of concurrent outstanding\r | |
738 | purges allowed.\r | |
739 | \r | |
740 | **/\r | |
741 | typedef struct {\r | |
742 | UINT64 WidthOfVirtualAddress:8;\r | |
743 | UINT64 WidthOfRid:8;\r | |
744 | UINT64 MaxPurgedTlbs:16;\r | |
745 | UINT64 Reserved:32;\r | |
746 | } PAL_VM_INFO2;\r | |
747 | \r | |
748 | /**\r | |
9c2369c1 | 749 | \r |
c13f09d0 | 750 | PAL Procedure - PAL_VM_SUMMARY.\r |
9c2369c1 | 751 | \r |
c13f09d0 | 752 | Return summary information about virtual memory features\r |
753 | supported in the processor. It is required by IPF. The PAL\r | |
754 | procedure supports the Static Registers calling convention. It\r | |
755 | could be called at physical mode and Virtual mode.\r | |
9c2369c1 | 756 | \r |
c13f09d0 | 757 | @param Index Index of PAL_VM_SUMMARY within the list\r |
758 | of PAL procedures.\r | |
9c2369c1 | 759 | \r |
c13f09d0 | 760 | \r |
761 | @return R9 8-byte formatted value returning global virtual\r | |
762 | memory information. See PAL_VM_INFO1 above.\r | |
763 | \r | |
764 | @return R10 8-byte formatted value returning global virtual\r | |
765 | memory information. See PAL_VM_INFO2 above.\r | |
766 | \r | |
767 | @return Status 0 - Call completed without error\r | |
768 | \r | |
769 | @return Status -2 - Invalid argument\r | |
770 | \r | |
771 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 772 | \r |
c13f09d0 | 773 | **/\r |
774 | #define PAL_VM_SUMMARY 8\r | |
775 | \r | |
fb3df220 | 776 | \r |
fb3df220 | 777 | //\r |
c13f09d0 | 778 | // Bit mask of TR_valid flag.\r |
9c2369c1 | 779 | //\r |
c13f09d0 | 780 | #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r |
781 | #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r | |
782 | #define PAL_TR_DIRTY_IS_VALID BIT2\r | |
783 | #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r | |
784 | \r | |
785 | \r | |
786 | /**\r | |
9c2369c1 | 787 | \r |
c13f09d0 | 788 | PAL Procedure - PAL_VM_TR_READ.\r |
9c2369c1 | 789 | \r |
c13f09d0 | 790 | Read contents of a translation register. It is required by\r |
791 | IPF. The PAL procedure supports the Stacked Register calling\r | |
792 | convention. It could be called at physical mode.\r | |
9c2369c1 | 793 | \r |
c13f09d0 | 794 | @param Index Index of PAL_VM_TR_READ within the list\r |
795 | of PAL procedures.\r | |
796 | \r | |
797 | @param RegNumber Unsigned 64-bit number denoting which TR to\r | |
798 | read.\r | |
799 | \r | |
800 | @param TrType Unsigned 64-bit number denoting whether to\r | |
801 | read an ITR (0) or DTR (1). All other values\r | |
802 | are reserved.\r | |
803 | \r | |
804 | @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r | |
805 | which translation data is returned.\r | |
806 | \r | |
807 | @return R9 Formatted bit vector denoting which fields are\r | |
808 | valid. See TR_valid above.\r | |
809 | \r | |
810 | @return Status 0 - Call completed without error\r | |
811 | \r | |
812 | @return Status -2 - Invalid argument\r | |
813 | \r | |
814 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 815 | \r |
c13f09d0 | 816 | **/\r |
9c2369c1 | 817 | #define PAL_VM_TR_READ 261\r |
c13f09d0 | 818 | \r |
819 | \r | |
820 | \r | |
821 | \r | |
fb3df220 | 822 | //\r |
c13f09d0 | 823 | // Bit Mask of Processor Bus Fesatures .\r |
9c2369c1 | 824 | //\r |
c13f09d0 | 825 | \r |
826 | /**\r | |
9c2369c1 | 827 | \r |
c13f09d0 | 828 | When 0, bus data errors are detected and single bit errors are\r |
829 | corrected. When 1, no error detection or correction is done.\r | |
830 | \r | |
831 | **/\r | |
832 | #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r | |
833 | \r | |
834 | \r | |
835 | /**\r | |
9c2369c1 | 836 | \r |
c13f09d0 | 837 | When 0, bus address errors are signalled on the bus. When 1,\r |
838 | no bus errors are signalled on the bus. If Disable Bus Address\r | |
839 | Error Checking is 1, this bit is ignored.\r | |
840 | \r | |
841 | **/\r | |
842 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r | |
843 | \r | |
844 | \r | |
845 | \r | |
846 | \r | |
847 | /**\r | |
9c2369c1 | 848 | \r |
c13f09d0 | 849 | When 0, bus errors are detected, single bit errors are\r |
850 | corrected., and a CMCI or MCA is generated internally to the\r | |
851 | processor. When 1, no bus address errors are detected or\r | |
852 | corrected.\r | |
853 | \r | |
854 | **/\r | |
855 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r | |
856 | \r | |
857 | \r | |
858 | /**\r | |
9c2369c1 | 859 | \r |
c13f09d0 | 860 | When 0, bus protocol errors (BINIT#) are signaled by the\r |
861 | processor on the bus. When 1, bus protocol errors (BINIT#) are\r | |
862 | not signaled on the bus. If Disable Bus Initialization Event\r | |
863 | Checking is 1, this bit is ignored.\r | |
864 | \r | |
865 | **/\r | |
866 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r | |
867 | \r | |
868 | \r | |
869 | /**\r | |
9c2369c1 | 870 | \r |
c13f09d0 | 871 | When 0, bus protocol errors (BINIT#) are detected and sampled\r |
872 | and an MCA is generated internally to the processor. When 1,\r | |
873 | the processor will ignore bus protocol error conditions\r | |
874 | (BINIT#).\r | |
875 | \r | |
876 | **/\r | |
877 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r | |
878 | \r | |
879 | \r | |
880 | \r | |
881 | /**\r | |
9c2369c1 | 882 | \r |
c13f09d0 | 883 | When 0, BERR# is signalled if a bus error is detected. When 1,\r |
884 | bus errors are not signalled on the bus.\r | |
885 | \r | |
886 | **/\r | |
887 | #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r | |
888 | \r | |
889 | \r | |
890 | \r | |
891 | \r | |
892 | /**\r | |
9c2369c1 | 893 | \r |
c13f09d0 | 894 | When 0, BERR# is signalled when internal processor requestor\r |
895 | initiated bus errors are detected. When 1, internal requester\r | |
896 | bus errors are not signalled on the bus.\r | |
9c2369c1 | 897 | \r |
c13f09d0 | 898 | **/\r |
899 | #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r | |
900 | \r | |
901 | \r | |
902 | /**\r | |
9c2369c1 | 903 | \r |
c13f09d0 | 904 | When 0, the processor takes an MCA if BERR# is asserted. When\r |
905 | 1, the processor ignores the BERR# signal.\r | |
906 | \r | |
907 | **/\r | |
908 | #define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r | |
909 | \r | |
910 | \r | |
911 | /**\r | |
9c2369c1 | 912 | \r |
c13f09d0 | 913 | When 0, the processor asserts BINIT# if it detects a parity\r |
914 | error on the signals which identify the transactions to which\r | |
915 | this is a response. When 1, the processor ignores parity on\r | |
916 | these signals.\r | |
9c2369c1 | 917 | \r |
c13f09d0 | 918 | **/\r |
919 | #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r | |
920 | \r | |
921 | \r | |
922 | /**\r | |
9c2369c1 | 923 | \r |
c13f09d0 | 924 | When 0, the in-order transaction queue is limited only by the\r |
925 | number of hardware entries. When 1, the processor's in-order\r | |
926 | transactions queue is limited to one entry.\r | |
927 | \r | |
928 | **/\r | |
929 | #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r | |
930 | \r | |
931 | /**\r | |
9c2369c1 | 932 | \r |
c13f09d0 | 933 | Enable a bus cache line replacement transaction when a cache\r |
934 | line in the exclusive state is replaced from the highest level\r | |
935 | processor cache and is not present in the lower level processor\r | |
936 | caches. When 0, no bus cache line replacement transaction will\r | |
937 | be seen on the bus. When 1, bus cache line replacement\r | |
938 | transactions will be seen on the bus when the above condition is\r | |
939 | detected.\r | |
940 | \r | |
941 | **/\r | |
942 | #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r | |
943 | \r | |
944 | \r | |
945 | /**\r | |
9c2369c1 | 946 | \r |
c13f09d0 | 947 | Enable a bus cache line replacement transaction when a cache\r |
948 | line in the shared or exclusive state is replaced from the\r | |
949 | highest level processor cache and is not present in the lower\r | |
950 | level processor caches.\r | |
951 | When 0, no bus cache line replacement transaction will be seen\r | |
952 | on the bus. When 1, bus cache line replacement transactions\r | |
953 | will be seen on the bus when the above condition is detected.\r | |
954 | \r | |
955 | **/\r | |
956 | #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r | |
957 | \r | |
958 | \r | |
9c2369c1 | 959 | \r |
c13f09d0 | 960 | /**\r |
9c2369c1 | 961 | \r |
c13f09d0 | 962 | When 0, the data bus is configured at the 2x data transfer\r |
963 | rate.When 1, the data bus is configured at the 1x data\r | |
964 | transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r | |
965 | processor executes locked transactions atomically. When 1, the\r | |
966 | processor masks the bus lock signal and executes locked\r | |
967 | transactions as a non-atomic series of transactions.\r | |
968 | \r | |
969 | **/\r | |
970 | #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r | |
971 | \r | |
972 | /**\r | |
9c2369c1 | 973 | \r |
c13f09d0 | 974 | When 0, the processor will deassert bus request when finished\r |
975 | with each transaction. When 1, the processor will continue to\r | |
976 | assert bus request after it has finished, if it was the last\r | |
977 | agent to own the bus and if there are no other pending\r | |
978 | requests.\r | |
979 | \r | |
980 | **/\r | |
981 | #define PAL_BUS_REQUEST_BUS_PARKING BIT29\r | |
982 | \r | |
983 | \r | |
984 | /**\r | |
9c2369c1 | 985 | \r |
c13f09d0 | 986 | PAL Procedure - PAL_BUS_GET_FEATURES.\r |
9c2369c1 | 987 | \r |
c13f09d0 | 988 | Return configurable processor bus interface features and their\r |
989 | current settings. It is required by IPF. The PAL procedure\r | |
990 | supports the Stacked Register calling convention. It could be\r | |
991 | called at physical mode.\r | |
9c2369c1 | 992 | \r |
c13f09d0 | 993 | @param Index Index of PAL_BUS_GET_FEATURES within the list\r |
994 | of PAL procedures.\r | |
995 | \r | |
996 | @return R9 64-bit vector of features implemented.\r | |
997 | (1=implemented, 0=not implemented)\r | |
998 | \r | |
999 | @return R10 64-bit vector of current feature settings.\r | |
1000 | \r | |
1001 | @return R11 64-bit vector of features controllable by\r | |
1002 | software. (1=controllable, 0= not controllable)\r | |
1003 | \r | |
1004 | @return Status 0 - Call completed without error\r | |
1005 | \r | |
1006 | @return Status -2 - Invalid argument\r | |
1007 | \r | |
1008 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1009 | \r |
c13f09d0 | 1010 | **/\r |
1011 | #define PAL_BUS_GET_FEATURES 9\r | |
1012 | \r | |
1013 | /**\r | |
9c2369c1 | 1014 | \r |
c13f09d0 | 1015 | PAL Procedure - PAL_BUS_SET_FEATURES.\r |
9c2369c1 | 1016 | \r |
c13f09d0 | 1017 | Enable or disable configurable features in processor bus\r |
1018 | interface. It is required by IPF. It is required by IPF. The PAL procedure\r | |
1019 | supports the Static Registers calling convention. It could be\r | |
1020 | called at physical mode.\r | |
9c2369c1 | 1021 | \r |
c13f09d0 | 1022 | @param Index Index of PAL_BUS_SET_FEATURES within the list\r |
1023 | of PAL procedures.\r | |
9c2369c1 | 1024 | \r |
c13f09d0 | 1025 | @param FeatureSelect 64-bit vector denoting desired state of\r |
1026 | each feature (1=select, 0=non-select).\r | |
1027 | \r | |
1028 | @return Status 0 - Call completed without error\r | |
1029 | \r | |
1030 | @return Status -2 - Invalid argument\r | |
1031 | \r | |
1032 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1033 | \r |
c13f09d0 | 1034 | **/\r |
1035 | #define PAL_BUS_SET_FEATURES 10\r | |
1036 | \r | |
1037 | \r | |
1038 | /**\r | |
9c2369c1 | 1039 | \r |
c13f09d0 | 1040 | PAL Procedure - PAL_DEBUG_INFO.\r |
9c2369c1 | 1041 | \r |
c13f09d0 | 1042 | Return the number of instruction and data breakpoint\r |
1043 | registers. It is required by IPF. It is required by IPF. The\r | |
1044 | PAL procedure supports the Static Registers calling\r | |
1045 | convention. It could be called at physical mode and virtual\r | |
1046 | mode.\r | |
9c2369c1 | 1047 | \r |
c13f09d0 | 1048 | @param Index Index of PAL_DEBUG_INFO within the list of PAL\r |
1049 | procedures.\r | |
9c2369c1 | 1050 | \r |
c13f09d0 | 1051 | @return R9 Unsigned 64-bit integer denoting the number of\r |
1052 | pairs of instruction debug registers implemented\r | |
9c2369c1 | 1053 | by the processor.\r |
1054 | \r | |
c13f09d0 | 1055 | @return R10 Unsigned 64-bit integer denoting the number of\r |
1056 | pairs of data debug registers implemented by the\r | |
1057 | processor.\r | |
9c2369c1 | 1058 | \r |
c13f09d0 | 1059 | @return Status 0 - Call completed without error\r |
1060 | \r | |
1061 | @return Status -2 - Invalid argument\r | |
1062 | \r | |
1063 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1064 | \r |
c13f09d0 | 1065 | **/\r |
1066 | #define PAL_DEBUG_INFO 11\r | |
1067 | \r | |
1068 | /**\r | |
9c2369c1 | 1069 | \r |
c13f09d0 | 1070 | PAL Procedure - PAL_FIXED_ADDR.\r |
9c2369c1 | 1071 | \r |
ac644614 | 1072 | Return the fixed component of a processor's directed address.\r |
c13f09d0 | 1073 | It is required by IPF. It is required by IPF. The PAL\r |
1074 | procedure supports the Static Registers calling convention. It\r | |
1075 | could be called at physical mode and virtual mode.\r | |
9c2369c1 | 1076 | \r |
c13f09d0 | 1077 | @param Index Index of PAL_FIXED_ADDR within the list of PAL\r |
1078 | procedures.\r | |
9c2369c1 | 1079 | \r |
1080 | @return R9 Fixed geographical address of this processor.\r | |
1081 | \r | |
1082 | \r | |
c13f09d0 | 1083 | @return Status 0 - Call completed without error\r |
1084 | \r | |
1085 | @return Status -2 - Invalid argument\r | |
1086 | \r | |
1087 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1088 | \r |
c13f09d0 | 1089 | **/\r |
1090 | #define PAL_FIXED_ADDR 12\r | |
1091 | \r | |
1092 | /**\r | |
9c2369c1 | 1093 | \r |
c13f09d0 | 1094 | PAL Procedure - PAL_FREQ_BASE.\r |
9c2369c1 | 1095 | \r |
c13f09d0 | 1096 | Return the frequency of the output clock for use by the\r |
1097 | platform, if generated by the processor. It is optinal. The\r | |
1098 | PAL procedure supports the Static Registers calling\r | |
1099 | convention. It could be called at physical mode and virtual\r | |
1100 | mode.\r | |
9c2369c1 | 1101 | \r |
c13f09d0 | 1102 | @param Index Index of PAL_FREQ_BASE within the list of PAL\r |
1103 | procedures.\r | |
9c2369c1 | 1104 | \r |
c13f09d0 | 1105 | @return R9 Base frequency of the platform if generated by the\r |
1106 | processor chip.\r | |
9c2369c1 | 1107 | \r |
1108 | \r | |
c13f09d0 | 1109 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1110 | \r |
c13f09d0 | 1111 | @return Status -1 - Unimplemented procedure\r |
1112 | \r | |
1113 | @return Status -2 - Invalid argument\r | |
1114 | \r | |
1115 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1116 | \r |
c13f09d0 | 1117 | **/\r |
1118 | #define PAL_FREQ_BASE 13\r | |
1119 | \r | |
1120 | \r | |
1121 | /**\r | |
9c2369c1 | 1122 | \r |
c13f09d0 | 1123 | PAL Procedure - PAL_FREQ_RATIOS.\r |
9c2369c1 | 1124 | \r |
c13f09d0 | 1125 | Return ratio of processor, bus, and interval time counter to\r |
1126 | processor input clock or output clock for platform use, if\r | |
1127 | generated by the processor. It is required by IPF. The PAL\r | |
1128 | procedure supports the Static Registers calling convention. It\r | |
1129 | could be called at physical mode and virtual mode.\r | |
9c2369c1 | 1130 | \r |
c13f09d0 | 1131 | @param Index Index of PAL_FREQ_RATIOS within the list of PAL\r |
1132 | procedures.\r | |
9c2369c1 | 1133 | \r |
c13f09d0 | 1134 | @return R9 Ratio of the processor frequency to the input\r |
1135 | clock of the processor, if the platform clock is\r | |
1136 | generated externally or to the output clock to the\r | |
1137 | platform, if the platform clock is generated by\r | |
1138 | the processor.\r | |
9c2369c1 | 1139 | \r |
c13f09d0 | 1140 | @return R10 Ratio of the bus frequency to the input clock of\r |
1141 | the processor, if the platform clock is generated\r | |
1142 | externally or to the output clock to the platform,\r | |
1143 | if the platform clock is generated by the\r | |
1144 | processor.\r | |
9c2369c1 | 1145 | \r |
c13f09d0 | 1146 | @return R11 Ratio of the interval timer counter rate to input\r |
1147 | clock of the processor, if the platform clock is\r | |
1148 | generated externally or to the output clock to the\r | |
1149 | platform, if the platform clock is generated by\r | |
1150 | the processor.\r | |
9c2369c1 | 1151 | \r |
c13f09d0 | 1152 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1153 | \r |
c13f09d0 | 1154 | @return Status -2 - Invalid argument\r |
1155 | \r | |
1156 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1157 | \r |
c13f09d0 | 1158 | **/\r |
1159 | #define PAL_FREQ_RATIOS 14\r | |
1160 | \r | |
1161 | /**\r | |
9c2369c1 | 1162 | \r |
c13f09d0 | 1163 | @param NumberOfLogicalProcessors Total number of logical\r |
1164 | processors on this physical\r | |
1165 | processor package that are\r | |
1166 | enabled.\r | |
1167 | \r | |
1168 | @param ThreadsPerCore Number of threads per core.\r | |
1169 | \r | |
1170 | @param CoresPerProcessor Total number of cores on this\r | |
1171 | physical processor package.\r | |
1172 | \r | |
1173 | @param PhysicalProcessorPackageId Physical processor package\r | |
1174 | identifier which was\r | |
1175 | assigned at reset by the\r | |
1176 | platform or bus\r | |
1177 | controller. This value may\r | |
1178 | or may not be unique\r | |
1179 | across the entire platform\r | |
1180 | since it depends on the\r | |
1181 | platform vendor's policy.\r | |
1182 | **/\r | |
1183 | typedef struct {\r | |
1184 | UINT64 NumberOfLogicalProcessors:16;\r | |
1185 | UINT64 ThreadsPerCore:8;\r | |
1186 | UINT64 Reserved1:8;\r | |
1187 | UINT64 CoresPerProcessor;\r | |
1188 | UINT64 Reserved2:8;\r | |
1189 | UINT64 PhysicalProcessorPackageId:8;\r | |
1190 | UINT64 Reserved3:8;\r | |
1191 | } PAL_LOGICAL_PROCESSPR_OVERVIEW;\r | |
1192 | \r | |
1193 | /**\r | |
9c2369c1 | 1194 | \r |
c13f09d0 | 1195 | @param ThreadId The thread identifier of the logical\r |
1196 | processor for which information is being\r | |
1197 | returned. This value will be unique on a per\r | |
1198 | core basis.\r | |
1199 | \r | |
1200 | @param CoreId The core identifier of the logical processor\r | |
1201 | for which information is being returned.\r | |
1202 | This value will be unique on a per physical\r | |
1203 | processor package basis.\r | |
1204 | \r | |
1205 | **/\r | |
1206 | typedef struct {\r | |
1207 | UINT64 ThreadId:16;\r | |
1208 | UINT64 Reserved1:16;\r | |
1209 | UINT64 CoreId:16;\r | |
1210 | UINT64 Reserved2:16;\r | |
1211 | } PAL_LOGICAL_PROCESSORN_INFO1;\r | |
1212 | \r | |
1213 | \r | |
1214 | /**\r | |
9c2369c1 | 1215 | \r |
c13f09d0 | 1216 | @param LogicalAddress Geographical address of the logical\r |
1217 | processor for which information is being\r | |
1218 | returned. This is the same value that is\r | |
1219 | returned by the PAL_FIXED_ADDR procedure\r | |
1220 | when it is called on the logical\r | |
1221 | processor.\r | |
1222 | \r | |
1223 | \r | |
1224 | **/\r | |
1225 | typedef struct {\r | |
1226 | UINT64 LogicalAddress:16;\r | |
1227 | UINT64 Reserved:48;\r | |
1228 | } PAL_LOGICAL_PROCESSORN_INFO2;\r | |
1229 | \r | |
1230 | /**\r | |
9c2369c1 | 1231 | \r |
c13f09d0 | 1232 | PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r |
9c2369c1 | 1233 | \r |
c13f09d0 | 1234 | Return information on which logical processors map to a\r |
1235 | physical processor die. It is optinal. The PAL procedure\r | |
1236 | supports the Static Registers calling convention. It could be\r | |
1237 | called at physical mode and virtual mode.\r | |
9c2369c1 | 1238 | \r |
c13f09d0 | 1239 | @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r |
1240 | procedures.\r | |
9c2369c1 | 1241 | \r |
c13f09d0 | 1242 | @param ProcessorNumber Signed 64-bit integer that specifies\r |
1243 | for which logical processor\r | |
1244 | information is being requested. When\r | |
1245 | this input argument is -1, information\r | |
1246 | is returned about the logical\r | |
1247 | processor on which the procedure call\r | |
1248 | is made. This input argument must be\r | |
1249 | in the range of 1 up to one less than\r | |
1250 | the number of logical processors\r | |
1251 | returned by num_log in the\r | |
1252 | log_overview return value.\r | |
9c2369c1 | 1253 | \r |
1254 | \r | |
c13f09d0 | 1255 | @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r |
9c2369c1 | 1256 | \r |
c13f09d0 | 1257 | @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r |
9c2369c1 | 1258 | \r |
c13f09d0 | 1259 | @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r |
9c2369c1 | 1260 | \r |
1261 | \r | |
c13f09d0 | 1262 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1263 | \r |
c13f09d0 | 1264 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 1265 | \r |
c13f09d0 | 1266 | @return Status -2 - Invalid argument\r |
1267 | \r | |
1268 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1269 | \r |
c13f09d0 | 1270 | **/\r |
1271 | #define PAL_LOGICAL_TO_PHYSICAL 42\r | |
1272 | \r | |
1273 | \r | |
1274 | /**\r | |
9c2369c1 | 1275 | \r |
c13f09d0 | 1276 | @param NumberOfPmcPairs Unsigned 8-bit number defining the\r |
1277 | number of generic PMC/PMD pairs.\r | |
1278 | \r | |
1279 | @param WidthOfCounter Unsigned 8-bit number in the range\r | |
1280 | 0:60 defining the number of\r | |
1281 | implemented counter bits.\r | |
1282 | \r | |
1283 | @param TypeOfCycleCounting Unsigned 8-bit number defining the\r | |
1284 | event type for counting processor\r | |
1285 | cycles.\r | |
1286 | \r | |
1287 | \r | |
1288 | @param TypeOfRetiredInstructionBundle Retired Unsigned 8-bit\r | |
1289 | number defining the\r | |
1290 | event type for retired\r | |
1291 | instruction bundles.\r | |
1292 | \r | |
1293 | **/\r | |
1294 | typedef struct {\r | |
1295 | UINT64 NumberOfPmcPairs:8;\r | |
1296 | UINT64 WidthOfCounter:8;\r | |
1297 | UINT64 TypeOfCycleCounting:8;\r | |
1298 | UINT64 TypeOfRetiredInstructionBundle:8;\r | |
1299 | UINT64 Reserved:32;\r | |
1300 | } PAL_PERFORMANCE_INFO;\r | |
1301 | \r | |
1302 | /**\r | |
9c2369c1 | 1303 | \r |
c13f09d0 | 1304 | PAL Procedure - PAL_PERF_MON_INFO.\r |
9c2369c1 | 1305 | \r |
c13f09d0 | 1306 | Return the number and type of performance monitors. It is\r |
1307 | required by IPF. The PAL procedure supports the Static\r | |
1308 | Registers calling convention. It could be called at physical\r | |
1309 | mode and virtual mode.\r | |
9c2369c1 | 1310 | \r |
c13f09d0 | 1311 | @param Index Index of PAL_PERF_MON_INFO within the list of\r |
1312 | PAL procedures.\r | |
9c2369c1 | 1313 | \r |
c13f09d0 | 1314 | @param PerformanceBuffer An address to an 8-byte aligned\r |
1315 | 128-byte memory buffer.\r | |
9c2369c1 | 1316 | \r |
1317 | \r | |
c13f09d0 | 1318 | @return R9 Information about the performance monitors\r |
1319 | implemented. See PAL_PERFORMANCE_INFO;\r | |
9c2369c1 | 1320 | \r |
c13f09d0 | 1321 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1322 | \r |
c13f09d0 | 1323 | @return Status -2 - Invalid argument\r |
1324 | \r | |
1325 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1326 | \r |
c13f09d0 | 1327 | **/\r |
1328 | #define PAL_PERF_MON_INFO 15\r | |
1329 | \r | |
6ef95099 | 1330 | #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0\r |
1331 | #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r | |
1332 | \r | |
c13f09d0 | 1333 | /**\r |
9c2369c1 | 1334 | \r |
c13f09d0 | 1335 | PAL Procedure - PAL_PLATFORM_ADDR.\r |
9c2369c1 | 1336 | \r |
c13f09d0 | 1337 | Specify processor interrupt block address and I/O port space\r |
1338 | address. It is required by IPF. The PAL procedure supports the\r | |
1339 | Static Registers calling convention. It could be called at\r | |
1340 | physical mode and virtual mode.\r | |
9c2369c1 | 1341 | \r |
c13f09d0 | 1342 | @param Index Index of PAL_PLATFORM_ADDR within the list of\r |
1343 | PAL procedures.\r | |
9c2369c1 | 1344 | \r |
c13f09d0 | 1345 | @param Type Unsigned 64-bit integer specifying the type of\r |
1346 | block. 0 indicates that the processor interrupt\r | |
1347 | block pointer should be initialized. 1 indicates\r | |
1348 | that the processor I/O block pointer should be\r | |
1349 | initialized.\r | |
9c2369c1 | 1350 | \r |
c13f09d0 | 1351 | @param Address Unsigned 64-bit integer specifying the address\r |
1352 | to which the processor I/O block or interrupt\r | |
1353 | block shall be set. The address must specify\r | |
1354 | an implemented physical address on the\r | |
1355 | processor model, bit 63 is ignored.\r | |
9c2369c1 | 1356 | \r |
1357 | \r | |
c13f09d0 | 1358 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1359 | \r |
c13f09d0 | 1360 | @return Status -1 - Unimplemented procedure.\r |
9c2369c1 | 1361 | \r |
c13f09d0 | 1362 | @return Status -2 - Invalid argument\r |
1363 | \r | |
1364 | @return Status -3 - Call completed with error.\r | |
9c2369c1 | 1365 | \r |
c13f09d0 | 1366 | **/\r |
1367 | #define PAL_PLATFORM_ADDR 16\r | |
1368 | \r | |
1369 | \r | |
1370 | /**\r | |
9c2369c1 | 1371 | \r |
c13f09d0 | 1372 | @param EnableBerrPromotion Bit63. Enable BERR promotion. When\r |
1373 | 1, the Bus Error (BERR) signal is\r | |
1374 | promoted to the Bus Initialization\r | |
1375 | (BINIT) signal, and the BINIT pin\r | |
1376 | is asserted on the occurrence of\r | |
1377 | each Bus Error. Setting this bit\r | |
1378 | has no effect if BINIT signalling\r | |
1379 | is disabled. (See\r | |
1380 | PAL_BUS_GET/SET_FEATURES)\r | |
9c2369c1 | 1381 | \r |
c13f09d0 | 1382 | @param EnableMcaPromotion Bit62, Enable MCA promotion. When\r |
1383 | 1, machine check aborts (MCAs) are\r | |
1384 | promoted to the Bus Error signal,\r | |
1385 | and the BERR pin is assert on each\r | |
1386 | occurrence of an MCA. Setting this\r | |
1387 | bit has no effect if BERR\r | |
1388 | signalling is disabled. (See\r | |
1389 | PAL_BUS_GET/SET_FEATURES)\r | |
1390 | \r | |
1391 | @param EnableMcaToBinitPromotion Bit61, Enable MCA to BINIT\r | |
1392 | promotion. When 1, machine\r | |
1393 | check aborts (MCAs) are\r | |
1394 | promoted to the Bus\r | |
1395 | Initialization signal, and\r | |
1396 | the BINIT pin is assert on\r | |
1397 | each occurrence of an MCA.\r | |
1398 | Setting this bit has no\r | |
1399 | effect if BINIT signalling\r | |
1400 | is disabled. (See\r | |
1401 | PAL_BUS_GET/SET_FEATURES)\r | |
1402 | \r | |
1403 | @param EnableCmciPromotion Bit60, Enable CMCI promotion When\r | |
1404 | 1, Corrected Machine Check\r | |
1405 | Interrupts (CMCI) are promoted to\r | |
1406 | MCAs. They are also further\r | |
1407 | promoted to BERR if bit 39, Enable\r | |
1408 | MCA promotion, is also set and\r | |
1409 | they are promoted to BINIT if bit\r | |
1410 | 38, Enable MCA to BINIT promotion,\r | |
1411 | is also set. This bit has no\r | |
1412 | effect if MCA signalling is\r | |
1413 | disabled (see\r | |
1414 | PAL_BUS_GET/SET_FEATURES)\r | |
1415 | \r | |
1416 | @param DisableCache Bit59, Disable Cache. When 0, the\r | |
1417 | processor performs cast outs on\r | |
1418 | cacheable pages and issues and responds\r | |
1419 | to coherency requests normally. When 1,\r | |
1420 | the processor performs a memory access\r | |
1421 | for each reference regardless of cache\r | |
1422 | contents and issues no coherence\r | |
1423 | requests and responds as if the line\r | |
1424 | were not present. Cache contents cannot\r | |
1425 | be relied upon when the cache is\r | |
1426 | disabled. WARNING: Semaphore\r | |
1427 | instructions may not be atomic or may\r | |
1428 | cause Unsupported Data Reference faults\r | |
1429 | if caches are disabled.\r | |
1430 | \r | |
1431 | @param DisableCoherency Bit58, Disable Coherency. When 0,\r | |
1432 | the processor uses normal coherency\r | |
1433 | requests and responses. When 1, the\r | |
1434 | processor answers all requests as if\r | |
1435 | the line were not present.\r | |
1436 | \r | |
1437 | @param DisableDPM Bit57, Disable Dynamic Power Management\r | |
1438 | (DPM). When 0, the hardware may reduce\r | |
1439 | power consumption by removing the clock\r | |
1440 | input from idle functional units. When 1,\r | |
1441 | all functional units will receive clock\r | |
1442 | input, even when idle.\r | |
1443 | \r | |
1444 | @param DisableBinitWithTimeout Bit56, Disable a BINIT on\r | |
1445 | internal processor time-out.\r | |
1446 | When 0, the processor may\r | |
1447 | generate a BINIT on an\r | |
1448 | internal processor time-out.\r | |
1449 | When 1, the processor will not\r | |
1450 | generate a BINIT on an\r | |
1451 | internal processor time-out.\r | |
1452 | The event is silently ignored.\r | |
1453 | \r | |
1454 | \r | |
1455 | @param EnableEnvNotification Bit55, Enable external\r | |
1456 | notification when the processor\r | |
1457 | detects hardware errors caused\r | |
1458 | by environmental factors that\r | |
1459 | could cause loss of\r | |
1460 | deterministic behavior of the\r | |
1461 | processor. When 1, this bit will\r | |
1462 | enable external notification,\r | |
1463 | when 0 external notification is\r | |
1464 | not provided. The type of\r | |
1465 | external notification of these\r | |
1466 | errors is processor-dependent. A\r | |
1467 | loss of processor deterministic\r | |
1468 | behavior is considered to have\r | |
1469 | occurred if these\r | |
1470 | environmentally induced errors\r | |
1471 | cause the processor to deviate\r | |
1472 | from its normal execution and\r | |
1473 | eventually causes different\r | |
1474 | behavior which can be observed\r | |
1475 | at the processor bus pins.\r | |
1476 | Processor errors that do not\r | |
1477 | have this effects (i.e.,\r | |
1478 | software induced machine checks)\r | |
1479 | may or may not be promoted\r | |
1480 | depending on the processor\r | |
1481 | implementation.\r | |
1482 | \r | |
1483 | @param EnableVmsw Bit54, Enable the use of the vmsw\r | |
1484 | instruction. When 0, the vmsw instruction\r | |
1485 | causes a Virtualization fault when\r | |
1486 | executed at the most privileged level.\r | |
1487 | When 1, this bit will enable normal\r | |
1488 | operation of the vmsw instruction.\r | |
1489 | \r | |
1490 | @param EnableMcaOnDataPoisoning Bit53, Enable MCA signaling\r | |
1491 | on data-poisoning event\r | |
1492 | detection. When 0, a CMCI\r | |
1493 | will be signaled on error\r | |
1494 | detection. When 1, an MCA\r | |
1495 | will be signaled on error\r | |
1496 | detection. If this feature\r | |
1497 | is not supported, then the\r | |
1498 | corresponding argument is\r | |
1499 | ignored when calling\r | |
1500 | PAL_PROC_SET_FEATURES. Note\r | |
1501 | that the functionality of\r | |
1502 | this bit is independent of\r | |
1503 | the setting in bit 60\r | |
1504 | (Enable CMCI promotion), and\r | |
1505 | that the bit 60 setting does\r | |
1506 | not affect CMCI signaling\r | |
1507 | for data-poisoning related\r | |
1508 | events. Volume 2: Processor\r | |
1509 | Abstraction Layer 2:431\r | |
1510 | PAL_PROC_GET_FEATURES\r | |
1511 | \r | |
1512 | @param DisablePState Bit52, Disable P-states. When 1, the PAL\r | |
1513 | P-state procedures (PAL_PSTATE_INFO,\r | |
1514 | PAL_SET_PSTATE, PAL_GET_PSTATE) will\r | |
1515 | return with a status of -1\r | |
1516 | (Unimplemented procedure).\r | |
1517 | \r | |
1518 | @param DisableBranchPrediction Bit47, Disable Dynamic branch\r | |
1519 | prediction. When 0, the\r | |
1520 | processor may predict branch\r | |
1521 | targets and speculatively\r | |
1522 | execute, but may not commit\r | |
1523 | results. When 1, the processor\r | |
1524 | must wait until branch targets\r | |
1525 | are known to execute.\r | |
1526 | \r | |
1527 | @param DisableDynamicInsCachePrefetch Bit46, Disable\r | |
1528 | DynamicInstruction Cache\r | |
1529 | Prefetch. When 0, the\r | |
1530 | processor may prefetch\r | |
1531 | into the caches any\r | |
1532 | instruction which has\r | |
1533 | not been executed, but\r | |
1534 | whose execution is\r | |
1535 | likely. When 1,\r | |
1536 | instructions may not be\r | |
1537 | fetched until needed or\r | |
1538 | hinted for execution.\r | |
1539 | (Prefetch for a hinted\r | |
1540 | branch is allowed even\r | |
1541 | when dynamic instruction\r | |
1542 | cache prefetch is\r | |
1543 | disabled.)\r | |
1544 | \r | |
1545 | @param DisableDynamicDataCachePrefetch Bit45, Disable Dynamic\r | |
1546 | Data Cache Prefetch.\r | |
1547 | When 0, the processor\r | |
1548 | may prefetch into the\r | |
1549 | caches any data which\r | |
1550 | has not been accessed\r | |
1551 | by instruction\r | |
1552 | execution, but which\r | |
1553 | is likely to be\r | |
1554 | accessed. When 1, no\r | |
1555 | data may be fetched\r | |
1556 | until it is needed for\r | |
1557 | instruction execution\r | |
1558 | or is fetched by an\r | |
1559 | lfetch instruction.\r | |
1560 | \r | |
1561 | @param DisableSpontaneousDeferral Bit44, Disable Spontaneous\r | |
1562 | Deferral. When 1, the\r | |
1563 | processor may optionally\r | |
1564 | defer speculative loads\r | |
1565 | that do not encounter any\r | |
1566 | exception conditions, but\r | |
1567 | that trigger other\r | |
1568 | implementation-dependent\r | |
1569 | conditions (e.g., cache\r | |
1570 | miss). When 0, spontaneous\r | |
1571 | deferral is disabled.\r | |
1572 | \r | |
1573 | @param DisableDynamicPrediction Bit43, Disable Dynamic\r | |
1574 | Predicate Prediction. When\r | |
1575 | 0, the processor may predict\r | |
1576 | predicate results and\r | |
1577 | execute speculatively, but\r | |
1578 | may not commit results until\r | |
1579 | the actual predicates are\r | |
1580 | known. When 1, the processor\r | |
1581 | shall not execute predicated\r | |
1582 | instructions until the\r | |
1583 | actual predicates are known.\r | |
1584 | \r | |
1585 | @param NoXr1ThroughXr3 Bit42, No XR1 through XR3 implemented.\r | |
1586 | Denotes whether XR1 XR3 are\r | |
1587 | implemented for machine check\r | |
1588 | recovery. This feature may only be\r | |
1589 | interrogated by PAL_PROC_GET_FEATURES.\r | |
1590 | It may not be enabled or disabled by\r | |
1591 | PAL_PROC_SET_FEATURES. The\r | |
1592 | corresponding argument is ignored.\r | |
1593 | \r | |
1594 | @param NoXipXpsrXfs Bit41, No XIP, XPSR, and XFS\r | |
1595 | implemented. Denotes whether XIP, XPSR,\r | |
1596 | and XFS are implemented for machine\r | |
1597 | check recovery. This feature may only be\r | |
1598 | interrogated by PAL_PROC_GET_FEATURES.\r | |
1599 | It may not be enabled or disabled by\r | |
1600 | PAL_PROC_SET_FEATURES. The corresponding\r | |
1601 | argument is ignored.\r | |
1602 | \r | |
1603 | @param NoVM Bit40, No Virtual Machine features implemented.\r | |
1604 | Denotes whether PSR.vm is implemented. This\r | |
1605 | feature may only be interrogated by\r | |
1606 | PAL_PROC_GET_FEATURES. It may not be enabled or\r | |
1607 | disabled by PAL_PROC_SET_FEATURES. The\r | |
1608 | corresponding argument is ignored.\r | |
1609 | \r | |
1610 | @param NoVariablePState Bit39, No Variable P-state\r | |
1611 | performance: A value of 1, indicates\r | |
1612 | that a processor implements\r | |
1613 | techniques to optimize performance\r | |
1614 | for the given P-state power budget\r | |
1615 | by dynamically varying the\r | |
1616 | frequency, such that maximum\r | |
1617 | performance is achieved for the\r | |
1618 | power budget. A value of 0,\r | |
1619 | indicates that P-states have no\r | |
1620 | frequency variation or very small\r | |
1621 | frequency variations for their given\r | |
1622 | power budget. This feature may only\r | |
1623 | be interrogated by\r | |
1624 | PAL_PROC_GET_FEATURES. it may not be\r | |
1625 | enabled or disabled by\r | |
1626 | PAL_PROC_SET_FEATURES. The\r | |
1627 | corresponding argument is ignored.\r | |
1628 | \r | |
1629 | \r | |
1630 | @param NoSimpleImpInUndefinedIns Bit38, No Simple\r | |
1631 | implementation of\r | |
1632 | unimplemented instruction\r | |
1633 | addresses. Denotes how an\r | |
1634 | unimplemented instruction\r | |
1635 | address is recorded in IIP\r | |
1636 | on an Unimplemented\r | |
1637 | Instruction Address trap or\r | |
1638 | fault. When 1, the full\r | |
1639 | unimplemented address is\r | |
1640 | recorded in IIP; when 0, the\r | |
1641 | address is sign extended\r | |
1642 | (virtual addresses) or zero\r | |
1643 | extended (physical\r | |
1644 | addresses). This feature may\r | |
1645 | only be interrogated by\r | |
1646 | PAL_PROC_GET_FEATURES. It\r | |
1647 | may not be enabled or\r | |
1648 | disabled by\r | |
1649 | PAL_PROC_SET_FEATURES. The\r | |
1650 | corresponding argument is\r | |
1651 | ignored.\r | |
1652 | \r | |
1653 | @param NoPresentPmi Bit37, No INIT, PMI, and LINT pins\r | |
1654 | present. Denotes the absence of INIT,\r | |
1655 | PMI, LINT0 and LINT1 pins on the\r | |
1656 | processor. When 1, the pins are absent.\r | |
1657 | When 0, the pins are present. This\r | |
1658 | feature may only be interrogated by\r | |
1659 | PAL_PROC_GET_FEATURES. It may not be\r | |
1660 | enabled or disabled by\r | |
1661 | PAL_PROC_SET_FEATURES. The corresponding\r | |
1662 | argument is ignored.\r | |
1663 | \r | |
1664 | @param FaultInUndefinedIns Bit36, No Unimplemented\r | |
1665 | instruction address reported as\r | |
1666 | fault. Denotes how the processor\r | |
1667 | reports the detection of\r | |
1668 | unimplemented instruction\r | |
1669 | addresses. When 1, the processor\r | |
1670 | reports an Unimplemented\r | |
1671 | Instruction Address fault on the\r | |
1672 | unimplemented address; when 0, it\r | |
1673 | reports an Unimplemented\r | |
1674 | Instruction Address trap on the\r | |
1675 | previous instruction in program\r | |
1676 | order. This feature may only be\r | |
1677 | interrogated by\r | |
1678 | PAL_PROC_GET_FEATURES. It may not\r | |
1679 | be enabled or disabled by\r | |
1680 | PAL_PROC_SET_FEATURES. The\r | |
1681 | corresponding argument is\r | |
1682 | ignored.\r | |
1683 | \r | |
1684 | **/\r | |
1685 | typedef struct {\r | |
1686 | UINT64 Reserved1:36;\r | |
1687 | UINT64 FaultInUndefinedIns:1;\r | |
1688 | UINT64 NoPresentPmi:1;\r | |
1689 | UINT64 NoSimpleImpInUndefinedIns:1;\r | |
1690 | UINT64 NoVariablePState:1;\r | |
1691 | UINT64 NoVM:1;\r | |
1692 | UINT64 NoXipXpsrXfs:1;\r | |
1693 | UINT64 NoXr1ThroughXr3:1;\r | |
1694 | UINT64 DisableDynamicPrediction:1;\r | |
1695 | UINT64 DisableSpontaneousDeferral:1;\r | |
1696 | UINT64 DisableDynamicDataCachePrefetch:1;\r | |
1697 | UINT64 DisableDynamicInsCachePrefetch:1;\r | |
1698 | UINT64 DisableBranchPrediction:1;\r | |
1699 | UINT64 Reserved2:4;\r | |
1700 | UINT64 DisablePState:1;\r | |
1701 | UINT64 EnableMcaOnDataPoisoning:1;\r | |
1702 | UINT64 EnableVmsw:1;\r | |
1703 | UINT64 EnableEnvNotification:1;\r | |
1704 | UINT64 DisableBinitWithTimeout:1;\r | |
1705 | UINT64 DisableDPM:1;\r | |
1706 | UINT64 DisableCoherency:1;\r | |
1707 | UINT64 DisableCache:1;\r | |
1708 | UINT64 EnableCmciPromotion:1;\r | |
1709 | UINT64 EnableMcaToBinitPromotion:1;\r | |
1710 | UINT64 EnableMcaPromotion:1;\r | |
1711 | UINT64 EnableBerrPromotion:1;\r | |
1712 | } PAL_PROCESSOR_FEATURES;\r | |
1713 | \r | |
1714 | /**\r | |
9c2369c1 | 1715 | \r |
c13f09d0 | 1716 | PAL Procedure - PAL_PROC_GET_FEATURES.\r |
9c2369c1 | 1717 | \r |
c13f09d0 | 1718 | Return configurable processor features and their current\r |
1719 | setting. It is required by IPF. The PAL procedure supports the\r | |
1720 | Static Registers calling convention. It could be called at\r | |
1721 | physical mode and virtual mode.\r | |
9c2369c1 | 1722 | \r |
c13f09d0 | 1723 | @param Index Index of PAL_PROC_GET_FEATURES within the list of\r |
1724 | PAL procedures.\r | |
9c2369c1 | 1725 | \r |
c13f09d0 | 1726 | @param Reserved Reserved parameter.\r |
9c2369c1 | 1727 | \r |
c13f09d0 | 1728 | @param FeatureSet Feature set information is being requested\r |
1729 | for.\r | |
9c2369c1 | 1730 | \r |
1731 | \r | |
c13f09d0 | 1732 | @return R9 64-bit vector of features implemented. See\r |
1733 | PAL_PROCESSOR_FEATURES.\r | |
9c2369c1 | 1734 | \r |
c13f09d0 | 1735 | @return R10 64-bit vector of current feature settings. See\r |
1736 | PAL_PROCESSOR_FEATURES.\r | |
9c2369c1 | 1737 | \r |
c13f09d0 | 1738 | @return R11 64-bit vector of features controllable by\r |
1739 | software.\r | |
9c2369c1 | 1740 | \r |
c13f09d0 | 1741 | @return Status 1 - Call completed without error; The\r |
1742 | feature_set passed is not supported but a\r | |
1743 | feature_set of a larger value is supported.\r | |
9c2369c1 | 1744 | \r |
c13f09d0 | 1745 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1746 | \r |
c13f09d0 | 1747 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1748 | \r |
c13f09d0 | 1749 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1750 | \r |
c13f09d0 | 1751 | @return Status -8 - feature_set passed is beyond the maximum\r |
1752 | feature_set supported\r | |
9c2369c1 | 1753 | \r |
c13f09d0 | 1754 | **/\r |
1755 | #define PAL_PROC_GET_FEATURES 17\r | |
1756 | \r | |
1757 | \r | |
1758 | /**\r | |
9c2369c1 | 1759 | \r |
c13f09d0 | 1760 | PAL Procedure - PAL_PROC_SET_FEATURES.\r |
9c2369c1 | 1761 | \r |
c13f09d0 | 1762 | Enable or disable configurable processor features. It is\r |
1763 | required by IPF. The PAL procedure supports the Static\r | |
1764 | Registers calling convention. It could be called at physical\r | |
1765 | mode.\r | |
9c2369c1 | 1766 | \r |
c13f09d0 | 1767 | @param Index Index of PAL_PROC_SET_FEATURES within the list of\r |
1768 | PAL procedures.\r | |
9c2369c1 | 1769 | \r |
c13f09d0 | 1770 | @param FeatureSelect 64-bit vector denoting desired state of\r |
1771 | each feature (1=select, 0=non-select).\r | |
1772 | \r | |
1773 | @param FeatureSet Feature set to apply changes to. See\r | |
1774 | PAL_PROC_GET_FEATURES for more information\r | |
1775 | on feature sets.\r | |
9c2369c1 | 1776 | \r |
1777 | \r | |
1778 | \r | |
c13f09d0 | 1779 | @return Status 1 - Call completed without error; The\r |
1780 | feature_set passed is not supported but a\r | |
1781 | feature_set of a larger value is supported\r | |
9c2369c1 | 1782 | \r |
c13f09d0 | 1783 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1784 | \r |
c13f09d0 | 1785 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1786 | \r |
c13f09d0 | 1787 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1788 | \r |
c13f09d0 | 1789 | @return Status -8 - feature_set passed is beyond the maximum\r |
1790 | feature_set supported\r | |
9c2369c1 | 1791 | \r |
c13f09d0 | 1792 | **/\r |
1793 | #define PAL_PROC_SET_FEATURES 18\r | |
1794 | \r | |
1795 | \r | |
1796 | //\r | |
1797 | // Value of PAL_REGISTER_INFO.InfoRequest.\r | |
9c2369c1 | 1798 | //\r |
c13f09d0 | 1799 | #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r |
1800 | #define PAL_APPLICATION_REGISTER_READABLE 1\r | |
1801 | #define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r | |
1802 | #define PAL_CONTROL_REGISTER_READABLE 3\r | |
1803 | \r | |
1804 | \r | |
1805 | /**\r | |
9c2369c1 | 1806 | \r |
c13f09d0 | 1807 | PAL Procedure - PAL_REGISTER_INFO.\r |
9c2369c1 | 1808 | \r |
c13f09d0 | 1809 | Return AR and CR register information. It is required by IPF.\r |
1810 | The PAL procedure supports the Static Registers calling\r | |
1811 | convention. It could be called at physical mode and virtual\r | |
1812 | mode.\r | |
9c2369c1 | 1813 | \r |
c13f09d0 | 1814 | @param Index Index of PAL_REGISTER_INFO within the list of\r |
1815 | PAL procedures.\r | |
9c2369c1 | 1816 | \r |
c13f09d0 | 1817 | @param InfoRequest Unsigned 64-bit integer denoting what\r |
1818 | register information is requested. See\r | |
1819 | PAL_REGISTER_INFO.InfoRequest above.\r | |
9c2369c1 | 1820 | \r |
c13f09d0 | 1821 | @return R9 64-bit vector denoting information for registers\r |
1822 | 0-63. Bit 0 is register 0, bit 63 is register 63.\r | |
9c2369c1 | 1823 | \r |
c13f09d0 | 1824 | @return R10 64-bit vector denoting information for registers\r |
1825 | 64-127. Bit 0 is register 64, bit 63 is register\r | |
1826 | 127.\r | |
9c2369c1 | 1827 | \r |
1828 | \r | |
c13f09d0 | 1829 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1830 | \r |
c13f09d0 | 1831 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1832 | \r |
c13f09d0 | 1833 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1834 | \r |
1835 | \r | |
c13f09d0 | 1836 | **/\r |
9c2369c1 | 1837 | #define PAL_REGISTER_INFO 39\r |
c13f09d0 | 1838 | \r |
1839 | /**\r | |
9c2369c1 | 1840 | \r |
c13f09d0 | 1841 | PAL Procedure - PAL_RSE_INFO.\r |
9c2369c1 | 1842 | \r |
c13f09d0 | 1843 | Return RSE information. It is required by IPF. The PAL\r |
1844 | procedure supports the Static Registers calling convention. It\r | |
1845 | could be called at physical mode and virtual mode.\r | |
9c2369c1 | 1846 | \r |
c13f09d0 | 1847 | @param Index Index of PAL_RSE_INFO within the list of\r |
1848 | PAL procedures.\r | |
9c2369c1 | 1849 | \r |
c13f09d0 | 1850 | @param InfoRequest Unsigned 64-bit integer denoting what\r |
1851 | register information is requested. See\r | |
1852 | PAL_REGISTER_INFO.InfoRequest above.\r | |
9c2369c1 | 1853 | \r |
c13f09d0 | 1854 | @return R9 Number of physical stacked general registers.\r |
1855 | \r | |
1856 | @return R10 RSE hints supported by processor.\r | |
9c2369c1 | 1857 | \r |
c13f09d0 | 1858 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1859 | \r |
c13f09d0 | 1860 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1861 | \r |
c13f09d0 | 1862 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1863 | \r |
1864 | \r | |
c13f09d0 | 1865 | **/\r |
1866 | #define PAL_RSE_INFO 19\r | |
1867 | \r | |
1868 | /**\r | |
9c2369c1 | 1869 | \r |
c13f09d0 | 1870 | @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r |
1871 | number that provides identification\r | |
1872 | information about the PAL_B firmware.\r | |
1873 | \r | |
1874 | @param PalVendor Is an unsigned 8-bit integer indicating the\r | |
1875 | vendor of the PAL code.\r | |
1876 | \r | |
1877 | @param VersionOfPalB Is a 16-bit binary coded decimal (BCD)\r | |
1878 | number that provides identification\r | |
1879 | information about the PAL_A firmware. In\r | |
1880 | the split PAL_A model, this return value\r | |
1881 | is the version number of the\r | |
1882 | processor-specific PAL_A. The generic\r | |
1883 | PAL_A version is not returned by this\r | |
1884 | procedure in the split PAL_A model.\r | |
1885 | \r | |
1886 | **/\r | |
1887 | typedef struct {\r | |
1888 | UINT64 VersionOfPalB:16;\r | |
1889 | UINT64 Reserved1:8;\r | |
1890 | UINT64 PalVendor:8;\r | |
1891 | UINT64 VersionOfPalA:16;\r | |
1892 | UINT64 Reserved2:16;\r | |
1893 | } PAL_VERSION_INFO;\r | |
1894 | \r | |
1895 | /**\r | |
9c2369c1 | 1896 | \r |
c13f09d0 | 1897 | PAL Procedure - PAL_VERSION.\r |
9c2369c1 | 1898 | \r |
c13f09d0 | 1899 | Return version of PAL code. It is required by IPF. The PAL\r |
1900 | procedure supports the Static Registers calling convention. It\r | |
1901 | could be called at physical mode and virtual mode.\r | |
9c2369c1 | 1902 | \r |
c13f09d0 | 1903 | @param Index Index of PAL_VERSION within the list of\r |
1904 | PAL procedures.\r | |
9c2369c1 | 1905 | \r |
c13f09d0 | 1906 | @param InfoRequest Unsigned 64-bit integer denoting what\r |
1907 | register information is requested. See\r | |
1908 | PAL_REGISTER_INFO.InfoRequest above.\r | |
9c2369c1 | 1909 | \r |
c13f09d0 | 1910 | @return R9 8-byte formatted value returning the minimum PAL\r |
1911 | version needed for proper operation of the\r | |
1912 | processor. See PAL_VERSION_INFO above.\r | |
9c2369c1 | 1913 | \r |
c13f09d0 | 1914 | @return R10 8-byte formatted value returning the current PAL\r |
1915 | version running on the processor. See\r | |
1916 | PAL_VERSION_INFO above.\r | |
9c2369c1 | 1917 | \r |
c13f09d0 | 1918 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1919 | \r |
c13f09d0 | 1920 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1921 | \r |
c13f09d0 | 1922 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1923 | \r |
1924 | \r | |
c13f09d0 | 1925 | **/\r |
1926 | #define PAL_VERSION 20\r | |
1927 | \r | |
1928 | \r | |
1929 | \r | |
1930 | //\r | |
1931 | // Vectors of PAL_MC_CLEAR_LOG.pending\r | |
9c2369c1 | 1932 | //\r |
c13f09d0 | 1933 | #define PAL_MC_PENDING BIT0\r |
1934 | #define PAL_INIT_PENDING BIT1\r | |
1935 | \r | |
1936 | /**\r | |
9c2369c1 | 1937 | \r |
c13f09d0 | 1938 | PAL Procedure - PAL_MC_CLEAR_LOG.\r |
9c2369c1 | 1939 | \r |
c13f09d0 | 1940 | Clear all error information from processor error logging\r |
1941 | registers. It is required by IPF. The PAL procedure supports\r | |
1942 | the Static Registers calling convention. It could be called at\r | |
1943 | physical mode and virtual mode.\r | |
9c2369c1 | 1944 | \r |
c13f09d0 | 1945 | @param Index Index of PAL_MC_CLEAR_LOG within the list of\r |
1946 | PAL procedures.\r | |
9c2369c1 | 1947 | \r |
1948 | \r | |
c13f09d0 | 1949 | @return R9 64-bit vector denoting whether an event is\r |
1950 | pending. See PAL_MC_CLEAR_LOG.pending above.\r | |
9c2369c1 | 1951 | \r |
1952 | \r | |
c13f09d0 | 1953 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1954 | \r |
c13f09d0 | 1955 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1956 | \r |
c13f09d0 | 1957 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1958 | \r |
1959 | \r | |
c13f09d0 | 1960 | **/\r |
9c2369c1 | 1961 | #define PAL_MC_CLEAR_LOG 21\r |
c13f09d0 | 1962 | \r |
1963 | /**\r | |
9c2369c1 | 1964 | \r |
c13f09d0 | 1965 | PAL Procedure - PAL_MC_DRAIN.\r |
9c2369c1 | 1966 | \r |
c13f09d0 | 1967 | Ensure that all operations that could cause an MCA have\r |
1968 | completed. It is required by IPF. The PAL procedure supports\r | |
1969 | the Static Registers calling convention. It could be called at\r | |
1970 | physical mode and virtual mode.\r | |
9c2369c1 | 1971 | \r |
c13f09d0 | 1972 | @param Index Index of PAL_MC_DRAIN within the list of PAL\r |
1973 | procedures.\r | |
9c2369c1 | 1974 | \r |
1975 | \r | |
c13f09d0 | 1976 | @return Status 0 - Call completed without error\r |
9c2369c1 | 1977 | \r |
c13f09d0 | 1978 | @return Status -2 - Invalid argument\r |
9c2369c1 | 1979 | \r |
c13f09d0 | 1980 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 1981 | \r |
1982 | \r | |
c13f09d0 | 1983 | **/\r |
1984 | #define PAL_MC_DRAIN 22\r | |
1985 | \r | |
1986 | \r | |
1987 | /**\r | |
9c2369c1 | 1988 | \r |
c13f09d0 | 1989 | PAL Procedure - PAL_MC_DYNAMIC_STATE.\r |
9c2369c1 | 1990 | \r |
c13f09d0 | 1991 | Return Processor Dynamic State for logging by SAL. It is\r |
1992 | optional. The PAL procedure supports the Static Registers\r | |
1993 | calling convention. It could be called at physical mode.\r | |
9c2369c1 | 1994 | \r |
c13f09d0 | 1995 | @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r |
1996 | procedures.\r | |
9c2369c1 | 1997 | \r |
c13f09d0 | 1998 | @param Offset Offset of the next 8 bytes of Dynamic Processor\r |
1999 | State to return. (multiple of 8).\r | |
9c2369c1 | 2000 | \r |
c13f09d0 | 2001 | @return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r |
2002 | Processor State returned.\r | |
9c2369c1 | 2003 | \r |
c13f09d0 | 2004 | @return R10 Next 8 bytes of Dynamic Processor State.\r |
9c2369c1 | 2005 | \r |
c13f09d0 | 2006 | @return Status 0 - Call completed without error\r |
9c2369c1 | 2007 | \r |
c13f09d0 | 2008 | @return Status -1 - Unimplemented procedure.\r |
9c2369c1 | 2009 | \r |
c13f09d0 | 2010 | @return Status -2 - Invalid argument\r |
9c2369c1 | 2011 | \r |
c13f09d0 | 2012 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 2013 | \r |
2014 | \r | |
c13f09d0 | 2015 | **/\r |
9c2369c1 | 2016 | #define PAL_MC_DYNAMIC_STATE 24\r |
c13f09d0 | 2017 | \r |
2018 | \r | |
2019 | \r | |
2020 | //\r | |
2021 | // Values of PAL_MC_ERROR_INFO.InfoIndex.\r | |
9c2369c1 | 2022 | //\r |
c13f09d0 | 2023 | #define PAL_PROCESSOR_ERROR_MAP 0\r |
2024 | #define PAL_PROCESSOR_STATE_PARAM 1\r | |
2025 | #define PAL_STRUCTURE_SPECIFIC_ERROR 2\r | |
2026 | \r | |
2027 | /**\r | |
9c2369c1 | 2028 | \r |
c13f09d0 | 2029 | @param CoreId Bit3:0, Processor core ID (default is 0 for\r |
2030 | processors with a single core)\r | |
2031 | \r | |
2032 | @param ThreadId Bit7:4, Logical thread ID (default is 0 for\r | |
9c2369c1 | 2033 | processors that execute a single thread)\r |
c13f09d0 | 2034 | \r |
2035 | @param InfoOfInsCache Bit11:8, Error information is\r | |
2036 | available for 1st, 2nd, 3rd, and 4th\r | |
2037 | level instruction caches.\r | |
2038 | \r | |
2039 | @param InfoOfDataCache Bit15:12, Error information is\r | |
2040 | available for 1st, 2nd, 3rd, and 4th\r | |
2041 | level data/unified caches.\r | |
2042 | \r | |
2043 | @param InfoOfInsTlb Bit19:16 Error information is available\r | |
2044 | for 1st, 2nd, 3rd, and 4th level\r | |
2045 | instruction TLB.\r | |
2046 | \r | |
2047 | @param InfoOfDataTlb Bit23:20, Error information is available\r | |
2048 | for 1st, 2nd, 3rd, and 4th level\r | |
2049 | data/unified TLB\r | |
2050 | \r | |
2051 | @param InfoOfProcessorBus Bit27:24 Error information is\r | |
2052 | available for the 1st, 2nd, 3rd,\r | |
2053 | and 4th level processor bus\r | |
2054 | hierarchy.\r | |
2055 | \r | |
2056 | @param InfoOfRegisterFile Bit31:28 Error information is\r | |
2057 | available on register file\r | |
2058 | structures.\r | |
2059 | \r | |
2060 | @param InfoOfMicroArch Bit47:32, Error information is\r | |
2061 | available on micro-architectural\r | |
2062 | structures.\r | |
2063 | \r | |
2064 | **/\r | |
2065 | typedef struct {\r | |
2066 | UINT64 CoreId:4;\r | |
2067 | UINT64 ThreadId:4;\r | |
2068 | UINT64 InfoOfInsCache:4;\r | |
2069 | UINT64 InfoOfDataCache:4;\r | |
2070 | UINT64 InfoOfInsTlb:4;\r | |
2071 | UINT64 InfoOfDataTlb:4;\r | |
2072 | UINT64 InfoOfProcessorBus:4;\r | |
2073 | UINT64 InfoOfRegisterFile:4;\r | |
2074 | UINT64 InfoOfMicroArch:4;\r | |
2075 | UINT64 Reserved:16;\r | |
2076 | } PAL_MC_ERROR_INFO_LEVEL_INDEX;\r | |
2077 | \r | |
2078 | //\r | |
2079 | // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r | |
9c2369c1 | 2080 | //\r |
c13f09d0 | 2081 | #define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r |
2082 | #define PAL_ERR_INFO_TARGET_ADDRESS 1\r | |
2083 | #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r | |
2084 | #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3\r | |
2085 | #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r | |
2086 | \r | |
2087 | /**\r | |
2088 | \r | |
2089 | @param Operation Bit3:0, Type of cache operation that caused\r | |
2090 | the machine check: 0 - unknown or internal\r | |
2091 | error 1 - load 2 - store 3 - instruction\r | |
2092 | fetch or instruction prefetch 4 - data\r | |
2093 | prefetch (both hardware and software) 5 -\r | |
2094 | snoop (coherency check) 6 - cast out\r | |
2095 | (explicit or implicit write-back of a cache\r | |
9c2369c1 | 2096 | line) 7 - move in (cache line fill)\r |
c13f09d0 | 2097 | \r |
2098 | @param FailedCacheLevel Bit5:4 Level of cache where the\r | |
2099 | error occurred. A value of 0\r | |
2100 | indicates the first level of cache.\r | |
2101 | \r | |
2102 | @param FailedInDataPart Bit8, Failure located in the data\r | |
2103 | part of the cache line.\r | |
2104 | \r | |
2105 | @param FailedInTagPart Bit9, Failure located in the tag part\r | |
2106 | of the cache line.\r | |
2107 | \r | |
2108 | @param FailedInDataCache Bit10, Failure located in the data\r | |
2109 | cache\r | |
2110 | \r | |
2111 | @param FailedInInsCache Bit11, Failure located in the\r | |
2112 | instruction cache.\r | |
2113 | \r | |
2114 | \r | |
2115 | @param Mesi Bit14:12, 0 - cache line is invalid. 1 - cache\r | |
2116 | line is held shared. 2 - cache line is held\r | |
2117 | exclusive. 3 - cache line is modified. All other\r | |
2118 | values are reserved.\r | |
2119 | \r | |
2120 | @param MesiIsValid Bit15, The mesi field in the cache_check\r | |
2121 | parameter is valid.\r | |
2122 | \r | |
2123 | @param FailedWay Bit20:16, Failure located in the way of\r | |
2124 | the cache indicated by this value.\r | |
2125 | \r | |
2126 | @param WayIndexIsValid Bit21, The way and index field in the\r | |
2127 | cache_check parameter is valid.\r | |
2128 | \r | |
2129 | @param MultipleBitsError Bit23, A multiple-bit error was\r | |
2130 | detected, and data was poisoned for\r | |
2131 | the corresponding cache line during\r | |
9c2369c1 | 2132 | castout.\r |
c13f09d0 | 2133 | \r |
2134 | @param IndexOfCacheLineError Bit51:32, Index of the cache\r | |
2135 | line where the error occurred.\r | |
2136 | \r | |
2137 | @param InstructionSet Bit54, Instruction set. If this value\r | |
2138 | is set to zero, the instruction that\r | |
2139 | generated the machine check was an\r | |
2140 | Intel Itanium instruction. If this bit\r | |
2141 | is set to one, the instruction that\r | |
2142 | generated the machine check was IA-32\r | |
2143 | instruction.\r | |
2144 | \r | |
2145 | @param InstructionSetIsValid Bit55, The is field in the\r | |
2146 | cache_check parameter is valid.\r | |
2147 | \r | |
2148 | @param PrivilegeLevel Bit57:56, Privilege level. The\r | |
2149 | privilege level of the instruction\r | |
2150 | bundle responsible for generating the\r | |
2151 | machine check.\r | |
2152 | \r | |
2153 | @param PrivilegeLevelIsValide Bit58, The pl field of the\r | |
2154 | cache_check parameter is\r | |
2155 | valid.\r | |
2156 | \r | |
2157 | @param McCorrected Bit59, Machine check corrected: This bit\r | |
2158 | is set to one to indicate that the machine\r | |
2159 | check has been corrected.\r | |
2160 | \r | |
2161 | @param TargetAddressIsValid Bit60, Target address is valid:\r | |
2162 | This bit is set to one to\r | |
2163 | indicate that a valid target\r | |
2164 | address has been logged.\r | |
2165 | \r | |
2166 | @param RequesterIdentifier Bit61, Requester identifier: This\r | |
2167 | bit is set to one to indicate that\r | |
2168 | a valid requester identifier has\r | |
2169 | been logged.\r | |
2170 | \r | |
2171 | @param ResponserIdentifier Bit62, Responder identifier: This\r | |
2172 | bit is set to one to indicate that\r | |
2173 | a valid responder identifier has\r | |
2174 | been logged.\r | |
2175 | \r | |
2176 | @param PreciseInsPointer Bit63, Precise instruction pointer.\r | |
2177 | This bit is set to one to indicate\r | |
2178 | that a valid precise instruction\r | |
2179 | pointer has been logged.\r | |
2180 | \r | |
2181 | **/\r | |
2182 | typedef struct {\r | |
2183 | UINT64 Operation:4;\r | |
2184 | UINT64 FailedCacheLevel:2;\r | |
2185 | UINT64 Reserved1:2;\r | |
2186 | UINT64 FailedInDataPart:1;\r | |
2187 | UINT64 FailedInTagPart:1;\r | |
2188 | UINT64 FailedInDataCache:1;\r | |
2189 | UINT64 FailedInInsCache:1;\r | |
2190 | UINT64 Mesi:3;\r | |
2191 | UINT64 MesiIsValid:1;\r | |
2192 | UINT64 FailedWay:5;\r | |
2193 | UINT64 WayIndexIsValid:1;\r | |
2194 | \r | |
2195 | UINT64 Reserved2:1;\r | |
2196 | UINT64 MultipleBitsError:1;\r | |
2197 | UINT64 Reserved3:8;\r | |
2198 | UINT64 IndexOfCacheLineError:20;\r | |
2199 | UINT64 Reserved4:2;\r | |
2200 | UINT64 InstructionSet:1;\r | |
2201 | UINT64 InstructionSetIsValid:1;\r | |
2202 | \r | |
2203 | UINT64 PrivilegeLevel:2;\r | |
2204 | UINT64 PrivilegeLevelIsValide:1;\r | |
2205 | \r | |
2206 | UINT64 McCorrected:1;\r | |
2207 | \r | |
2208 | UINT64 TargetAddressIsValid:1;\r | |
2209 | UINT64 RequesterIdentifier:1;\r | |
2210 | UINT64 ResponserIdentifier:1;\r | |
2211 | UINT64 PreciseInsPointer:1;\r | |
2212 | \r | |
2213 | } PAL_CACHE_CHECK_INFO;\r | |
2214 | \r | |
2215 | /**\r | |
9c2369c1 | 2216 | \r |
c13f09d0 | 2217 | @param FailedSlot Bit7:0, Slot number of the translation\r |
2218 | register where the failure occurred.\r | |
2219 | \r | |
2220 | @param FailedSlotIsValid Bit8, The tr_slot field in the\r | |
2221 | TLB_check parameter is valid.\r | |
2222 | \r | |
2223 | @param TlbLevel Bit11:10, The level of the TLB where the\r | |
2224 | error occurred. A value of 0 indicates the\r | |
9c2369c1 | 2225 | first level of TLB\r |
c13f09d0 | 2226 | \r |
2227 | @param FailedInDataTr Bit16, Error occurred in the data\r | |
2228 | translation registers.\r | |
2229 | \r | |
2230 | @param FailedInInsTr Bit17, Error occurred in the instruction\r | |
2231 | translation registers\r | |
2232 | \r | |
2233 | @param FailedInDataTc Bit18, Error occurred in data\r | |
2234 | translation cache.\r | |
2235 | \r | |
2236 | @param FailedInInsTc Bit19, Error occurred in the instruction\r | |
2237 | translation cache.\r | |
2238 | \r | |
2239 | @param FailedOperation Bit23:20, Type of cache operation that\r | |
2240 | caused the machine check: 0 - unknown\r | |
2241 | 1 - TLB access due to load instruction\r | |
2242 | 2 - TLB access due to store\r | |
2243 | instruction 3 - TLB access due to\r | |
2244 | instruction fetch or instruction\r | |
2245 | prefetch 4 - TLB access due to data\r | |
2246 | prefetch (both hardware and software)\r | |
2247 | 5 - TLB shoot down access 6 - TLB\r | |
2248 | probe instruction (probe, tpa) 7 -\r | |
2249 | move in (VHPT fill) 8 - purge (insert\r | |
2250 | operation that purges entries or a TLB\r | |
2251 | purge instruction) All other values\r | |
2252 | are reserved.\r | |
2253 | \r | |
2254 | @param InstructionSet Bit54, Instruction set. If this value\r | |
2255 | is set to zero, the instruction that\r | |
2256 | generated the machine check was an\r | |
2257 | Intel Itanium instruction. If this bit\r | |
2258 | is set to one, the instruction that\r | |
2259 | generated the machine check was IA-32\r | |
2260 | instruction.\r | |
2261 | \r | |
2262 | @param InstructionSetIsValid Bit55, The is field in the\r | |
2263 | TLB_check parameter is valid.\r | |
2264 | \r | |
2265 | @param PrivelegeLevel Bit57:56, Privilege level. The\r | |
2266 | privilege level of the instruction\r | |
2267 | bundle responsible for generating the\r | |
2268 | machine check.\r | |
2269 | \r | |
2270 | @param PrivelegeLevelIsValid Bit58, The pl field of the\r | |
2271 | TLB_check parameter is valid.\r | |
2272 | \r | |
2273 | @param McCorrected Bit59, Machine check corrected: This bit\r | |
2274 | is set to one to indicate that the machine\r | |
2275 | check has been corrected.\r | |
2276 | \r | |
2277 | @param TargetAddressIsValid Bit60, Target address is valid:\r | |
2278 | This bit is set to one to\r | |
2279 | indicate that a valid target\r | |
2280 | address has been logged.\r | |
2281 | \r | |
2282 | @param RequesterIdentifier Bit61 Requester identifier: This\r | |
2283 | bit is set to one to indicate that\r | |
2284 | a valid requester identifier has\r | |
2285 | been logged.\r | |
2286 | \r | |
2287 | @param ResponserIdentifier Bit62, Responder identifier: This\r | |
2288 | bit is set to one to indicate that\r | |
2289 | a valid responder identifier has\r | |
2290 | been logged.\r | |
2291 | \r | |
2292 | @param PreciseInsPointer Bit63 Precise instruction pointer.\r | |
2293 | This bit is set to one to indicate\r | |
2294 | that a valid precise instruction\r | |
2295 | pointer has been logged.\r | |
2296 | **/\r | |
2297 | typedef struct {\r | |
2298 | UINT64 FailedSlot:8;\r | |
2299 | UINT64 FailedSlotIsValid:1;\r | |
2300 | UINT64 Reserved1 :1;\r | |
2301 | UINT64 TlbLevel:2;\r | |
2302 | UINT64 Reserved2 :4;\r | |
2303 | UINT64 FailedInDataTr:1;\r | |
2304 | UINT64 FailedInInsTr:1;\r | |
2305 | UINT64 FailedInDataTc:1;\r | |
2306 | UINT64 FailedInInsTc:1;\r | |
2307 | UINT64 FailedOperation:4;\r | |
2308 | UINT64 Reserved3:30;\r | |
2309 | UINT64 InstructionSet:1;\r | |
2310 | UINT64 InstructionSetIsValid:1;\r | |
2311 | UINT64 PrivelegeLevel:2;\r | |
2312 | UINT64 PrivelegeLevelIsValid:1;\r | |
2313 | UINT64 McCorrected:1;\r | |
2314 | UINT64 TargetAddressIsValid:1;\r | |
2315 | UINT64 RequesterIdentifier:1;\r | |
2316 | UINT64 ResponserIdentifier:1;\r | |
2317 | UINT64 PreciseInsPointer:1;\r | |
2318 | } PAL_TLB_CHECK_INFO;\r | |
2319 | \r | |
2320 | /**\r | |
9c2369c1 | 2321 | \r |
c13f09d0 | 2322 | PAL Procedure - PAL_MC_ERROR_INFO.\r |
9c2369c1 | 2323 | \r |
c13f09d0 | 2324 | Return Processor Machine Check Information and Processor\r |
2325 | Static State for logging by SAL. It is required by IPF. The\r | |
2326 | PAL procedure supports the Static Registers calling\r | |
2327 | convention. It could be called at physical and virtual mode.\r | |
9c2369c1 | 2328 | \r |
c13f09d0 | 2329 | @param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r |
2330 | procedures.\r | |
9c2369c1 | 2331 | \r |
c13f09d0 | 2332 | @param InfoIndex Unsigned 64-bit integer identifying the\r |
2333 | error information that is being requested.\r | |
2334 | See PAL_MC_ERROR_INFO.InfoIndex.\r | |
9c2369c1 | 2335 | \r |
c13f09d0 | 2336 | @param LevelIndex 8-byte formatted value identifying the\r |
2337 | structure to return error information\r | |
2338 | on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r | |
9c2369c1 | 2339 | \r |
c13f09d0 | 2340 | @param ErrorTypeIndex Unsigned 64-bit integer denoting the\r |
2341 | type of error information that is\r | |
2342 | being requested for the structure\r | |
2343 | identified in LevelIndex.\r | |
9c2369c1 | 2344 | \r |
2345 | \r | |
c13f09d0 | 2346 | @return R9 Error information returned. The format of this\r |
2347 | value is dependant on the input values passed.\r | |
9c2369c1 | 2348 | \r |
c13f09d0 | 2349 | @return R10 If this value is zero, all the error information\r |
2350 | specified by err_type_index has been returned. If\r | |
2351 | this value is one, more structure-specific error\r | |
2352 | information is available and the caller needs to\r | |
2353 | make this procedure call again with level_index\r | |
2354 | unchanged and err_type_index, incremented.\r | |
9c2369c1 | 2355 | \r |
2356 | \r | |
c13f09d0 | 2357 | @return Status 0 - Call completed without error\r |
9c2369c1 | 2358 | \r |
c13f09d0 | 2359 | @return Status -2 - Invalid argument\r |
9c2369c1 | 2360 | \r |
c13f09d0 | 2361 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 2362 | \r |
c13f09d0 | 2363 | @return Status -6 - Argument was valid, but no error\r |
2364 | information was available\r | |
9c2369c1 | 2365 | \r |
2366 | \r | |
c13f09d0 | 2367 | **/\r |
2368 | #define PAL_MC_ERROR_INFO 25\r | |
2369 | \r | |
2370 | /**\r | |
9c2369c1 | 2371 | \r |
c13f09d0 | 2372 | PAL Procedure - PAL_MC_EXPECTED.\r |
9c2369c1 | 2373 | \r |
c13f09d0 | 2374 | Set/Reset Expected Machine Check Indicator. It is required by\r |
2375 | IPF. The PAL procedure supports the Static Registers calling\r | |
2376 | convention. It could be called at physical mode.\r | |
9c2369c1 | 2377 | \r |
c13f09d0 | 2378 | @param Index Index of PAL_MC_EXPECTED within the list of PAL\r |
2379 | procedures.\r | |
9c2369c1 | 2380 | \r |
c13f09d0 | 2381 | @param Expected Unsigned integer with a value of 0 or 1 to\r |
2382 | set or reset the hardware resource\r | |
2383 | PALE_CHECK examines for expected machine\r | |
2384 | checks.\r | |
9c2369c1 | 2385 | \r |
c13f09d0 | 2386 | \r |
2387 | @return R9 Unsigned integer denoting whether a machine check\r | |
2388 | was previously expected.\r | |
9c2369c1 | 2389 | \r |
c13f09d0 | 2390 | \r |
2391 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 2392 | \r |
c13f09d0 | 2393 | @return Status -2 - Invalid argument\r |
9c2369c1 | 2394 | \r |
c13f09d0 | 2395 | @return Status -3 - Call completed with error.\r |
2396 | \r | |
2397 | **/\r | |
9c2369c1 | 2398 | #define PAL_MC_EXPECTED 23\r |
c13f09d0 | 2399 | \r |
2400 | /**\r | |
9c2369c1 | 2401 | \r |
c13f09d0 | 2402 | PAL Procedure - PAL_MC_REGISTER_MEM.\r |
9c2369c1 | 2403 | \r |
c13f09d0 | 2404 | Register min-state save area with PAL for machine checks and\r |
2405 | inits. It is required by IPF. The PAL procedure supports the\r | |
2406 | Static Registers calling convention. It could be called at\r | |
2407 | physical mode.\r | |
9c2369c1 | 2408 | \r |
c13f09d0 | 2409 | @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r |
2410 | procedures.\r | |
9c2369c1 | 2411 | \r |
c13f09d0 | 2412 | @param Address Physical address of the buffer to be\r |
2413 | registered with PAL.\r | |
c13f09d0 | 2414 | \r |
9c2369c1 | 2415 | \r |
2416 | \r | |
c13f09d0 | 2417 | @return Status 0 - Call completed without error\r |
9c2369c1 | 2418 | \r |
c13f09d0 | 2419 | @return Status -2 - Invalid argument\r |
9c2369c1 | 2420 | \r |
c13f09d0 | 2421 | @return Status -3 - Call completed with error.\r |
2422 | \r | |
2423 | **/\r | |
9c2369c1 | 2424 | #define PAL_MC_REGISTER_MEM 27\r |
c13f09d0 | 2425 | \r |
2426 | /**\r | |
9c2369c1 | 2427 | \r |
c13f09d0 | 2428 | PAL Procedure - PAL_MC_RESUME.\r |
9c2369c1 | 2429 | \r |
c13f09d0 | 2430 | Restore minimal architected state and return to interrupted\r |
2431 | process. It is required by IPF. The PAL procedure supports the\r | |
2432 | Static Registers calling convention. It could be called at\r | |
2433 | physical mode.\r | |
9c2369c1 | 2434 | \r |
c13f09d0 | 2435 | @param Index Index of PAL_MC_RESUME within the list of PAL\r |
2436 | procedures.\r | |
9c2369c1 | 2437 | \r |
c13f09d0 | 2438 | @param SetCmci Unsigned 64 bit integer denoting whether to\r |
2439 | set the CMC interrupt. A value of 0 indicates\r | |
2440 | not to set the interrupt, a value of 1\r | |
2441 | indicated to set the interrupt, and all other\r | |
2442 | values are reserved.\r | |
2443 | \r | |
2444 | @param SavePtr Physical address of min-state save area used\r | |
2445 | to used to restore processor state.\r | |
2446 | \r | |
2447 | @param NewContext Unsigned 64-bit integer denoting whether\r | |
2448 | the caller is returning to a new context.\r | |
2449 | A value of 0 indicates the caller is\r | |
2450 | returning to the interrupted context, a\r | |
2451 | value of 1 indicates that the caller is\r | |
2452 | returning to a new context.\r | |
c13f09d0 | 2453 | \r |
9c2369c1 | 2454 | \r |
2455 | \r | |
c13f09d0 | 2456 | @return Status -2 - Invalid argument\r |
9c2369c1 | 2457 | \r |
c13f09d0 | 2458 | @return Status -3 - Call completed with error.\r |
2459 | \r | |
2460 | **/\r | |
9c2369c1 | 2461 | #define PAL_MC_RESUME 26\r |
c13f09d0 | 2462 | \r |
2463 | /**\r | |
9c2369c1 | 2464 | \r |
c13f09d0 | 2465 | PAL Procedure - PAL_HALT.\r |
9c2369c1 | 2466 | \r |
c13f09d0 | 2467 | Enter the low-power HALT state or an implementation-dependent\r |
2468 | low-power state. It is optinal. The PAL procedure supports the\r | |
2469 | Static Registers calling convention. It could be called at\r | |
2470 | physical mode.\r | |
9c2369c1 | 2471 | \r |
c13f09d0 | 2472 | @param Index Index of PAL_HALT within the list of PAL\r |
2473 | procedures.\r | |
9c2369c1 | 2474 | \r |
c13f09d0 | 2475 | @param HaltState Unsigned 64-bit integer denoting low power\r |
2476 | state requested.\r | |
2477 | \r | |
2478 | @param IoDetailPtr 8-byte aligned physical address pointer to\r | |
2479 | information on the type of I/O\r | |
2480 | (load/store) requested.\r | |
2481 | \r | |
2482 | \r | |
2483 | @return R9 Value returned if a load instruction is requested\r | |
2484 | in the io_detail_ptr\r | |
2485 | \r | |
9c2369c1 | 2486 | \r |
c13f09d0 | 2487 | @return Status 0 - Call completed without error\r |
2488 | \r | |
2489 | @return Status -1 - Unimplemented procedure\r | |
2490 | \r | |
2491 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2492 | \r |
c13f09d0 | 2493 | @return Status -3 - Call completed with error.\r |
2494 | \r | |
2495 | **/\r | |
2496 | #define PAL_HALT 28\r | |
2497 | \r | |
2498 | \r | |
2499 | /**\r | |
9c2369c1 | 2500 | \r |
c13f09d0 | 2501 | PAL Procedure - PAL_HALT_INFO.\r |
9c2369c1 | 2502 | \r |
c13f09d0 | 2503 | Return the low power capabilities of the processor. It is\r |
2504 | required by IPF. The PAL procedure supports the\r | |
2505 | Stacked Registers calling convention. It could be called at\r | |
2506 | physical and virtual mode.\r | |
9c2369c1 | 2507 | \r |
c13f09d0 | 2508 | @param Index Index of PAL_HALT_INFO within the list of PAL\r |
2509 | procedures.\r | |
9c2369c1 | 2510 | \r |
c13f09d0 | 2511 | @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r |
2512 | on an 8-byte boundary.\r | |
2513 | \r | |
2514 | \r | |
9c2369c1 | 2515 | \r |
c13f09d0 | 2516 | @return Status 0 - Call completed without error\r |
2517 | \r | |
2518 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2519 | \r |
c13f09d0 | 2520 | @return Status -3 - Call completed with error.\r |
2521 | \r | |
2522 | **/\r | |
2523 | #define PAL_HALT_INFO 257\r | |
2524 | \r | |
2525 | \r | |
2526 | /**\r | |
9c2369c1 | 2527 | \r |
c13f09d0 | 2528 | PAL Procedure - PAL_HALT_LIGHT.\r |
9c2369c1 | 2529 | \r |
c13f09d0 | 2530 | Enter the low power LIGHT HALT state. It is required by\r |
2531 | IPF. The PAL procedure supports the Static Registers calling\r | |
2532 | convention. It could be called at physical and virtual mode.\r | |
9c2369c1 | 2533 | \r |
c13f09d0 | 2534 | @param Index Index of PAL_HALT_LIGHT within the list of PAL\r |
2535 | procedures.\r | |
9c2369c1 | 2536 | \r |
2537 | \r | |
c13f09d0 | 2538 | @return Status 0 - Call completed without error\r |
2539 | \r | |
2540 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2541 | \r |
c13f09d0 | 2542 | @return Status -3 - Call completed with error.\r |
2543 | \r | |
2544 | **/\r | |
9c2369c1 | 2545 | #define PAL_HALT_LIGHT 29\r |
c13f09d0 | 2546 | \r |
2547 | /**\r | |
9c2369c1 | 2548 | \r |
c13f09d0 | 2549 | PAL Procedure - PAL_CACHE_LINE_INIT.\r |
9c2369c1 | 2550 | \r |
c13f09d0 | 2551 | Initialize tags and data of a cache line for processor\r |
2552 | testing. It is required by IPF. The PAL procedure supports the\r | |
2553 | Static Registers calling convention. It could be called at\r | |
2554 | physical and virtual mode.\r | |
9c2369c1 | 2555 | \r |
c13f09d0 | 2556 | @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r |
2557 | procedures.\r | |
9c2369c1 | 2558 | \r |
c13f09d0 | 2559 | @param Address Unsigned 64-bit integer value denoting the\r |
2560 | physical address from which the physical page\r | |
2561 | number is to be generated. The address must be\r | |
2562 | an implemented physical address, bit 63 must\r | |
2563 | be zero.\r | |
9c2369c1 | 2564 | \r |
c13f09d0 | 2565 | @param DataValue 64-bit data value which is used to\r |
2566 | initialize the cache line.\r | |
9c2369c1 | 2567 | \r |
2568 | \r | |
c13f09d0 | 2569 | @return Status 0 - Call completed without error\r |
2570 | \r | |
2571 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2572 | \r |
c13f09d0 | 2573 | @return Status -3 - Call completed with error.\r |
2574 | \r | |
2575 | **/\r | |
2576 | #define PAL_CACHE_LINE_INIT 31\r | |
2577 | \r | |
2578 | /**\r | |
9c2369c1 | 2579 | \r |
c13f09d0 | 2580 | PAL Procedure - PAL_CACHE_READ.\r |
9c2369c1 | 2581 | \r |
c13f09d0 | 2582 | Read tag and data of a cache line for diagnostic testing. It\r |
2583 | is optional. The PAL procedure supports the\r | |
2584 | Satcked Registers calling convention. It could be called at\r | |
2585 | physical mode.\r | |
9c2369c1 | 2586 | \r |
c13f09d0 | 2587 | @param Index Index of PAL_CACHE_READ within the list of PAL\r |
2588 | procedures.\r | |
9c2369c1 | 2589 | \r |
c13f09d0 | 2590 | @param LineId 8-byte formatted value describing where in the\r |
2591 | cache to read the data.\r | |
2592 | \r | |
2593 | @param Address 64-bit 8-byte aligned physical address from\r | |
2594 | which to read the data. The address must be an\r | |
2595 | implemented physical address on the processor\r | |
2596 | model with bit 63 set to zero.\r | |
2597 | \r | |
2598 | @return R9 Right-justified value returned from the cache\r | |
2599 | line.\r | |
2600 | \r | |
2601 | @return R10 The number of bits returned in data.\r | |
2602 | \r | |
2603 | @return R11 The status of the cache line.\r | |
2604 | \r | |
2605 | \r | |
9c2369c1 | 2606 | \r |
c13f09d0 | 2607 | @return Status 1 - The word at address was found in the\r |
2608 | cache, but the line was invalid.\r | |
2609 | \r | |
2610 | @return Status 0 - Call completed without error\r | |
2611 | \r | |
2612 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2613 | \r |
c13f09d0 | 2614 | @return Status -3 - Call completed with error.\r |
2615 | \r | |
2616 | @return Status -5 - The word at address was not found in the\r | |
2617 | cache.\r | |
9c2369c1 | 2618 | \r |
c13f09d0 | 2619 | @return Status -7 - The operation requested is not supported\r |
2620 | for this cache_type and level.\r | |
2621 | \r | |
2622 | **/\r | |
9c2369c1 | 2623 | #define PAL_CACHE_READ 259\r |
c13f09d0 | 2624 | \r |
2625 | \r | |
2626 | /**\r | |
9c2369c1 | 2627 | \r |
c13f09d0 | 2628 | Write tag and data of a cache for diagnostic testing. It is\r |
2629 | optional. The PAL procedure supports the Satcked Registers\r | |
2630 | calling convention. It could be called at physical mode.\r | |
9c2369c1 | 2631 | \r |
c13f09d0 | 2632 | @param Index Index of PAL_CACHE_WRITE within the list of PAL\r |
2633 | procedures.\r | |
9c2369c1 | 2634 | \r |
c13f09d0 | 2635 | @param LineId 8-byte formatted value describing where in the\r |
2636 | cache to write the data.\r | |
2637 | \r | |
2638 | @param Address 64-bit 8-byte aligned physical address at\r | |
2639 | which the data should be written. The address\r | |
2640 | must be an implemented physical address on the\r | |
2641 | processor model with bit 63 set to 0.\r | |
2642 | \r | |
2643 | @param Data Unsigned 64-bit integer value to write into\r | |
2644 | the specified part of the cache.\r | |
2645 | \r | |
9c2369c1 | 2646 | \r |
c13f09d0 | 2647 | @return Status 0 - Call completed without error\r |
2648 | \r | |
2649 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2650 | \r |
c13f09d0 | 2651 | @return Status -3 - Call completed with error.\r |
2652 | \r | |
9c2369c1 | 2653 | \r |
c13f09d0 | 2654 | @return Status -7 - The operation requested is not supported\r |
2655 | for this cache_type and level.\r | |
2656 | \r | |
2657 | **/\r | |
2658 | #define PAL_CACHE_WRITE 260\r | |
2659 | \r | |
2660 | /**\r | |
9c2369c1 | 2661 | \r |
c13f09d0 | 2662 | PAL Procedure - PAL_TEST_INFO.\r |
9c2369c1 | 2663 | \r |
c13f09d0 | 2664 | Returns alignment and size requirements needed for the memory\r |
2665 | buffer passed to the PAL_TEST_PROC procedure as well as\r | |
2666 | information on self-test control words for the processor self\r | |
2667 | tests. It is required by IPF. The PAL procedure supports the\r | |
2668 | Static Registers calling convention. It could be called at\r | |
2669 | physical mode.\r | |
9c2369c1 | 2670 | \r |
c13f09d0 | 2671 | @param Index Index of PAL_TEST_INFO within the list of PAL\r |
2672 | procedures.\r | |
9c2369c1 | 2673 | \r |
c13f09d0 | 2674 | @param TestPhase Unsigned integer that specifies which phase\r |
2675 | of the processor self-test information is\r | |
2676 | being requested on. A value of 0 indicates\r | |
2677 | the phase two of the processor self-test and\r | |
2678 | a value of 1 indicates phase one of the\r | |
2679 | processor self-test. All other values are\r | |
2680 | reserved.\r | |
9c2369c1 | 2681 | \r |
c13f09d0 | 2682 | @return R9 Unsigned 64-bit integer denoting the number of\r |
2683 | bytes of main memory needed to perform the second\r | |
2684 | phase of processor self-test.\r | |
9c2369c1 | 2685 | \r |
c13f09d0 | 2686 | @return R10 Unsigned 64-bit integer denoting the alignment\r |
2687 | required for the memory buffer.\r | |
9c2369c1 | 2688 | \r |
c13f09d0 | 2689 | @return R11 48-bit wide bit-field indicating if control of\r |
2690 | the processor self-tests is supported and which\r | |
2691 | bits of the test_control field are defined for\r | |
2692 | use.\r | |
2693 | \r | |
9c2369c1 | 2694 | \r |
c13f09d0 | 2695 | @return Status 0 - Call completed without error\r |
2696 | \r | |
2697 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2698 | \r |
c13f09d0 | 2699 | @return Status -3 - Call completed with error.\r |
2700 | \r | |
2701 | \r | |
2702 | **/\r | |
2703 | #define PAL_TEST_INFO 37\r | |
2704 | \r | |
2705 | /**\r | |
2706 | \r | |
2707 | @param BufferSize Indicates the size in bytes of the memory\r | |
2708 | buffer that is passed to this procedure.\r | |
2709 | BufferSize must be greater than or equal in\r | |
2710 | size to the bytes_needed return value from\r | |
2711 | PAL_TEST_INFO, otherwise this procedure will\r | |
2712 | return with an invalid argument return\r | |
2713 | value.\r | |
2714 | \r | |
2715 | @param TestPhase Defines which phase of the processor\r | |
2716 | self-tests are requested to be run. A value\r | |
2717 | of zero indicates to run phase two of the\r | |
2718 | processor self-tests. Phase two of the\r | |
2719 | processor self-tests are ones that require\r | |
2720 | external memory to execute correctly. A\r | |
2721 | value of one indicates to run phase one of\r | |
2722 | the processor self-tests. Phase one of the\r | |
2723 | processor self-tests are tests run during\r | |
2724 | PALE_RESET and do not depend on external\r | |
2725 | memory to run correctly. When the caller\r | |
2726 | requests to have phase one of the processor\r | |
2727 | self-test run via this procedure call, a\r | |
2728 | memory buffer may be needed to save and\r | |
2729 | restore state as required by the PAL calling\r | |
2730 | conventions. The procedure PAL_TEST_INFO\r | |
2731 | informs the caller about the requirements of\r | |
2732 | the memory buffer.\r | |
2733 | \r | |
2734 | **/\r | |
2735 | typedef struct {\r | |
2736 | UINT64 BufferSize:56;\r | |
2737 | UINT64 TestPhase:8;\r | |
2738 | } PAL_TEST_INFO_INFO;\r | |
2739 | \r | |
2740 | /**\r | |
9c2369c1 | 2741 | \r |
c13f09d0 | 2742 | @param TestControl This is an ordered implementation-specific\r |
2743 | control word that allows the user control\r | |
2744 | over the length and runtime of the\r | |
2745 | processor self-tests. This control word is\r | |
2746 | ordered from the longest running tests up\r | |
2747 | to the shortest running tests with bit 0\r | |
2748 | controlling the longest running test. PAL\r | |
2749 | may not implement all 47-bits of the\r | |
2750 | test_control word. PAL communicates if a\r | |
2751 | bit provides control by placing a zero in\r | |
2752 | that bit. If a bit provides no control,\r | |
2753 | PAL will place a one in it. PAL will have\r | |
2754 | two sets of test_control bits for the two\r | |
2755 | phases of the processor self-test. PAL\r | |
2756 | provides information about implemented\r | |
2757 | test_control bits at the hand-off from PAL\r | |
2758 | to SAL for the firmware recovery check.\r | |
2759 | These test_control bits provide control\r | |
2760 | for phase one of processor self-test. It\r | |
2761 | also provides this information via the PAL\r | |
2762 | procedure call PAL_TEST_INFO for both the\r | |
2763 | phase one and phase two processor tests\r | |
2764 | depending on which information the caller\r | |
2765 | is requesting. PAL interprets these bits\r | |
2766 | as input parameters on two occasions. The\r | |
2767 | first time is when SAL passes control back\r | |
2768 | to PAL after the firmware recovery check.\r | |
2769 | The second time is when a call to\r | |
2770 | PAL_TEST_PROC is made. When PAL interprets\r | |
2771 | these bits it will only interpret\r | |
2772 | implemented test_control bits and will\r | |
2773 | ignore the values located in the\r | |
2774 | unimplemented test_control bits. PAL\r | |
2775 | interprets the implemented bits such that\r | |
2776 | if a bit contains a zero, this indicates\r | |
2777 | to run the test. If a bit contains a one,\r | |
2778 | this indicates to PAL to skip the test. If\r | |
2779 | the cs bit indicates that control is not\r | |
2780 | available, the test_control bits will be\r | |
2781 | ignored or generate an illegal argument in\r | |
2782 | procedure calls if the caller sets these\r | |
2783 | bits.\r | |
2784 | \r | |
2785 | @param ControlSupport This bit defines if an implementation\r | |
2786 | supports control of the PAL self-tests\r | |
2787 | via the self-test control word. If\r | |
2788 | this bit is 0, the implementation does\r | |
2789 | not support control of the processor\r | |
2790 | self-tests via the self-test control\r | |
2791 | word. If this bit is 1, the\r | |
2792 | implementation does support control of\r | |
2793 | the processor self-tests via the\r | |
2794 | self-test control word. If control is\r | |
2795 | not supported, GR37 will be ignored at\r | |
2796 | the hand-off between SAL and PAL after\r | |
2797 | the firmware recovery check and the\r | |
2798 | PAL procedures related to the\r | |
2799 | processor self-tests may return\r | |
2800 | illegal arguments if a user tries to\r | |
2801 | use the self-test control features.\r | |
2802 | \r | |
2803 | **/\r | |
2804 | typedef struct {\r | |
2805 | UINT64 TestControl:47;\r | |
2806 | UINT64 ControlSupport:1;\r | |
2807 | UINT64 Reserved:16;\r | |
2808 | } PAL_SELF_TEST_CONTROL;\r | |
2809 | \r | |
2810 | /**\r | |
9c2369c1 | 2811 | \r |
c13f09d0 | 2812 | @param Attributes Specifies the memory attributes that are\r |
2813 | allowed to be used with the memory buffer\r | |
2814 | passed to this procedure. The attributes\r | |
2815 | parameter is a vector where each bit\r | |
2816 | represents one of the virtual memory\r | |
2817 | attributes defined by the architecture.See\r | |
2818 | MEMORY_AATRIBUTES. The caller is required\r | |
2819 | to support the cacheable attribute for the\r | |
2820 | memory buffer, otherwise an invalid\r | |
2821 | argument will be returned.\r | |
2822 | \r | |
2823 | \r | |
2824 | @param TestControl Is the self-test control word\r | |
2825 | corresponding to the test_phase passed.\r | |
2826 | This test_control directs the coverage and\r | |
2827 | runtime of the processor self-tests\r | |
2828 | specified by the test_phase input\r | |
2829 | argument. Information on if this\r | |
2830 | feature is implemented and the number of\r | |
2831 | bits supported can be obtained by the\r | |
2832 | PAL_TEST_INFO procedure call. If this\r | |
2833 | feature is implemented by the processor,\r | |
2834 | the caller can selectively skip parts of\r | |
2835 | the processor self-test by setting\r | |
2836 | test_control bits to a one. If a bit has a\r | |
2837 | zero, this test will be run. The values in\r | |
2838 | the unimplemented bits are ignored. If\r | |
2839 | PAL_TEST_INFO indicated that the self-test\r | |
2840 | control word is not implemented, this\r | |
2841 | procedure will return with an invalid\r | |
2842 | argument status if the caller sets any of\r | |
2843 | the test_control bits. See\r | |
2844 | PAL_SELF_TEST_CONTROL.\r | |
2845 | **/\r | |
2846 | typedef struct {\r | |
2847 | UINT64 Attributes:8;\r | |
2848 | UINT64 Reserved:8;\r | |
2849 | UINT64 TestControl:48;\r | |
2850 | } PAL_TEST_CONTROL;\r | |
2851 | \r | |
2852 | /**\r | |
9c2369c1 | 2853 | \r |
c13f09d0 | 2854 | PAL Procedure - PAL_TEST_PROC.\r |
9c2369c1 | 2855 | \r |
c13f09d0 | 2856 | Perform late processor self test. It is required by IPF. The\r |
2857 | PAL procedure supports the Static Registers calling\r | |
2858 | convention. It could be called at physical mode.\r | |
9c2369c1 | 2859 | \r |
c13f09d0 | 2860 | @param Index Index of PAL_TEST_PROC within the list of PAL\r |
2861 | procedures.\r | |
9c2369c1 | 2862 | \r |
c13f09d0 | 2863 | @param TestAddress 64-bit physical address of main memory\r |
2864 | area to be used by processor self-test.\r | |
2865 | The memory region passed must be\r | |
2866 | cacheable, bit 63 must be zero.\r | |
2867 | \r | |
2868 | @param TestInfo Input argument specifying the size of the\r | |
2869 | memory buffer passed and the phase of the\r | |
2870 | processor self-test that should be run. See\r | |
2871 | PAL_TEST_INFO.\r | |
2872 | \r | |
2873 | @param TestParam Input argument specifying the self-test\r | |
2874 | control word and the allowable memory\r | |
2875 | attributes that can be used with the memory\r | |
2876 | buffer. See PAL_TEST_CONTROL.\r | |
9c2369c1 | 2877 | \r |
c13f09d0 | 2878 | @return R9 Formatted 8-byte value denoting the state of the\r |
2879 | processor after self-test\r | |
9c2369c1 | 2880 | \r |
2881 | \r | |
2882 | \r | |
c13f09d0 | 2883 | @return Status 1 - Call completed without error, but hardware\r |
2884 | failures occurred during self-test.\r | |
9c2369c1 | 2885 | \r |
c13f09d0 | 2886 | @return Status 0 - Call completed without error\r |
2887 | \r | |
2888 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2889 | \r |
c13f09d0 | 2890 | @return Status -3 - Call completed with error.\r |
2891 | \r | |
2892 | \r | |
2893 | **/\r | |
2894 | #define PAL_TEST_PROC 258\r | |
2895 | \r | |
2896 | /**\r | |
9c2369c1 | 2897 | \r |
c13f09d0 | 2898 | @param NumberOfInterruptControllers Number of interrupt\r |
2899 | controllers currently\r | |
2900 | enabled on the system.\r | |
2901 | \r | |
2902 | @param NumberOfProcessors Number of processors currently\r | |
2903 | enabled on the system.\r | |
2904 | \r | |
2905 | **/\r | |
2906 | typedef struct {\r | |
2907 | UINT32 NumberOfInterruptControllers;\r | |
2908 | UINT32 NumberOfProcessors;\r | |
2909 | } PAL_PLATFORM_INFO;\r | |
2910 | \r | |
2911 | /**\r | |
9c2369c1 | 2912 | \r |
c13f09d0 | 2913 | PAL Procedure - PAL_COPY_INFO.\r |
9c2369c1 | 2914 | \r |
c13f09d0 | 2915 | Return information needed to relocate PAL procedures and PAL\r |
2916 | PMI code to memory. It is required by IPF. The PAL procedure\r | |
2917 | supports the Static Registers calling convention. It could be\r | |
2918 | called at physical mode.\r | |
9c2369c1 | 2919 | \r |
c13f09d0 | 2920 | @param Index Index of PAL_COPY_INFO within the list of PAL\r |
2921 | procedures.\r | |
9c2369c1 | 2922 | \r |
c13f09d0 | 2923 | @param CopyType Unsigned integer denoting type of procedures\r |
2924 | for which copy information is requested.\r | |
2925 | \r | |
2926 | @param PlatformInfo 8-byte formatted value describing the\r | |
2927 | number of processors and the number of\r | |
2928 | interrupt controllers currently enabled\r | |
2929 | on the system. See PAL_PLATFORM_INFO.\r | |
2930 | \r | |
2931 | \r | |
2932 | @param McaProcStateInfo Unsigned integer denoting the number\r | |
2933 | of bytes that SAL needs for the\r | |
2934 | min-state save area for each\r | |
2935 | processor.\r | |
2936 | \r | |
2937 | \r | |
9c2369c1 | 2938 | \r |
c13f09d0 | 2939 | @return R9 Unsigned integer denoting the number of bytes of\r |
2940 | PAL information that must be copied to main\r | |
2941 | memory.\r | |
2942 | \r | |
2943 | @return R10 Unsigned integer denoting the starting alignment\r | |
2944 | of the data to be copied.\r | |
9c2369c1 | 2945 | \r |
c13f09d0 | 2946 | @return Status 0 - Call completed without error\r |
2947 | \r | |
2948 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2949 | \r |
c13f09d0 | 2950 | @return Status -3 - Call completed with error.\r |
2951 | \r | |
2952 | \r | |
2953 | **/\r | |
2954 | #define PAL_COPY_INFO 30\r | |
2955 | \r | |
2956 | /**\r | |
9c2369c1 | 2957 | \r |
c13f09d0 | 2958 | PAL Procedure - PAL_COPY_PAL.\r |
9c2369c1 | 2959 | \r |
c13f09d0 | 2960 | Relocate PAL procedures and PAL PMI code to memory. It is\r |
2961 | required by IPF. The PAL procedure supports the Stacked\r | |
2962 | Registers calling convention. It could be called at physical\r | |
2963 | mode.\r | |
9c2369c1 | 2964 | \r |
c13f09d0 | 2965 | @param Index Index of PAL_COPY_PAL within the list of PAL\r |
2966 | procedures.\r | |
9c2369c1 | 2967 | \r |
c13f09d0 | 2968 | @param TargetAddress Physical address of a memory buffer to\r |
2969 | copy relocatable PAL procedures and PAL\r | |
2970 | PMI code.\r | |
2971 | \r | |
2972 | @param AllocSize Unsigned integer denoting the size of the\r | |
2973 | buffer passed by SAL for the copy operation.\r | |
2974 | \r | |
2975 | \r | |
2976 | @param CopyOption Unsigned integer indicating whether\r | |
2977 | relocatable PAL code and PAL PMI code\r | |
2978 | should be copied from firmware address\r | |
2979 | space to main memory.\r | |
2980 | \r | |
9c2369c1 | 2981 | \r |
c13f09d0 | 2982 | @return R9 Unsigned integer denoting the offset of PAL_PROC\r |
2983 | in the relocatable segment copied.\r | |
9c2369c1 | 2984 | \r |
c13f09d0 | 2985 | @return Status 0 - Call completed without error\r |
2986 | \r | |
2987 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 2988 | \r |
c13f09d0 | 2989 | @return Status -3 - Call completed with error.\r |
2990 | \r | |
2991 | \r | |
2992 | **/\r | |
2993 | #define PAL_COPY_PAL 256\r | |
2994 | \r | |
2995 | /**\r | |
9c2369c1 | 2996 | \r |
c13f09d0 | 2997 | PAL Procedure - PAL_ENTER_IA_32_ENV.\r |
9c2369c1 | 2998 | \r |
c13f09d0 | 2999 | Enter IA-32 System environment. It is optional. The PAL\r |
3000 | procedure supports the Static Registers calling convention.\r | |
3001 | It could be called at physical mode.\r | |
9c2369c1 | 3002 | \r |
c13f09d0 | 3003 | Note: Since this is a special call, it does not follow the PAL\r |
9c2369c1 | 3004 | static register calling convention. GR28 contains the index of\r |
3005 | PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r | |
3006 | input arguments including GR29-GR31 are setup by SAL to values\r | |
3007 | as required by the IA-32 operating system defined in Table\r | |
3008 | 11-67. The registers that are designated as preserved, scratch,\r | |
3009 | input arguments and procedure return values by the static\r | |
3010 | procedure calling convention are not followed by this call. For\r | |
3011 | instance, GR5 and GR6 need not be preserved since these are\r | |
3012 | regarded as scratch by the IA-32 operating system. Note: In an\r | |
3013 | MP system, this call must be COMPLETED on the first CPU to enter\r | |
3014 | the IA-32 System Environment (may or may not be the BSP) prior\r | |
3015 | to being called on the remaining processors in the MP system.\r | |
3016 | \r | |
c13f09d0 | 3017 | @param Index GR28 contains the index of the\r |
3018 | PAL_ENTER_IA_32_ENV call within the list of PAL\r | |
3019 | procedures.\r | |
9c2369c1 | 3020 | \r |
3021 | \r | |
c13f09d0 | 3022 | @return Status The status is returned in GR4.\r |
3023 | -1 - Un-implemented procedure 0 JMPE detected\r | |
3024 | at privilege level\r | |
9c2369c1 | 3025 | \r |
c13f09d0 | 3026 | 0 - 1 SAL allocated buffer for IA-32 System\r |
3027 | Environment operation is too small\r | |
9c2369c1 | 3028 | \r |
c13f09d0 | 3029 | 2 - IA-32 Firmware Checksum Error\r |
9c2369c1 | 3030 | \r |
c13f09d0 | 3031 | 3 - SAL allocated buffer for IA-32 System\r |
3032 | Environment operation is not properly aligned\r | |
9c2369c1 | 3033 | \r |
c13f09d0 | 3034 | 4 - Error in SAL MP Info Table\r |
9c2369c1 | 3035 | \r |
c13f09d0 | 3036 | 5 - Error in SAL Memory Descriptor Table\r |
9c2369c1 | 3037 | \r |
c13f09d0 | 3038 | 6 - Error in SAL System Table\r |
9c2369c1 | 3039 | \r |
c13f09d0 | 3040 | 7 - Inconsistent IA-32 state\r |
9c2369c1 | 3041 | \r |
c13f09d0 | 3042 | 8 - IA-32 Firmware Internal Error\r |
9c2369c1 | 3043 | \r |
c13f09d0 | 3044 | 9 - IA-32 Soft Reset (Note: remaining register\r |
3045 | state is undefined for this termination\r | |
3046 | reason)\r | |
9c2369c1 | 3047 | \r |
c13f09d0 | 3048 | 10 - Machine Check Error\r |
9c2369c1 | 3049 | \r |
3050 | 11 - Error in SAL I/O Intercept Table\r | |
3051 | \r | |
c13f09d0 | 3052 | 12 - Processor exit due to other processor in\r |
3053 | MP system terminating the IA32 system\r | |
3054 | environment. (Note: remaining register state\r | |
3055 | is undefined for this termination reason.)\r | |
9c2369c1 | 3056 | \r |
c13f09d0 | 3057 | 13 - Itanium architecture-based state\r |
3058 | corruption by either SAL PMI handler or I/O\r | |
3059 | Intercept callback function.\r | |
3060 | \r | |
3061 | \r | |
3062 | **/\r | |
3063 | #define PAL_ENTER_IA_32_ENV 33\r | |
3064 | \r | |
3065 | /**\r | |
9c2369c1 | 3066 | \r |
c13f09d0 | 3067 | PAL Procedure - PAL_PMI_ENTRYPOINT.\r |
9c2369c1 | 3068 | \r |
c13f09d0 | 3069 | Register PMI memory entrypoints with processor. It is required\r |
3070 | by IPF. The PAL procedure supports the Stacked Registers\r | |
3071 | calling convention. It could be called at physical mode.\r | |
9c2369c1 | 3072 | \r |
c13f09d0 | 3073 | @param Index Index of PAL_PMI_ENTRYPOINT within the list of\r |
3074 | PAL procedures.\r | |
9c2369c1 | 3075 | \r |
c13f09d0 | 3076 | @param SalPmiEntry 256-byte aligned physical address of SAL\r |
3077 | PMI entrypoint in memory.\r | |
3078 | \r | |
9c2369c1 | 3079 | \r |
c13f09d0 | 3080 | @return Status 0 - Call completed without error\r |
3081 | \r | |
3082 | @return Status -2 - Invalid argument\r | |
9c2369c1 | 3083 | \r |
c13f09d0 | 3084 | @return Status -3 - Call completed with error.\r |
3085 | \r | |
3086 | \r | |
3087 | **/\r | |
3088 | #define PAL_PMI_ENTRYPOINT 32\r | |
3089 | \r | |
3090 | \r | |
3091 | /**\r | |
9c2369c1 | 3092 | \r |
c13f09d0 | 3093 | The ASCII brand identification string will be copied to the\r |
3094 | address specified in the address input argument. The processor\r | |
3095 | brand identification string is defined to be a maximum of 128\r | |
3096 | characters long; 127 bytes will contain characters and the 128th\r | |
3097 | byte is defined to be NULL (0). A processor may return less than\r | |
3098 | the 127 ASCII characters as long as the string is null\r | |
3099 | terminated. The string length will be placed in the brand_info\r | |
3100 | return argument.\r | |
3101 | \r | |
3102 | **/\r | |
9c2369c1 | 3103 | #define PAL_BRAND_INFO_ID_REQUEST 0\r |
c13f09d0 | 3104 | \r |
3105 | /**\r | |
9c2369c1 | 3106 | \r |
c13f09d0 | 3107 | PAL Procedure - PAL_BRAND_INFO.\r |
9c2369c1 | 3108 | \r |
c13f09d0 | 3109 | Provides processor branding information. It is optional by\r |
3110 | IPF. The PAL procedure supports the Stacked Registers calling\r | |
3111 | convention. It could be called at physical and Virtual mode.\r | |
3112 | \r | |
3113 | \r | |
3114 | @param Index Index of PAL_BRAND_INFO within the list of PAL\r | |
3115 | procedures.\r | |
9c2369c1 | 3116 | \r |
c13f09d0 | 3117 | @param InfoRequest Unsigned 64-bit integer specifying the\r |
3118 | information that is being requested. (See\r | |
3119 | PAL_BRAND_INFO_ID_REQUEST)\r | |
3120 | \r | |
3121 | @param Address Unsigned 64-bit integer specifying the\r | |
3122 | address of the 128-byte block to which the\r | |
3123 | processor brand string shall be written.\r | |
3124 | \r | |
3125 | \r | |
3126 | @reture R9 Brand information returned. The format of this\r | |
3127 | value is dependent on the input values passed.\r | |
3128 | \r | |
9c2369c1 | 3129 | \r |
c13f09d0 | 3130 | @return Status 0 - Call completed without error\r |
3131 | \r | |
3132 | @return Status -1 - Unimplemented procedure\r | |
9c2369c1 | 3133 | \r |
c13f09d0 | 3134 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3135 | \r |
c13f09d0 | 3136 | @return Status -3 - Call completed with error.\r |
3137 | \r | |
3138 | @return Status -6 - Input argument is not implemented.\r | |
9c2369c1 | 3139 | \r |
c13f09d0 | 3140 | **/\r |
3141 | #define PAL_BRAND_INFO 274\r | |
3142 | \r | |
3143 | /**\r | |
9c2369c1 | 3144 | \r |
c13f09d0 | 3145 | PAL Procedure - PAL_GET_HW_POLICY.\r |
9c2369c1 | 3146 | \r |
c13f09d0 | 3147 | Returns the current hardware resource sharing policy of the\r |
3148 | processor. It is optional by IPF. The PAL procedure supports\r | |
3149 | the Static Registers calling convention. It could be called at\r | |
3150 | physical and Virtual mode.\r | |
3151 | \r | |
3152 | \r | |
3153 | @param Index Index of PAL_GET_HW_POLICY within the list of PAL\r | |
3154 | procedures.\r | |
9c2369c1 | 3155 | \r |
c13f09d0 | 3156 | @param ProcessorNumber Unsigned 64-bit integer that specifies\r |
3157 | for which logical processor\r | |
3158 | information is being requested. This\r | |
3159 | input argument must be zero for the\r | |
3160 | first call to this procedure and can\r | |
3161 | be a maximum value of one less than\r | |
3162 | the number of logical processors\r | |
3163 | impacted by the hardware resource\r | |
3164 | sharing policy, which is returned by\r | |
3165 | the R10 return value.\r | |
3166 | \r | |
3167 | \r | |
3168 | @reture R9 Unsigned 64-bit integer representing the current\r | |
3169 | hardware resource sharing policy.\r | |
9c2369c1 | 3170 | \r |
c13f09d0 | 3171 | @return R10 Unsigned 64-bit integer that returns the number\r |
3172 | of logical processors impacted by the policy\r | |
3173 | input argument.\r | |
9c2369c1 | 3174 | \r |
c13f09d0 | 3175 | @return R11 Unsigned 64-bit integer containing the logical\r |
3176 | address of one of the logical processors\r | |
9c2369c1 | 3177 | impacted by policy modification.\r |
3178 | \r | |
3179 | \r | |
c13f09d0 | 3180 | @return Status 0 - Call completed without error\r |
3181 | \r | |
3182 | @return Status -1 - Unimplemented procedure\r | |
9c2369c1 | 3183 | \r |
c13f09d0 | 3184 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3185 | \r |
c13f09d0 | 3186 | @return Status -3 - Call completed with error.\r |
3187 | \r | |
3188 | @return Status -9 - Call requires PAL memory buffer.\r | |
9c2369c1 | 3189 | \r |
c13f09d0 | 3190 | **/\r |
3191 | #define PAL_GET_HW_POLICY 48\r | |
3192 | \r | |
3193 | \r | |
3194 | //\r | |
3195 | // Value of PAL_SET_HW_POLICY.Policy\r | |
9c2369c1 | 3196 | //\r |
c13f09d0 | 3197 | #define PAL_SET_HW_POLICY_PERFORMANCE 0\r |
3198 | #define PAL_SET_HW_POLICY_FAIRNESS 1\r | |
3199 | #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r | |
3200 | #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r | |
3201 | \r | |
3202 | /**\r | |
9c2369c1 | 3203 | \r |
c13f09d0 | 3204 | PAL Procedure - PAL_SET_HW_POLICY.\r |
9c2369c1 | 3205 | \r |
c13f09d0 | 3206 | Sets the current hardware resource sharing policy of the\r |
3207 | processor. It is optional by IPF. The PAL procedure supports\r | |
3208 | the Static Registers calling convention. It could be called at\r | |
3209 | physical and Virtual mode.\r | |
3210 | \r | |
3211 | \r | |
3212 | @param Index Index of PAL_SET_HW_POLICY within the list of PAL\r | |
3213 | procedures.\r | |
9c2369c1 | 3214 | \r |
c13f09d0 | 3215 | @param Policy Unsigned 64-bit integer specifying the hardware\r |
3216 | resource sharing policy the caller is setting.\r | |
3217 | See Value of PAL_SET_HW_POLICY.Policy above.\r | |
3218 | \r | |
9c2369c1 | 3219 | \r |
c13f09d0 | 3220 | @return Status 1 - Call completed successfully but could not\r |
3221 | change the hardware policy since a\r | |
3222 | competing logical processor is set in\r | |
3223 | exclusive high priority.\r | |
3224 | \r | |
3225 | @return Status 0 - Call completed without error\r | |
3226 | \r | |
3227 | @return Status -1 - Unimplemented procedure\r | |
9c2369c1 | 3228 | \r |
c13f09d0 | 3229 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3230 | \r |
c13f09d0 | 3231 | @return Status -3 - Call completed with error.\r |
3232 | \r | |
3233 | @return Status -9 - Call requires PAL memory buffer.\r | |
9c2369c1 | 3234 | \r |
c13f09d0 | 3235 | **/\r |
3236 | #define PAL_SET_HW_POLICY 49\r | |
3237 | \r | |
3238 | \r | |
3239 | /**\r | |
3240 | \r | |
3241 | @param Mode Bit2:0, Indicates the mode of operation for this\r | |
ac644614 | 3242 | procedure: 0 - Query mode 1 - Error inject mode\r |
c13f09d0 | 3243 | (err_inj should also be specified) 2 - Cancel\r |
3244 | outstanding trigger. All other fields in\r | |
3245 | PAL_MC_ERROR_TYPE_INFO,\r | |
3246 | PAL_MC_ERROR_STRUCTURE_INFO and\r | |
3247 | PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r | |
3248 | values are reserved.\r | |
3249 | \r | |
3250 | @param ErrorInjection Bit5:3, indicates the mode of error\r | |
3251 | injection: 0 - Error inject only (no\r | |
3252 | error consumption) 1 - Error inject\r | |
3253 | and consume All other values are\r | |
3254 | reserved.\r | |
3255 | \r | |
3256 | \r | |
3257 | @param ErrorSeverity Bit7:6, indicates the severity desired\r | |
3258 | for error injection/query. Definitions\r | |
3259 | of the different error severity types\r | |
3260 | 0 - Corrected error 1 - Recoverable\r | |
3261 | error 2 - Fatal error 3 - Reserved\r | |
3262 | \r | |
3263 | \r | |
3264 | @param ErrorStructure Bit12:8, Indicates the structure\r | |
3265 | identification for error\r | |
3266 | injection/query: 0 - Any structure\r | |
3267 | (cannot be used during query mode).\r | |
3268 | When selected, the structure type used\r | |
3269 | for error injection is determined by\r | |
3270 | PAL. 1 - Cache 2 - TLB 3 - Register\r | |
3271 | file 4 - Bus/System interconnect 5-15\r | |
3272 | - Reserved 16-31 - Processor\r | |
3273 | specific error injection\r | |
3274 | capabilities.ErrorDataBuffer is used\r | |
3275 | to specify error types. Please refer\r | |
3276 | to the processor specific\r | |
3277 | documentation for additional details.\r | |
3278 | \r | |
3279 | @param StructureHierarchy Bit15:13, Indicates the structure\r | |
3280 | hierarchy for error\r | |
3281 | injection/query: 0 - Any level of\r | |
3282 | hierarchy (cannot be used during\r | |
3283 | query mode). When selected, the\r | |
3284 | structure hierarchy used for error\r | |
3285 | injection is determined by PAL. 1\r | |
3286 | - Error structure hierarchy\r | |
3287 | level-1 2 - Error structure\r | |
3288 | hierarchy level-2 3 - Error\r | |
3289 | structure hierarchy level-3 4 -\r | |
3290 | Error structure hierarchy level-4\r | |
3291 | All other values are reserved.\r | |
3292 | Reserved 63:16 Reserved\r | |
3293 | \r | |
3294 | **/\r | |
3295 | typedef struct {\r | |
3296 | UINT64 Mode:3;\r | |
3297 | UINT64 ErrorInjection:3;\r | |
3298 | UINT64 ErrorSeverity:2;\r | |
3299 | UINT64 ErrorStructure:5;\r | |
3300 | UINT64 StructureHierarchy:3;\r | |
3301 | UINT64 Reserved:48;\r | |
3302 | } PAL_MC_ERROR_TYPE_INFO;\r | |
3303 | \r | |
3304 | /**\r | |
9c2369c1 | 3305 | \r |
c13f09d0 | 3306 | @param StructInfoIsValid Bit0 When 1, indicates that the\r |
3307 | structure information fields\r | |
3308 | (c_t,cl_p,cl_id) are valid and\r | |
3309 | should be used for error injection.\r | |
3310 | When 0, the structure information\r | |
3311 | fields are ignored, and the values\r | |
3312 | of these fields used for error\r | |
3313 | injection are\r | |
3314 | implementation-specific.\r | |
3315 | \r | |
3316 | @param CacheType Bit2:1 Indicates which cache should be used\r | |
3317 | for error injection: 0 - Reserved 1 -\r | |
3318 | Instruction cache 2 - Data or unified cache\r | |
3319 | 3 - Reserved\r | |
3320 | \r | |
3321 | \r | |
3322 | @param PortionOfCacheLine Bit5:3 Indicates the portion of the\r | |
3323 | cache line where the error should\r | |
3324 | be injected: 0 - Reserved 1 - Tag\r | |
3325 | 2 - Data 3 - mesi All other\r | |
3326 | values are reserved.\r | |
3327 | \r | |
3328 | @param Mechanism Bit8:6 Indicates which mechanism is used to\r | |
3329 | identify the cache line to be used for error\r | |
3330 | injection: 0 - Reserved 1 - Virtual address\r | |
3331 | provided in the inj_addr field of the buffer\r | |
3332 | pointed to by err_data_buffer should be used\r | |
3333 | to identify the cache line for error\r | |
3334 | injection. 2 - Physical address provided in\r | |
3335 | the inj_addr field of the buffer pointed to\r | |
3336 | by err_data_buffershould be used to identify\r | |
3337 | the cache line for error injection. 3 - way\r | |
3338 | and index fields provided in err_data_buffer\r | |
3339 | should be used to identify the cache line\r | |
3340 | for error injection. All other values are\r | |
3341 | reserved.\r | |
3342 | \r | |
3343 | @param DataPoisonOfCacheLine Bit9 When 1, indicates that a\r | |
3344 | multiple bit, non-correctable\r | |
3345 | error should be injected in the\r | |
3346 | cache line specified by cl_id.\r | |
3347 | If this injected error is not\r | |
3348 | consumed, it may eventually\r | |
3349 | cause a data-poisoning event\r | |
3350 | resulting in a corrected error\r | |
3351 | signal, when the associated\r | |
3352 | cache line is cast out (implicit\r | |
3353 | or explicit write-back of the\r | |
3354 | cache line). The error severity\r | |
3355 | specified by err_sev in\r | |
3356 | err_type_info must be set to 0\r | |
3357 | (corrected error) when this bit\r | |
3358 | is set.\r | |
3359 | \r | |
9c2369c1 | 3360 | \r |
c13f09d0 | 3361 | @param TrigerInfoIsValid Bit32 When 1, indicates that the\r |
3362 | trigger information fields (trigger,\r | |
3363 | trigger_pl) are valid and should be\r | |
3364 | used for error injection. When 0,\r | |
3365 | the trigger information fields are\r | |
3366 | ignored and error injection is\r | |
3367 | performed immediately.\r | |
3368 | \r | |
3369 | @param Triger Bit36:33 Indicates the operation type to be\r | |
3370 | used as the error trigger condition. The\r | |
3371 | address corresponding to the trigger is\r | |
3372 | specified in the trigger_addr field of the\r | |
3373 | buffer pointed to by err_data_buffer: 0 -\r | |
3374 | Instruction memory access. The trigger match\r | |
3375 | conditions for this operation type are similar\r | |
3376 | to the IBR address breakpoint match conditions\r | |
3377 | 1 - Data memory access. The trigger match\r | |
3378 | conditions for this operation type are similar\r | |
3379 | to the DBR address breakpoint match conditions\r | |
3380 | All other values are reserved.\r | |
3381 | \r | |
3382 | @param PrivilegeOfTriger Bit39:37 Indicates the privilege\r | |
3383 | level of the context during which\r | |
3384 | the error should be injected: 0 -\r | |
3385 | privilege level 0 1 - privilege\r | |
3386 | level 1 2 - privilege level 2 3 -\r | |
3387 | privilege level 3 All other values\r | |
3388 | are reserved. If the implementation\r | |
3389 | does not support privilege level\r | |
3390 | qualifier for triggers (i.e. if\r | |
3391 | trigger_pl is 0 in the capabilities\r | |
3392 | vector), this field is ignored and\r | |
3393 | triggers can be taken at any\r | |
3394 | privilege level.\r | |
3395 | \r | |
3396 | **/\r | |
3397 | typedef struct {\r | |
3398 | UINT64 StructInfoIsValid:1;\r | |
3399 | UINT64 CacheType:2;\r | |
3400 | UINT64 PortionOfCacheLine:3;\r | |
3401 | UINT64 Mechanism:3;\r | |
3402 | UINT64 DataPoisonOfCacheLine:1;\r | |
3403 | UINT64 Reserved1:22;\r | |
3404 | UINT64 TrigerInfoIsValid:1;\r | |
3405 | UINT64 Triger:4;\r | |
3406 | UINT64 PrivilegeOfTriger:3;\r | |
3407 | UINT64 Reserved2:24;\r | |
3408 | } PAL_MC_ERROR_STRUCT_INFO;\r | |
3409 | \r | |
3410 | /**\r | |
9c2369c1 | 3411 | \r |
ac644614 | 3412 | Buffer Pointed to by err_data_buffer - TLB\r |
9c2369c1 | 3413 | \r |
c13f09d0 | 3414 | **/\r |
3415 | typedef struct {\r | |
3416 | UINT64 TrigerAddress;\r | |
3417 | UINT64 VirtualPageNumber:52;\r | |
3418 | UINT64 Reserved1:8;\r | |
3419 | UINT64 RegionId:24;\r | |
3420 | UINT64 Reserved2:40;\r | |
3421 | } PAL_MC_ERROR_DATA_BUFFER_TLB;\r | |
3422 | \r | |
3423 | /**\r | |
9c2369c1 | 3424 | \r |
c13f09d0 | 3425 | PAL Procedure - PAL_MC_ERROR_INJECT.\r |
9c2369c1 | 3426 | \r |
c13f09d0 | 3427 | Injects the requested processor error or returns information\r |
3428 | on the supported injection capabilities for this particular\r | |
3429 | processor implementation. It is optional by IPF. The PAL\r | |
3430 | procedure supports the Stacked Registers calling convention.\r | |
3431 | It could be called at physical and Virtual mode.\r | |
3432 | \r | |
3433 | \r | |
3434 | @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r | |
3435 | procedures.\r | |
9c2369c1 | 3436 | \r |
c13f09d0 | 3437 | @param ErrorTypeInfo Unsigned 64-bit integer specifying the\r |
3438 | first level error information which\r | |
3439 | identifies the error structure and\r | |
3440 | corresponding structure hierarchy, and\r | |
3441 | the error severity.\r | |
3442 | \r | |
3443 | @param ErrorStructInfo Unsigned 64-bit integer identifying\r | |
3444 | the optional structure specific\r | |
3445 | information that provides the second\r | |
3446 | level details for the requested error.\r | |
3447 | \r | |
3448 | @param ErrorDataBuffer 64-bit physical address of a buffer\r | |
3449 | providing additional parameters for\r | |
3450 | the requested error. The address of\r | |
3451 | this buffer must be 8-byte aligned.\r | |
9c2369c1 | 3452 | \r |
c13f09d0 | 3453 | @return R9 64-bit vector specifying the supported error\r |
3454 | injection capabilities for the input argument\r | |
3455 | combination of struct_hier, err_struct and\r | |
3456 | err_sev fields in ErrorTypeInfo.\r | |
9c2369c1 | 3457 | \r |
c13f09d0 | 3458 | @return R10 64-bit vector specifying the architectural\r |
3459 | resources that are used by the procedure.\r | |
9c2369c1 | 3460 | \r |
3461 | \r | |
c13f09d0 | 3462 | @return Status 0 - Call completed without error\r |
3463 | \r | |
3464 | @return Status -1 - Unimplemented procedure\r | |
9c2369c1 | 3465 | \r |
c13f09d0 | 3466 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3467 | \r |
c13f09d0 | 3468 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3469 | \r |
c13f09d0 | 3470 | @return Status -4 - Call completed with error; the requested\r |
3471 | error could not be injected due to failure in\r | |
3472 | locating the target location in the specified\r | |
3473 | structure.\r | |
9c2369c1 | 3474 | \r |
c13f09d0 | 3475 | @return Status -5 - Argument was valid, but requested error\r |
3476 | injection capability is not supported.\r | |
3477 | \r | |
3478 | @return Status -9 - Call requires PAL memory buffer.\r | |
3479 | \r | |
3480 | **/\r | |
3481 | #define PAL_MC_ERROR_INJECT 276\r | |
3482 | \r | |
3483 | \r | |
3484 | //\r | |
3485 | // Types of PAL_GET_PSTATE.Type\r | |
9c2369c1 | 3486 | //\r |
c13f09d0 | 3487 | #define PAL_GET_PSTATE_RECENT 0\r |
3488 | #define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r | |
3489 | #define PAL_GET_PSTATE_AVERAGE 2\r | |
3490 | #define PAL_GET_PSTATE_NOW 3\r | |
3491 | \r | |
3492 | /**\r | |
9c2369c1 | 3493 | \r |
c13f09d0 | 3494 | PAL Procedure - PAL_GET_PSTATE.\r |
9c2369c1 | 3495 | \r |
c13f09d0 | 3496 | Returns the performance index of the processor. It is optional\r |
3497 | by IPF. The PAL procedure supports the Stacked Registers\r | |
3498 | calling convention. It could be called at physical and Virtual\r | |
3499 | mode.\r | |
3500 | \r | |
3501 | \r | |
3502 | @param Index Index of PAL_GET_PSTATE within the list of PAL\r | |
3503 | procedures.\r | |
9c2369c1 | 3504 | \r |
c13f09d0 | 3505 | @param Type Type of performance_index value to be returned\r |
3506 | by this procedure.See PAL_GET_PSTATE.Type above.\r | |
3507 | \r | |
9c2369c1 | 3508 | \r |
c13f09d0 | 3509 | @return R9 Unsigned integer denoting the processor\r |
3510 | performance for the time duration since the last\r | |
3511 | PAL_GET_PSTATE procedure call was made. The\r | |
3512 | value returned is between 0 and 100, and is\r | |
3513 | relative to the performance index of the highest\r | |
3514 | available P-state.\r | |
9c2369c1 | 3515 | \r |
c13f09d0 | 3516 | @return Status 1 - Call completed without error, but accuracy\r |
3517 | of performance index has been impacted by a\r | |
3518 | thermal throttling event, or a\r | |
3519 | hardware-initiated event.\r | |
9c2369c1 | 3520 | \r |
c13f09d0 | 3521 | @return Status 0 - Call completed without error\r |
3522 | \r | |
3523 | @return Status -1 - Unimplemented procedure\r | |
9c2369c1 | 3524 | \r |
c13f09d0 | 3525 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3526 | \r |
c13f09d0 | 3527 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3528 | \r |
c13f09d0 | 3529 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3530 | \r |
c13f09d0 | 3531 | **/\r |
3532 | #define PAL_GET_PSTATE 262\r | |
3533 | \r | |
3534 | /**\r | |
9c2369c1 | 3535 | \r |
c13f09d0 | 3536 | Layout of PAL_PSTATE_INFO.PStateBuffer\r |
9c2369c1 | 3537 | \r |
c13f09d0 | 3538 | **/\r |
3539 | typedef struct {\r | |
3540 | UINT32 PerformanceIndex:7;\r | |
3541 | UINT32 Reserved1:5;\r | |
3542 | UINT32 TypicalPowerDissipation:20;\r | |
3543 | UINT32 TransitionLatency1;\r | |
3544 | UINT32 TransitionLatency2;\r | |
3545 | UINT32 Reserved2;\r | |
3546 | } PAL_PSTATE_INFO_BUFFER;\r | |
3547 | \r | |
3548 | \r | |
3549 | /**\r | |
9c2369c1 | 3550 | \r |
c13f09d0 | 3551 | PAL Procedure - PAL_PSTATE_INFO.\r |
9c2369c1 | 3552 | \r |
c13f09d0 | 3553 | Returns information about the P-states supported by the\r |
3554 | processor. It is optional by IPF. The PAL procedure supports\r | |
3555 | the Static Registers calling convention. It could be called\r | |
3556 | at physical and Virtual mode.\r | |
3557 | \r | |
3558 | \r | |
3559 | @param Index Index of PAL_PSTATE_INFO within the list of PAL\r | |
3560 | procedures.\r | |
9c2369c1 | 3561 | \r |
c13f09d0 | 3562 | @param PStateBuffer 64-bit pointer to a 256-byte buffer\r |
3563 | aligned on an 8-byte boundary. See\r | |
3564 | PAL_PSTATE_INFO_BUFFER above.\r | |
3565 | \r | |
9c2369c1 | 3566 | \r |
c13f09d0 | 3567 | @return R9 Unsigned integer denoting the number of P-states\r |
3568 | supported. The maximum value of this field is 16.\r | |
3569 | \r | |
3570 | @return R10 Dependency domain information\r | |
3571 | \r | |
9c2369c1 | 3572 | \r |
c13f09d0 | 3573 | @return Status 0 - Call completed without error\r |
3574 | \r | |
3575 | @return Status -1 - Unimplemented procedure\r | |
9c2369c1 | 3576 | \r |
c13f09d0 | 3577 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3578 | \r |
c13f09d0 | 3579 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3580 | \r |
c13f09d0 | 3581 | **/\r |
3582 | #define PAL_PSTATE_INFO 44\r | |
3583 | \r | |
3584 | \r | |
3585 | /**\r | |
9c2369c1 | 3586 | \r |
c13f09d0 | 3587 | PAL Procedure - PAL_SET_PSTATE.\r |
9c2369c1 | 3588 | \r |
c13f09d0 | 3589 | To request a processor transition to a given P-state. It is\r |
3590 | optional by IPF. The PAL procedure supports the Stacked\r | |
3591 | Registers calling convention. It could be called at physical\r | |
3592 | and Virtual mode.\r | |
3593 | \r | |
3594 | \r | |
3595 | @param Index Index of PAL_SET_PSTATE within the list of PAL\r | |
3596 | procedures.\r | |
9c2369c1 | 3597 | \r |
c13f09d0 | 3598 | @param PState Unsigned integer denoting the processor\r |
3599 | P-state being requested.\r | |
9c2369c1 | 3600 | \r |
c13f09d0 | 3601 | @param ForcePState Unsigned integer denoting whether the\r |
3602 | P-state change should be forced for the\r | |
3603 | logical processor.\r | |
3604 | \r | |
3605 | \r | |
3606 | \r | |
9c2369c1 | 3607 | \r |
3608 | \r | |
c13f09d0 | 3609 | @return Status 1 - Call completed without error, but\r |
3610 | transition request was not accepted\r | |
9c2369c1 | 3611 | \r |
c13f09d0 | 3612 | @return Status 0 - Call completed without error\r |
9c2369c1 | 3613 | \r |
c13f09d0 | 3614 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3615 | \r |
c13f09d0 | 3616 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3617 | \r |
c13f09d0 | 3618 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3619 | \r |
c13f09d0 | 3620 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3621 | \r |
c13f09d0 | 3622 | **/\r |
3623 | #define PAL_SET_PSTATE 263\r | |
3624 | \r | |
3625 | /**\r | |
9c2369c1 | 3626 | \r |
c13f09d0 | 3627 | PAL Procedure - PAL_SHUTDOWN.\r |
9c2369c1 | 3628 | \r |
c13f09d0 | 3629 | Put the logical processor into a low power state which can be\r |
3630 | exited only by a reset event. It is optional by IPF. The PAL\r | |
3631 | procedure supports the Static Registers calling convention. It\r | |
3632 | could be called at physical mode.\r | |
3633 | \r | |
3634 | \r | |
3635 | @param Index Index of PAL_SHUTDOWN within the list of PAL\r | |
3636 | procedures.\r | |
9c2369c1 | 3637 | \r |
c13f09d0 | 3638 | @param NotifyPlatform 8-byte aligned physical address\r |
3639 | pointer providing details on how to\r | |
3640 | optionally notify the platform that\r | |
3641 | the processor is entering a shutdown\r | |
3642 | state.\r | |
9c2369c1 | 3643 | \r |
c13f09d0 | 3644 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3645 | \r |
c13f09d0 | 3646 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3647 | \r |
c13f09d0 | 3648 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3649 | \r |
c13f09d0 | 3650 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3651 | \r |
c13f09d0 | 3652 | **/\r |
3653 | #define PAL_SHUTDOWN 45\r | |
3654 | \r | |
3655 | /**\r | |
3656 | \r | |
3657 | Layout of PAL_MEMORY_BUFFER.ControlWord\r | |
9c2369c1 | 3658 | \r |
c13f09d0 | 3659 | **/\r |
3660 | typedef struct {\r | |
3661 | UINT64 Registration:1;\r | |
3662 | UINT64 ProbeInterrupt:1;\r | |
3663 | UINT64 Reserved:62;\r | |
3664 | } PAL_MEMORY_CONTROL_WORD;\r | |
3665 | \r | |
3666 | /**\r | |
9c2369c1 | 3667 | \r |
c13f09d0 | 3668 | PAL Procedure - PAL_MEMORY_BUFFER.\r |
9c2369c1 | 3669 | \r |
c13f09d0 | 3670 | Provides cacheable memory to PAL for exclusive use during\r |
3671 | runtime. It is optional by IPF. The PAL procedure supports the\r | |
3672 | Static Registers calling convention. It could be called at\r | |
3673 | physical mode.\r | |
3674 | \r | |
3675 | \r | |
3676 | @param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r | |
3677 | procedures.\r | |
9c2369c1 | 3678 | \r |
c13f09d0 | 3679 | @param BaseAddress Physical address of the memory buffer\r |
3680 | allocated for PAL use.\r | |
9c2369c1 | 3681 | \r |
c13f09d0 | 3682 | @param AllocSize Unsigned integer denoting the size of the\r |
3683 | memory buffer.\r | |
9c2369c1 | 3684 | \r |
c13f09d0 | 3685 | @param ControlWord Formatted bit vector that provides control\r |
3686 | options for this procedure. See\r | |
3687 | PAL_MEMORY_CONTROL_WORD above.\r | |
9c2369c1 | 3688 | \r |
c13f09d0 | 3689 | @return R9 Returns the minimum size of the memory buffer\r |
3690 | required if the alloc_size input argument was\r | |
3691 | not large enough.\r | |
9c2369c1 | 3692 | \r |
c13f09d0 | 3693 | @return Status 1 - Call has not completed a buffer relocation\r |
3694 | due to a pending interrupt\r | |
9c2369c1 | 3695 | \r |
c13f09d0 | 3696 | @return Status 0 - Call completed without error\r |
9c2369c1 | 3697 | \r |
c13f09d0 | 3698 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3699 | \r |
c13f09d0 | 3700 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3701 | \r |
c13f09d0 | 3702 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3703 | \r |
c13f09d0 | 3704 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3705 | \r |
c13f09d0 | 3706 | **/\r |
3707 | #define PAL_MEMORY_BUFFER 277\r | |
3708 | \r | |
3709 | \r | |
3710 | /**\r | |
9c2369c1 | 3711 | \r |
c13f09d0 | 3712 | PAL Procedure - PAL_VP_CREATE.\r |
9c2369c1 | 3713 | \r |
c13f09d0 | 3714 | Initializes a new vpd for the operation of a new virtual\r |
3715 | processor in the virtual environment. It is optional by IPF.\r | |
3716 | The PAL procedure supports the Stacked Registers calling\r | |
3717 | convention. It could be called at Virtual mode.\r | |
3718 | \r | |
3719 | \r | |
3720 | @param Index Index of PAL_VP_CREATE within the list of PAL\r | |
3721 | procedures.\r | |
9c2369c1 | 3722 | \r |
c13f09d0 | 3723 | @param Vpd 64-bit host virtual pointer to the Virtual\r |
3724 | Processor Descriptor (VPD).\r | |
3725 | \r | |
3726 | @param HostIva 64-bit host virtual pointer to the host IVT\r | |
3727 | for the virtual processor\r | |
3728 | \r | |
3729 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
3730 | to an optional handler for\r | |
3731 | virtualization intercepts.\r | |
9c2369c1 | 3732 | \r |
c13f09d0 | 3733 | \r |
3734 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3735 | \r |
c13f09d0 | 3736 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3737 | \r |
c13f09d0 | 3738 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3739 | \r |
c13f09d0 | 3740 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3741 | \r |
c13f09d0 | 3742 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3743 | \r |
c13f09d0 | 3744 | **/\r |
3745 | #define PAL_VP_CREATE 265\r | |
3746 | \r | |
3747 | /**\r | |
9c2369c1 | 3748 | \r |
3749 | Virtual Environment Information Parameter\r | |
3750 | \r | |
c13f09d0 | 3751 | **/\r |
3752 | typedef struct {\r | |
3753 | UINT64 Reserved1:8;\r | |
3754 | UINT64 Opcode:1;\r | |
3755 | UINT64 Reserved:53;\r | |
3756 | } PAL_VP_ENV_INFO_RETURN;\r | |
3757 | \r | |
3758 | /**\r | |
9c2369c1 | 3759 | \r |
c13f09d0 | 3760 | PAL Procedure - PAL_VP_ENV_INFO.\r |
9c2369c1 | 3761 | \r |
c13f09d0 | 3762 | Returns the parameters needed to enter a virtual environment.\r |
3763 | It is optional by IPF. The PAL procedure supports the Stacked\r | |
3764 | Registers calling convention. It could be called at Virtual\r | |
3765 | mode.\r | |
3766 | \r | |
3767 | \r | |
3768 | @param Index Index of PAL_VP_ENV_INFO within the list of PAL\r | |
3769 | procedures.\r | |
9c2369c1 | 3770 | \r |
c13f09d0 | 3771 | @param Vpd 64-bit host virtual pointer to the Virtual\r |
3772 | Processor Descriptor (VPD).\r | |
3773 | \r | |
3774 | @param HostIva 64-bit host virtual pointer to the host IVT\r | |
3775 | for the virtual processor\r | |
3776 | \r | |
3777 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
3778 | to an optional handler for\r | |
3779 | virtualization intercepts.\r | |
3780 | @return R9 Unsigned integer denoting the number of bytes\r | |
3781 | required by the PAL virtual environment buffer\r | |
3782 | during PAL_VP_INIT_ENV\r | |
9c2369c1 | 3783 | \r |
c13f09d0 | 3784 | @return R10 64-bit vector of virtual environment\r |
3785 | information. See PAL_VP_ENV_INFO_RETURN.\r | |
9c2369c1 | 3786 | \r |
c13f09d0 | 3787 | \r |
3788 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3789 | \r |
c13f09d0 | 3790 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3791 | \r |
c13f09d0 | 3792 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3793 | \r |
c13f09d0 | 3794 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3795 | \r |
c13f09d0 | 3796 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3797 | \r |
c13f09d0 | 3798 | **/\r |
3799 | #define PAL_VP_ENV_INFO 266\r | |
3800 | \r | |
3801 | /**\r | |
9c2369c1 | 3802 | \r |
c13f09d0 | 3803 | PAL Procedure - PAL_VP_EXIT_ENV.\r |
9c2369c1 | 3804 | \r |
3805 | Allows a logical processor to exit a virtual environment.\r | |
c13f09d0 | 3806 | It is optional by IPF. The PAL procedure supports the Stacked\r |
3807 | Registers calling convention. It could be called at Virtual\r | |
3808 | mode.\r | |
3809 | \r | |
3810 | \r | |
3811 | @param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r | |
3812 | procedures.\r | |
9c2369c1 | 3813 | \r |
c13f09d0 | 3814 | @param Iva Optional 64-bit host virtual pointer to the IVT\r |
3815 | when this procedure is done\r | |
3816 | \r | |
3817 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3818 | \r |
c13f09d0 | 3819 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3820 | \r |
c13f09d0 | 3821 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3822 | \r |
c13f09d0 | 3823 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3824 | \r |
c13f09d0 | 3825 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3826 | \r |
c13f09d0 | 3827 | **/\r |
3828 | #define PAL_VP_EXIT_ENV 267\r | |
3829 | \r | |
3830 | \r | |
3831 | \r | |
3832 | /**\r | |
9c2369c1 | 3833 | \r |
c13f09d0 | 3834 | PAL Procedure - PAL_VP_INIT_ENV.\r |
9c2369c1 | 3835 | \r |
c13f09d0 | 3836 | Allows a logical processor to enter a virtual environment. It\r |
3837 | is optional by IPF. The PAL procedure supports the Stacked\r | |
3838 | Registers calling convention. It could be called at Virtual\r | |
3839 | mode.\r | |
3840 | \r | |
3841 | \r | |
3842 | @param Index Index of PAL_VP_INIT_ENV within the list of PAL\r | |
3843 | procedures.\r | |
9c2369c1 | 3844 | \r |
c13f09d0 | 3845 | @param ConfigOptions 64-bit vector of global configuration\r |
3846 | settings.\r | |
3847 | \r | |
3848 | @param PhysicalBase Host physical base address of a block of\r | |
3849 | contiguous physical memory for the PAL\r | |
3850 | virtual environment buffer 1) This\r | |
3851 | memory area must be allocated by the VMM\r | |
3852 | and be 4K aligned. The first logical\r | |
3853 | processor to enter the environment will\r | |
3854 | initialize the physical block for\r | |
3855 | virtualization operations.\r | |
3856 | \r | |
3857 | @param VirtualBase Host virtual base address of the\r | |
3858 | corresponding physical memory block for\r | |
3859 | the PAL virtual environment buffer : The\r | |
3860 | VMM must maintain the host virtual to host\r | |
3861 | physical data and instruction translations\r | |
3862 | in TRs for addresses within the allocated\r | |
3863 | address space. Logical processors in this\r | |
3864 | virtual environment will use this address\r | |
3865 | when transitioning to virtual mode\r | |
3866 | operations.\r | |
3867 | \r | |
ac644614 | 3868 | @return R9 Virtualization Service Address - VSA specifies\r |
c13f09d0 | 3869 | the virtual base address of the PAL\r |
3870 | virtualization services in this virtual\r | |
3871 | environment.\r | |
9c2369c1 | 3872 | \r |
c13f09d0 | 3873 | \r |
3874 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3875 | \r |
c13f09d0 | 3876 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3877 | \r |
c13f09d0 | 3878 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3879 | \r |
c13f09d0 | 3880 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3881 | \r |
c13f09d0 | 3882 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3883 | \r |
c13f09d0 | 3884 | **/\r |
3885 | #define PAL_VP_INIT_ENV 268\r | |
3886 | \r | |
3887 | \r | |
3888 | /**\r | |
9c2369c1 | 3889 | \r |
c13f09d0 | 3890 | PAL Procedure - PAL_VP_REGISTER.\r |
9c2369c1 | 3891 | \r |
c13f09d0 | 3892 | Register a different host IVT and/or a different optional\r |
3893 | virtualization intercept handler for the virtual processor\r | |
3894 | specified by vpd. It is optional by IPF. The PAL procedure\r | |
3895 | supports the Stacked Registers calling convention. It could be\r | |
3896 | called at Virtual mode.\r | |
3897 | \r | |
3898 | \r | |
3899 | @param Index Index of PAL_VP_REGISTER within the list of PAL\r | |
3900 | procedures.\r | |
9c2369c1 | 3901 | \r |
c13f09d0 | 3902 | @param Vpd 64-bit host virtual pointer to the Virtual\r |
3903 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
3904 | virtual pointer to the host IVT for the virtual\r | |
3905 | processor\r | |
3906 | \r | |
3907 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
3908 | to an optional handler for\r | |
3909 | virtualization intercepts.\r | |
3910 | \r | |
3911 | \r | |
3912 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3913 | \r |
c13f09d0 | 3914 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3915 | \r |
c13f09d0 | 3916 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3917 | \r |
c13f09d0 | 3918 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3919 | \r |
c13f09d0 | 3920 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3921 | \r |
c13f09d0 | 3922 | **/\r |
3923 | #define PAL_VP_REGISTER 269\r | |
3924 | \r | |
3925 | \r | |
3926 | /**\r | |
9c2369c1 | 3927 | \r |
c13f09d0 | 3928 | PAL Procedure - PAL_VP_RESTORE.\r |
9c2369c1 | 3929 | \r |
c13f09d0 | 3930 | Restores virtual processor state for the specified vpd on the\r |
3931 | logical processor. It is optional by IPF. The PAL procedure\r | |
3932 | supports the Stacked Registers calling convention. It could be\r | |
3933 | called at Virtual mode.\r | |
3934 | \r | |
3935 | \r | |
3936 | @param Index Index of PAL_VP_RESTORE within the list of PAL\r | |
3937 | procedures.\r | |
9c2369c1 | 3938 | \r |
c13f09d0 | 3939 | @param Vpd 64-bit host virtual pointer to the Virtual\r |
3940 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
3941 | virtual pointer to the host IVT for the virtual\r | |
3942 | processor\r | |
3943 | \r | |
3944 | @param PalVector Vector specifies PAL procedure\r | |
3945 | implementation-specific state to be\r | |
3946 | restored.\r | |
3947 | \r | |
3948 | \r | |
3949 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3950 | \r |
c13f09d0 | 3951 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3952 | \r |
c13f09d0 | 3953 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3954 | \r |
c13f09d0 | 3955 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3956 | \r |
c13f09d0 | 3957 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3958 | \r |
c13f09d0 | 3959 | **/\r |
3960 | #define PAL_VP_RESTORE 270\r | |
3961 | \r | |
3962 | /**\r | |
9c2369c1 | 3963 | \r |
c13f09d0 | 3964 | PAL Procedure - PAL_VP_SAVE.\r |
9c2369c1 | 3965 | \r |
c13f09d0 | 3966 | Saves virtual processor state for the specified vpd on the\r |
3967 | logical processor. It is optional by IPF. The PAL procedure\r | |
3968 | supports the Stacked Registers calling convention. It could be\r | |
3969 | called at Virtual mode.\r | |
3970 | \r | |
3971 | \r | |
3972 | @param Index Index of PAL_VP_SAVE within the list of PAL\r | |
3973 | procedures.\r | |
9c2369c1 | 3974 | \r |
c13f09d0 | 3975 | @param Vpd 64-bit host virtual pointer to the Virtual\r |
3976 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
3977 | virtual pointer to the host IVT for the virtual\r | |
3978 | processor\r | |
3979 | \r | |
3980 | @param PalVector Vector specifies PAL procedure\r | |
3981 | implementation-specific state to be\r | |
3982 | restored.\r | |
3983 | \r | |
3984 | \r | |
3985 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 3986 | \r |
c13f09d0 | 3987 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 3988 | \r |
c13f09d0 | 3989 | @return Status -2 - Invalid argument\r |
9c2369c1 | 3990 | \r |
c13f09d0 | 3991 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 3992 | \r |
c13f09d0 | 3993 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 3994 | \r |
c13f09d0 | 3995 | **/\r |
3996 | #define PAL_VP_SAVE 271\r | |
3997 | \r | |
3998 | \r | |
3999 | /**\r | |
9c2369c1 | 4000 | \r |
c13f09d0 | 4001 | PAL Procedure - PAL_VP_TERMINATE.\r |
9c2369c1 | 4002 | \r |
c13f09d0 | 4003 | Terminates operation for the specified virtual processor. It\r |
4004 | is optional by IPF. The PAL procedure supports the Stacked\r | |
4005 | Registers calling convention. It could be called at Virtual\r | |
4006 | mode.\r | |
4007 | \r | |
4008 | \r | |
4009 | @param Index Index of PAL_VP_TERMINATE within the list of PAL\r | |
4010 | procedures.\r | |
9c2369c1 | 4011 | \r |
c13f09d0 | 4012 | @param Vpd 64-bit host virtual pointer to the Virtual\r |
4013 | Processor Descriptor (VPD)\r | |
9c2369c1 | 4014 | \r |
c13f09d0 | 4015 | @param Iva Optional 64-bit host virtual pointer to the IVT\r |
4016 | when this procedure is done.\r | |
4017 | \r | |
4018 | @return Status 0 - Call completed without error\r | |
9c2369c1 | 4019 | \r |
c13f09d0 | 4020 | @return Status -1 - Unimplemented procedure\r |
9c2369c1 | 4021 | \r |
c13f09d0 | 4022 | @return Status -2 - Invalid argument\r |
9c2369c1 | 4023 | \r |
c13f09d0 | 4024 | @return Status -3 - Call completed with error.\r |
9c2369c1 | 4025 | \r |
c13f09d0 | 4026 | @return Status -9 - Call requires PAL memory buffer.\r |
9c2369c1 | 4027 | \r |
c13f09d0 | 4028 | **/\r |
4029 | #define PAL_VP_TERMINATE 272\r | |
fb3df220 | 4030 | \r |
9c2369c1 | 4031 | \r |
fb3df220 | 4032 | /**\r |
4033 | Makes a PAL procedure call.\r | |
4034 | \r | |
4035 | This is a wrapper function to make a PAL procedure call. Based on the Index value,\r | |
4036 | this API will make static or stacked PAL call. Architected procedures may be designated\r | |
4037 | as required or optional. If a PAL procedure is specified as optional, a unique return\r | |
4038 | code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.\r | |
4039 | This indicates that the procedure is not present in this PAL implementation. It is the\r | |
ac644614 | 4040 | caller's responsibility to check for this return code after calling any optional PAL\r |
fb3df220 | 4041 | procedure. No parameter checking is performed on the 4 input parameters, but there are\r |
4042 | some common rules that the caller should follow when making a PAL call. Any address\r | |
4043 | passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses\r | |
4044 | may cause undefined results. For those parameters defined as reserved or some fields\r | |
4045 | defined as reserved must be zero filled or the invalid argument return value may be\r | |
4046 | returned or undefined result may occur during the execution of the procedure.\r | |
4047 | This function is only available on IPF.\r | |
4048 | \r | |
4049 | @param Index - The PAL procedure Index number.\r | |
9c2369c1 | 4050 | @param Arg2 - The 2nd parameter for PAL procedure calls.\r |
fb3df220 | 4051 | @param Arg3 - The 3rd parameter for PAL procedure calls.\r |
4052 | @param Arg4 - The 4th parameter for PAL procedure calls.\r | |
4053 | \r | |
4054 | @return structure returned from the PAL Call procedure, including the status and return value.\r | |
4055 | \r | |
4056 | **/\r | |
4057 | PAL_CALL_RETURN\r | |
4058 | EFIAPI\r | |
4059 | PalCall (\r | |
4060 | IN UINT64 Index,\r | |
4061 | IN UINT64 Arg2,\r | |
4062 | IN UINT64 Arg3,\r | |
4063 | IN UINT64 Arg4\r | |
4064 | );\r | |
4065 | \r | |
4066 | #endif\r | |
4067 | \r |