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878ddf1f | 1 | /** @file\r |
24e25d11 | 2 | PCI CF8 Library Services for PCI Segment #0\r |
878ddf1f | 3 | \r |
24e25d11 | 4 | Copyright (c) 2006, Intel Corporation\r |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
878ddf1f | 9 | \r |
24e25d11 | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
878ddf1f | 12 | \r |
24e25d11 | 13 | Module Name: PciCf8Lib.h\r |
878ddf1f | 14 | \r |
15 | **/\r | |
16 | \r | |
17 | #ifndef __PCI_CF8_LIB_H__\r | |
18 | #define __PCI_CF8_LIB_H__\r | |
19 | \r | |
20 | #include <Library/PciLib.h>\r | |
21 | \r | |
22 | /**\r | |
23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
24 | address that can be passed to the PCI Library functions.\r | |
25 | \r | |
26 | Computes an address that is compatible with the PCI Library functions. The\r | |
27 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
28 | the generation of the address.\r | |
29 | \r | |
30 | @param Bus PCI Bus number. Range 0..255.\r | |
31 | @param Device PCI Device number. Range 0..31.\r | |
32 | @param Function PCI Function number. Range 0..7.\r | |
33 | @param Register PCI Register number. Range 0..255.\r | |
34 | \r | |
35 | @return The encode PCI address.\r | |
36 | \r | |
37 | **/\r | |
38 | #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
39 | PCI_LIB_ADDRESS (Bus, Device, Function, Offset)\r | |
40 | \r | |
41 | /**\r | |
42 | Reads an 8-bit PCI configuration register.\r | |
43 | \r | |
44 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
45 | This function must guarantee that all PCI read and write operations are\r | |
46 | serialized.\r | |
47 | \r | |
48 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
49 | If the register specified by Address >= 0x100, then ASSERT().\r | |
50 | \r | |
51 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
52 | Register.\r | |
53 | \r | |
54 | @return The read value from the PCI configuration register.\r | |
55 | \r | |
56 | **/\r | |
57 | UINT8\r | |
58 | EFIAPI\r | |
59 | PciCf8Read8 (\r | |
60 | IN UINTN Address\r | |
61 | );\r | |
62 | \r | |
63 | /**\r | |
64 | Writes an 8-bit PCI configuration register.\r | |
65 | \r | |
66 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
67 | value specified by Value. Value is returned. This function must guarantee\r | |
68 | that all PCI read and write operations are serialized.\r | |
69 | \r | |
70 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
71 | If the register specified by Address >= 0x100, then ASSERT().\r | |
72 | \r | |
73 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
74 | Register.\r | |
75 | @param Value The value to write.\r | |
76 | \r | |
77 | @return The value written to the PCI configuration register.\r | |
78 | \r | |
79 | **/\r | |
80 | UINT8\r | |
81 | EFIAPI\r | |
82 | PciCf8Write8 (\r | |
83 | IN UINTN Address,\r | |
84 | IN UINT8 Data\r | |
85 | );\r | |
86 | \r | |
87 | /**\r | |
88 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
89 | an 8-bit value.\r | |
90 | \r | |
91 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
92 | bitwise inclusive OR between the read result and the value specified by\r | |
93 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
94 | specified by Address. The value written to the PCI configuration register is\r | |
95 | returned. This function must guarantee that all PCI read and write operations\r | |
96 | are serialized.\r | |
97 | \r | |
98 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
99 | If the register specified by Address >= 0x100, then ASSERT().\r | |
100 | \r | |
101 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
102 | Register.\r | |
103 | @param OrData The value to OR with the PCI configuration register.\r | |
104 | \r | |
105 | @return The value written back to the PCI configuration register.\r | |
106 | \r | |
107 | **/\r | |
108 | UINT8\r | |
109 | EFIAPI\r | |
110 | PciCf8Or8 (\r | |
111 | IN UINTN Address,\r | |
112 | IN UINT8 OrData\r | |
113 | );\r | |
114 | \r | |
115 | /**\r | |
116 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
117 | value.\r | |
118 | \r | |
119 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
120 | bitwise AND between the read result and the value specified by AndData, and\r | |
121 | writes the result to the 8-bit PCI configuration register specified by\r | |
122 | Address. The value written to the PCI configuration register is returned.\r | |
123 | This function must guarantee that all PCI read and write operations are\r | |
124 | serialized.\r | |
125 | \r | |
126 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
127 | If the register specified by Address >= 0x100, then ASSERT().\r | |
128 | \r | |
129 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
130 | Register.\r | |
131 | @param AndData The value to AND with the PCI configuration register.\r | |
132 | \r | |
133 | @return The value written back to the PCI configuration register.\r | |
134 | \r | |
135 | **/\r | |
136 | UINT8\r | |
137 | EFIAPI\r | |
138 | PciCf8And8 (\r | |
139 | IN UINTN Address,\r | |
140 | IN UINT8 AndData\r | |
141 | );\r | |
142 | \r | |
143 | /**\r | |
144 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
145 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
146 | \r | |
147 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
148 | bitwise AND between the read result and the value specified by AndData,\r | |
149 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
150 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
151 | configuration register specified by Address. The value written to the PCI\r | |
152 | configuration register is returned. This function must guarantee that all PCI\r | |
153 | read and write operations are serialized.\r | |
154 | \r | |
155 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
156 | If the register specified by Address >= 0x100, then ASSERT().\r | |
157 | \r | |
158 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
159 | Register.\r | |
160 | @param AndData The value to AND with the PCI configuration register.\r | |
161 | @param OrData The value to OR with the result of the AND operation.\r | |
162 | \r | |
163 | @return The value written back to the PCI configuration register.\r | |
164 | \r | |
165 | **/\r | |
166 | UINT8\r | |
167 | EFIAPI\r | |
168 | PciCf8AndThenOr8 (\r | |
169 | IN UINTN Address,\r | |
170 | IN UINT8 AndData,\r | |
171 | IN UINT8 OrData\r | |
172 | );\r | |
173 | \r | |
174 | /**\r | |
175 | Reads a bit field of a PCI configuration register.\r | |
176 | \r | |
177 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
178 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
179 | returned.\r | |
180 | \r | |
181 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
182 | If the register specified by Address >= 0x100, then ASSERT().\r | |
183 | If StartBit is greater than 7, then ASSERT().\r | |
184 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 185 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 186 | \r |
187 | @param Address PCI configuration register to read.\r | |
188 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
189 | Range 0..7.\r | |
190 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
191 | Range 0..7.\r | |
192 | \r | |
193 | @return The value of the bit field read from the PCI configuration register.\r | |
194 | \r | |
195 | **/\r | |
196 | UINT8\r | |
197 | EFIAPI\r | |
198 | PciCf8BitFieldRead8 (\r | |
199 | IN UINTN Address,\r | |
200 | IN UINTN StartBit,\r | |
201 | IN UINTN EndBit\r | |
202 | );\r | |
203 | \r | |
204 | /**\r | |
205 | Writes a bit field to a PCI configuration register.\r | |
206 | \r | |
207 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
208 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
209 | destination PCI configuration register are preserved. The new value of the\r | |
210 | 8-bit register is returned.\r | |
211 | \r | |
212 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
213 | If the register specified by Address >= 0x100, then ASSERT().\r | |
214 | If StartBit is greater than 7, then ASSERT().\r | |
215 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 216 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 217 | \r |
218 | @param Address PCI configuration register to write.\r | |
219 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
220 | Range 0..7.\r | |
221 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
222 | Range 0..7.\r | |
223 | @param Value New value of the bit field.\r | |
224 | \r | |
225 | @return The value written back to the PCI configuration register.\r | |
226 | \r | |
227 | **/\r | |
228 | UINT8\r | |
229 | EFIAPI\r | |
230 | PciCf8BitFieldWrite8 (\r | |
231 | IN UINTN Address,\r | |
232 | IN UINTN StartBit,\r | |
233 | IN UINTN EndBit,\r | |
234 | IN UINT8 Value\r | |
235 | );\r | |
236 | \r | |
237 | /**\r | |
238 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
239 | writes the result back to the bit field in the 8-bit port.\r | |
240 | \r | |
241 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
242 | bitwise inclusive OR between the read result and the value specified by\r | |
243 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
244 | specified by Address. The value written to the PCI configuration register is\r | |
245 | returned. This function must guarantee that all PCI read and write operations\r | |
246 | are serialized. Extra left bits in OrData are stripped.\r | |
247 | \r | |
248 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
249 | If the register specified by Address >= 0x100, then ASSERT().\r | |
250 | If StartBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 252 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 253 | \r |
254 | @param Address PCI configuration register to write.\r | |
255 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
256 | Range 0..7.\r | |
257 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
258 | Range 0..7.\r | |
259 | @param OrData The value to OR with the PCI configuration register.\r | |
260 | \r | |
261 | @return The value written back to the PCI configuration register.\r | |
262 | \r | |
263 | **/\r | |
264 | UINT8\r | |
265 | EFIAPI\r | |
266 | PciCf8BitFieldOr8 (\r | |
267 | IN UINTN Address,\r | |
268 | IN UINTN StartBit,\r | |
269 | IN UINTN EndBit,\r | |
270 | IN UINT8 OrData\r | |
271 | );\r | |
272 | \r | |
273 | /**\r | |
274 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
275 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
276 | \r | |
277 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
278 | bitwise AND between the read result and the value specified by AndData, and\r | |
279 | writes the result to the 8-bit PCI configuration register specified by\r | |
280 | Address. The value written to the PCI configuration register is returned.\r | |
281 | This function must guarantee that all PCI read and write operations are\r | |
282 | serialized. Extra left bits in AndData are stripped.\r | |
283 | \r | |
284 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
285 | If the register specified by Address >= 0x100, then ASSERT().\r | |
286 | If StartBit is greater than 7, then ASSERT().\r | |
287 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 288 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 289 | \r |
290 | @param Address PCI configuration register to write.\r | |
291 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
292 | Range 0..7.\r | |
293 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
294 | Range 0..7.\r | |
295 | @param AndData The value to AND with the PCI configuration register.\r | |
296 | \r | |
297 | @return The value written back to the PCI configuration register.\r | |
298 | \r | |
299 | **/\r | |
300 | UINT8\r | |
301 | EFIAPI\r | |
302 | PciCf8BitFieldAnd8 (\r | |
303 | IN UINTN Address,\r | |
304 | IN UINTN StartBit,\r | |
305 | IN UINTN EndBit,\r | |
306 | IN UINT8 AndData\r | |
307 | );\r | |
308 | \r | |
309 | /**\r | |
310 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
311 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
312 | 8-bit port.\r | |
313 | \r | |
314 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
315 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
316 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
317 | configuration register specified by Address. The value written to the PCI\r | |
318 | configuration register is returned. This function must guarantee that all PCI\r | |
319 | read and write operations are serialized. Extra left bits in both AndData and\r | |
320 | OrData are stripped.\r | |
321 | \r | |
322 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
323 | If the register specified by Address >= 0x100, then ASSERT().\r | |
324 | If StartBit is greater than 7, then ASSERT().\r | |
325 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 326 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 327 | \r |
328 | @param Address PCI configuration register to write.\r | |
329 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
330 | Range 0..7.\r | |
331 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
332 | Range 0..7.\r | |
333 | @param AndData The value to AND with the PCI configuration register.\r | |
334 | @param OrData The value to OR with the result of the AND operation.\r | |
335 | \r | |
336 | @return The value written back to the PCI configuration register.\r | |
337 | \r | |
338 | **/\r | |
339 | UINT8\r | |
340 | EFIAPI\r | |
341 | PciCf8BitFieldAndThenOr8 (\r | |
342 | IN UINTN Address,\r | |
343 | IN UINTN StartBit,\r | |
344 | IN UINTN EndBit,\r | |
345 | IN UINT8 AndData,\r | |
346 | IN UINT8 OrData\r | |
347 | );\r | |
348 | \r | |
349 | /**\r | |
350 | Reads a 16-bit PCI configuration register.\r | |
351 | \r | |
352 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
353 | This function must guarantee that all PCI read and write operations are\r | |
354 | serialized.\r | |
355 | \r | |
356 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
357 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
358 | If the register specified by Address >= 0x100, then ASSERT().\r | |
359 | \r | |
360 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
361 | Register.\r | |
362 | \r | |
363 | @return The read value from the PCI configuration register.\r | |
364 | \r | |
365 | **/\r | |
366 | UINT16\r | |
367 | EFIAPI\r | |
368 | PciCf8Read16 (\r | |
369 | IN UINTN Address\r | |
370 | );\r | |
371 | \r | |
372 | /**\r | |
373 | Writes a 16-bit PCI configuration register.\r | |
374 | \r | |
375 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
376 | value specified by Value. Value is returned. This function must guarantee\r | |
377 | that all PCI read and write operations are serialized.\r | |
378 | \r | |
379 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
380 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
381 | If the register specified by Address >= 0x100, then ASSERT().\r | |
382 | \r | |
383 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
384 | Register.\r | |
385 | @param Value The value to write.\r | |
386 | \r | |
387 | @return The value written to the PCI configuration register.\r | |
388 | \r | |
389 | **/\r | |
390 | UINT16\r | |
391 | EFIAPI\r | |
392 | PciCf8Write16 (\r | |
393 | IN UINTN Address,\r | |
394 | IN UINT16 Data\r | |
395 | );\r | |
396 | \r | |
397 | /**\r | |
398 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
399 | a 16-bit value.\r | |
400 | \r | |
401 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
402 | bitwise inclusive OR between the read result and the value specified by\r | |
403 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
404 | specified by Address. The value written to the PCI configuration register is\r | |
405 | returned. This function must guarantee that all PCI read and write operations\r | |
406 | are serialized.\r | |
407 | \r | |
408 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
409 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
410 | If the register specified by Address >= 0x100, then ASSERT().\r | |
411 | \r | |
412 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
413 | Register.\r | |
414 | @param OrData The value to OR with the PCI configuration register.\r | |
415 | \r | |
416 | @return The value written back to the PCI configuration register.\r | |
417 | \r | |
418 | **/\r | |
419 | UINT16\r | |
420 | EFIAPI\r | |
421 | PciCf8Or16 (\r | |
422 | IN UINTN Address,\r | |
423 | IN UINT16 OrData\r | |
424 | );\r | |
425 | \r | |
426 | /**\r | |
427 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
428 | value.\r | |
429 | \r | |
430 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
431 | bitwise AND between the read result and the value specified by AndData, and\r | |
432 | writes the result to the 16-bit PCI configuration register specified by\r | |
433 | Address. The value written to the PCI configuration register is returned.\r | |
434 | This function must guarantee that all PCI read and write operations are\r | |
435 | serialized.\r | |
436 | \r | |
437 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
438 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
439 | If the register specified by Address >= 0x100, then ASSERT().\r | |
440 | \r | |
441 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
442 | Register.\r | |
443 | @param AndData The value to AND with the PCI configuration register.\r | |
444 | \r | |
445 | @return The value written back to the PCI configuration register.\r | |
446 | \r | |
447 | **/\r | |
448 | UINT16\r | |
449 | EFIAPI\r | |
450 | PciCf8And16 (\r | |
451 | IN UINTN Address,\r | |
452 | IN UINT16 AndData\r | |
453 | );\r | |
454 | \r | |
455 | /**\r | |
456 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
457 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
458 | \r | |
459 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
460 | bitwise AND between the read result and the value specified by AndData,\r | |
461 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
462 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
463 | configuration register specified by Address. The value written to the PCI\r | |
464 | configuration register is returned. This function must guarantee that all PCI\r | |
465 | read and write operations are serialized.\r | |
466 | \r | |
467 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
468 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
469 | If the register specified by Address >= 0x100, then ASSERT().\r | |
470 | \r | |
471 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
472 | Register.\r | |
473 | @param AndData The value to AND with the PCI configuration register.\r | |
474 | @param OrData The value to OR with the result of the AND operation.\r | |
475 | \r | |
476 | @return The value written back to the PCI configuration register.\r | |
477 | \r | |
478 | **/\r | |
479 | UINT16\r | |
480 | EFIAPI\r | |
481 | PciCf8AndThenOr16 (\r | |
482 | IN UINTN Address,\r | |
483 | IN UINT16 AndData,\r | |
484 | IN UINT16 OrData\r | |
485 | );\r | |
486 | \r | |
487 | /**\r | |
488 | Reads a bit field of a PCI configuration register.\r | |
489 | \r | |
490 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
491 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
492 | returned.\r | |
493 | \r | |
494 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
495 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
496 | If the register specified by Address >= 0x100, then ASSERT().\r | |
497 | If StartBit is greater than 15, then ASSERT().\r | |
498 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 499 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 500 | \r |
501 | @param Address PCI configuration register to read.\r | |
502 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
503 | Range 0..15.\r | |
504 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
505 | Range 0..15.\r | |
506 | \r | |
507 | @return The value of the bit field read from the PCI configuration register.\r | |
508 | \r | |
509 | **/\r | |
510 | UINT16\r | |
511 | EFIAPI\r | |
512 | PciCf8BitFieldRead16 (\r | |
513 | IN UINTN Address,\r | |
514 | IN UINTN StartBit,\r | |
515 | IN UINTN EndBit\r | |
516 | );\r | |
517 | \r | |
518 | /**\r | |
519 | Writes a bit field to a PCI configuration register.\r | |
520 | \r | |
521 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
522 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
523 | destination PCI configuration register are preserved. The new value of the\r | |
524 | 16-bit register is returned.\r | |
525 | \r | |
526 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
527 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
528 | If the register specified by Address >= 0x100, then ASSERT().\r | |
529 | If StartBit is greater than 15, then ASSERT().\r | |
530 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 531 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 532 | \r |
533 | @param Address PCI configuration register to write.\r | |
534 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
535 | Range 0..15.\r | |
536 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
537 | Range 0..15.\r | |
538 | @param Value New value of the bit field.\r | |
539 | \r | |
540 | @return The value written back to the PCI configuration register.\r | |
541 | \r | |
542 | **/\r | |
543 | UINT16\r | |
544 | EFIAPI\r | |
545 | PciCf8BitFieldWrite16 (\r | |
546 | IN UINTN Address,\r | |
547 | IN UINTN StartBit,\r | |
548 | IN UINTN EndBit,\r | |
549 | IN UINT16 Value\r | |
550 | );\r | |
551 | \r | |
552 | /**\r | |
553 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
554 | writes the result back to the bit field in the 16-bit port.\r | |
555 | \r | |
556 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
557 | bitwise inclusive OR between the read result and the value specified by\r | |
558 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
559 | specified by Address. The value written to the PCI configuration register is\r | |
560 | returned. This function must guarantee that all PCI read and write operations\r | |
561 | are serialized. Extra left bits in OrData are stripped.\r | |
562 | \r | |
563 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
564 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
565 | If the register specified by Address >= 0x100, then ASSERT().\r | |
566 | If StartBit is greater than 15, then ASSERT().\r | |
567 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 568 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 569 | \r |
570 | @param Address PCI configuration register to write.\r | |
571 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
572 | Range 0..15.\r | |
573 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
574 | Range 0..15.\r | |
575 | @param OrData The value to OR with the PCI configuration register.\r | |
576 | \r | |
577 | @return The value written back to the PCI configuration register.\r | |
578 | \r | |
579 | **/\r | |
580 | UINT16\r | |
581 | EFIAPI\r | |
582 | PciCf8BitFieldOr16 (\r | |
583 | IN UINTN Address,\r | |
584 | IN UINTN StartBit,\r | |
585 | IN UINTN EndBit,\r | |
586 | IN UINT16 OrData\r | |
587 | );\r | |
588 | \r | |
589 | /**\r | |
590 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
591 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
592 | \r | |
593 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
594 | bitwise AND between the read result and the value specified by AndData, and\r | |
595 | writes the result to the 16-bit PCI configuration register specified by\r | |
596 | Address. The value written to the PCI configuration register is returned.\r | |
597 | This function must guarantee that all PCI read and write operations are\r | |
598 | serialized. Extra left bits in AndData are stripped.\r | |
599 | \r | |
600 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
601 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
602 | If the register specified by Address >= 0x100, then ASSERT().\r | |
603 | If StartBit is greater than 15, then ASSERT().\r | |
604 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 605 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 606 | \r |
607 | @param Address PCI configuration register to write.\r | |
608 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
609 | Range 0..15.\r | |
610 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
611 | Range 0..15.\r | |
612 | @param AndData The value to AND with the PCI configuration register.\r | |
613 | \r | |
614 | @return The value written back to the PCI configuration register.\r | |
615 | \r | |
616 | **/\r | |
617 | UINT16\r | |
618 | EFIAPI\r | |
619 | PciCf8BitFieldAnd16 (\r | |
620 | IN UINTN Address,\r | |
621 | IN UINTN StartBit,\r | |
622 | IN UINTN EndBit,\r | |
623 | IN UINT16 AndData\r | |
624 | );\r | |
625 | \r | |
626 | /**\r | |
627 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
628 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
629 | 16-bit port.\r | |
630 | \r | |
631 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
632 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
633 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
634 | configuration register specified by Address. The value written to the PCI\r | |
635 | configuration register is returned. This function must guarantee that all PCI\r | |
636 | read and write operations are serialized. Extra left bits in both AndData and\r | |
637 | OrData are stripped.\r | |
638 | \r | |
639 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
640 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
641 | If the register specified by Address >= 0x100, then ASSERT().\r | |
642 | If StartBit is greater than 15, then ASSERT().\r | |
643 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 644 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 645 | \r |
646 | @param Address PCI configuration register to write.\r | |
647 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
648 | Range 0..15.\r | |
649 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
650 | Range 0..15.\r | |
651 | @param AndData The value to AND with the PCI configuration register.\r | |
652 | @param OrData The value to OR with the result of the AND operation.\r | |
653 | \r | |
654 | @return The value written back to the PCI configuration register.\r | |
655 | \r | |
656 | **/\r | |
657 | UINT16\r | |
658 | EFIAPI\r | |
659 | PciCf8BitFieldAndThenOr16 (\r | |
660 | IN UINTN Address,\r | |
661 | IN UINTN StartBit,\r | |
662 | IN UINTN EndBit,\r | |
663 | IN UINT16 AndData,\r | |
664 | IN UINT16 OrData\r | |
665 | );\r | |
666 | \r | |
667 | /**\r | |
668 | Reads a 32-bit PCI configuration register.\r | |
669 | \r | |
670 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
671 | This function must guarantee that all PCI read and write operations are\r | |
672 | serialized.\r | |
673 | \r | |
674 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
675 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
676 | If the register specified by Address >= 0x100, then ASSERT().\r | |
677 | \r | |
678 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
679 | Register.\r | |
680 | \r | |
681 | @return The read value from the PCI configuration register.\r | |
682 | \r | |
683 | **/\r | |
684 | UINT32\r | |
685 | EFIAPI\r | |
686 | PciCf8Read32 (\r | |
687 | IN UINTN Address\r | |
688 | );\r | |
689 | \r | |
690 | /**\r | |
691 | Writes a 32-bit PCI configuration register.\r | |
692 | \r | |
693 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
694 | value specified by Value. Value is returned. This function must guarantee\r | |
695 | that all PCI read and write operations are serialized.\r | |
696 | \r | |
697 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
698 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
699 | If the register specified by Address >= 0x100, then ASSERT().\r | |
700 | \r | |
701 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
702 | Register.\r | |
703 | @param Value The value to write.\r | |
704 | \r | |
705 | @return The value written to the PCI configuration register.\r | |
706 | \r | |
707 | **/\r | |
708 | UINT32\r | |
709 | EFIAPI\r | |
710 | PciCf8Write32 (\r | |
711 | IN UINTN Address,\r | |
712 | IN UINT32 Data\r | |
713 | );\r | |
714 | \r | |
715 | /**\r | |
716 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
717 | a 32-bit value.\r | |
718 | \r | |
719 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
720 | bitwise inclusive OR between the read result and the value specified by\r | |
721 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
722 | specified by Address. The value written to the PCI configuration register is\r | |
723 | returned. This function must guarantee that all PCI read and write operations\r | |
724 | are serialized.\r | |
725 | \r | |
726 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
727 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
728 | If the register specified by Address >= 0x100, then ASSERT().\r | |
729 | \r | |
730 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
731 | Register.\r | |
732 | @param OrData The value to OR with the PCI configuration register.\r | |
733 | \r | |
734 | @return The value written back to the PCI configuration register.\r | |
735 | \r | |
736 | **/\r | |
737 | UINT32\r | |
738 | EFIAPI\r | |
739 | PciCf8Or32 (\r | |
740 | IN UINTN Address,\r | |
741 | IN UINT32 OrData\r | |
742 | );\r | |
743 | \r | |
744 | /**\r | |
745 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
746 | value.\r | |
747 | \r | |
748 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
749 | bitwise AND between the read result and the value specified by AndData, and\r | |
750 | writes the result to the 32-bit PCI configuration register specified by\r | |
751 | Address. The value written to the PCI configuration register is returned.\r | |
752 | This function must guarantee that all PCI read and write operations are\r | |
753 | serialized.\r | |
754 | \r | |
755 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
756 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
757 | If the register specified by Address >= 0x100, then ASSERT().\r | |
758 | \r | |
759 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
760 | Register.\r | |
761 | @param AndData The value to AND with the PCI configuration register.\r | |
762 | \r | |
763 | @return The value written back to the PCI configuration register.\r | |
764 | \r | |
765 | **/\r | |
766 | UINT32\r | |
767 | EFIAPI\r | |
768 | PciCf8And32 (\r | |
769 | IN UINTN Address,\r | |
770 | IN UINT32 AndData\r | |
771 | );\r | |
772 | \r | |
773 | /**\r | |
774 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
775 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
776 | \r | |
777 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
778 | bitwise AND between the read result and the value specified by AndData,\r | |
779 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
780 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
781 | configuration register specified by Address. The value written to the PCI\r | |
782 | configuration register is returned. This function must guarantee that all PCI\r | |
783 | read and write operations are serialized.\r | |
784 | \r | |
785 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
786 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
787 | If the register specified by Address >= 0x100, then ASSERT().\r | |
788 | \r | |
789 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
790 | Register.\r | |
791 | @param AndData The value to AND with the PCI configuration register.\r | |
792 | @param OrData The value to OR with the result of the AND operation.\r | |
793 | \r | |
794 | @return The value written back to the PCI configuration register.\r | |
795 | \r | |
796 | **/\r | |
797 | UINT32\r | |
798 | EFIAPI\r | |
799 | PciCf8AndThenOr32 (\r | |
800 | IN UINTN Address,\r | |
801 | IN UINT32 AndData,\r | |
802 | IN UINT32 OrData\r | |
803 | );\r | |
804 | \r | |
805 | /**\r | |
806 | Reads a bit field of a PCI configuration register.\r | |
807 | \r | |
808 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
809 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
810 | returned.\r | |
811 | \r | |
812 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
813 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
814 | If the register specified by Address >= 0x100, then ASSERT().\r | |
815 | If StartBit is greater than 31, then ASSERT().\r | |
816 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 817 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 818 | \r |
819 | @param Address PCI configuration register to read.\r | |
820 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
821 | Range 0..31.\r | |
822 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
823 | Range 0..31.\r | |
824 | \r | |
825 | @return The value of the bit field read from the PCI configuration register.\r | |
826 | \r | |
827 | **/\r | |
828 | UINT32\r | |
829 | EFIAPI\r | |
830 | PciCf8BitFieldRead32 (\r | |
831 | IN UINTN Address,\r | |
832 | IN UINTN StartBit,\r | |
833 | IN UINTN EndBit\r | |
834 | );\r | |
835 | \r | |
836 | /**\r | |
837 | Writes a bit field to a PCI configuration register.\r | |
838 | \r | |
839 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
840 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
841 | destination PCI configuration register are preserved. The new value of the\r | |
842 | 32-bit register is returned.\r | |
843 | \r | |
844 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
845 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
846 | If the register specified by Address >= 0x100, then ASSERT().\r | |
847 | If StartBit is greater than 31, then ASSERT().\r | |
848 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 849 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 850 | \r |
851 | @param Address PCI configuration register to write.\r | |
852 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
853 | Range 0..31.\r | |
854 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
855 | Range 0..31.\r | |
856 | @param Value New value of the bit field.\r | |
857 | \r | |
858 | @return The value written back to the PCI configuration register.\r | |
859 | \r | |
860 | **/\r | |
861 | UINT32\r | |
862 | EFIAPI\r | |
863 | PciCf8BitFieldWrite32 (\r | |
864 | IN UINTN Address,\r | |
865 | IN UINTN StartBit,\r | |
866 | IN UINTN EndBit,\r | |
867 | IN UINT32 Value\r | |
868 | );\r | |
869 | \r | |
870 | /**\r | |
871 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
872 | writes the result back to the bit field in the 32-bit port.\r | |
873 | \r | |
874 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
875 | bitwise inclusive OR between the read result and the value specified by\r | |
876 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
877 | specified by Address. The value written to the PCI configuration register is\r | |
878 | returned. This function must guarantee that all PCI read and write operations\r | |
879 | are serialized. Extra left bits in OrData are stripped.\r | |
880 | \r | |
881 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
882 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
883 | If the register specified by Address >= 0x100, then ASSERT().\r | |
884 | If StartBit is greater than 31, then ASSERT().\r | |
885 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 886 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 887 | \r |
888 | @param Address PCI configuration register to write.\r | |
889 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
890 | Range 0..31.\r | |
891 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
892 | Range 0..31.\r | |
893 | @param OrData The value to OR with the PCI configuration register.\r | |
894 | \r | |
895 | @return The value written back to the PCI configuration register.\r | |
896 | \r | |
897 | **/\r | |
898 | UINT32\r | |
899 | EFIAPI\r | |
900 | PciCf8BitFieldOr32 (\r | |
901 | IN UINTN Address,\r | |
902 | IN UINTN StartBit,\r | |
903 | IN UINTN EndBit,\r | |
904 | IN UINT32 OrData\r | |
905 | );\r | |
906 | \r | |
907 | /**\r | |
908 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
909 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
910 | \r | |
911 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
912 | bitwise AND between the read result and the value specified by AndData, and\r | |
913 | writes the result to the 32-bit PCI configuration register specified by\r | |
914 | Address. The value written to the PCI configuration register is returned.\r | |
915 | This function must guarantee that all PCI read and write operations are\r | |
916 | serialized. Extra left bits in AndData are stripped.\r | |
917 | \r | |
918 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
919 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
920 | If the register specified by Address >= 0x100, then ASSERT().\r | |
921 | If StartBit is greater than 31, then ASSERT().\r | |
922 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 923 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 924 | \r |
925 | @param Address PCI configuration register to write.\r | |
926 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
927 | Range 0..31.\r | |
928 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
929 | Range 0..31.\r | |
930 | @param AndData The value to AND with the PCI configuration register.\r | |
931 | \r | |
932 | @return The value written back to the PCI configuration register.\r | |
933 | \r | |
934 | **/\r | |
935 | UINT32\r | |
936 | EFIAPI\r | |
937 | PciCf8BitFieldAnd32 (\r | |
938 | IN UINTN Address,\r | |
939 | IN UINTN StartBit,\r | |
940 | IN UINTN EndBit,\r | |
941 | IN UINT32 AndData\r | |
942 | );\r | |
943 | \r | |
944 | /**\r | |
945 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
946 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
947 | 32-bit port.\r | |
948 | \r | |
949 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
950 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
951 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
952 | configuration register specified by Address. The value written to the PCI\r | |
953 | configuration register is returned. This function must guarantee that all PCI\r | |
954 | read and write operations are serialized. Extra left bits in both AndData and\r | |
955 | OrData are stripped.\r | |
956 | \r | |
957 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
958 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
959 | If the register specified by Address >= 0x100, then ASSERT().\r | |
960 | If StartBit is greater than 31, then ASSERT().\r | |
961 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 962 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 963 | \r |
964 | @param Address PCI configuration register to write.\r | |
965 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
966 | Range 0..31.\r | |
967 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
968 | Range 0..31.\r | |
969 | @param AndData The value to AND with the PCI configuration register.\r | |
970 | @param OrData The value to OR with the result of the AND operation.\r | |
971 | \r | |
972 | @return The value written back to the PCI configuration register.\r | |
973 | \r | |
974 | **/\r | |
975 | UINT32\r | |
976 | EFIAPI\r | |
977 | PciCf8BitFieldAndThenOr32 (\r | |
978 | IN UINTN Address,\r | |
979 | IN UINTN StartBit,\r | |
980 | IN UINTN EndBit,\r | |
981 | IN UINT32 AndData,\r | |
982 | IN UINT32 OrData\r | |
983 | );\r | |
984 | \r | |
985 | /**\r | |
986 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
987 | \r | |
988 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
989 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
990 | configuration registers from a single PCI function to be read. Size is\r | |
991 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
992 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
993 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
994 | end of the range.\r | |
995 | \r | |
996 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
997 | If the register specified by StartAddress >= 0x100, then ASSERT().\r | |
998 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r | |
add13dc2 | 999 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
878ddf1f | 1000 | \r |
1001 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1002 | Function and Register.\r | |
1003 | @param Size Size in bytes of the transfer.\r | |
1004 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1005 | \r | |
1006 | @return Size\r | |
1007 | \r | |
1008 | **/\r | |
1009 | UINTN\r | |
1010 | EFIAPI\r | |
1011 | PciCf8ReadBuffer (\r | |
1012 | IN UINTN StartAddress,\r | |
1013 | IN UINTN Size,\r | |
1014 | OUT VOID *Buffer\r | |
1015 | );\r | |
1016 | \r | |
1017 | /**\r | |
1018 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1019 | configuration space.\r | |
1020 | \r | |
1021 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1022 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1023 | configuration registers from a single PCI function to be written. Size is\r | |
1024 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1025 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1026 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1027 | and the end of the range.\r | |
1028 | \r | |
1029 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1030 | If the register specified by StartAddress >= 0x100, then ASSERT().\r | |
1031 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r | |
add13dc2 | 1032 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
878ddf1f | 1033 | \r |
1034 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1035 | Function and Register.\r | |
1036 | @param Size Size in bytes of the transfer.\r | |
1037 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1038 | \r | |
1039 | @return Size\r | |
1040 | \r | |
1041 | **/\r | |
1042 | UINTN\r | |
1043 | EFIAPI\r | |
1044 | PciCf8WriteBuffer (\r | |
1045 | IN UINTN StartAddress,\r | |
1046 | IN UINTN Size,\r | |
1047 | IN VOID *Buffer\r | |
1048 | );\r | |
1049 | \r | |
1050 | #endif\r |