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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r |
fb3df220 | 3 | \r |
50a64e5b | 4 | Copyright (c) 2006 - 2008, Intel Corporation\r |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 9 | \r |
50a64e5b | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 12 | \r |
fb3df220 | 13 | **/\r |
14 | \r | |
15 | #ifndef __PCI_EXPRESS_LIB_H__\r | |
16 | #define __PCI_EXPRESS_LIB_H__\r | |
17 | \r | |
fb3df220 | 18 | /**\r |
19 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
20 | address that can be passed to the PCI Library functions.\r | |
21 | \r | |
22 | Computes an address that is compatible with the PCI Library functions. The\r | |
23 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
24 | the generation of the address.\r | |
25 | \r | |
26 | @param Bus PCI Bus number. Range 0..255.\r | |
27 | @param Device PCI Device number. Range 0..31.\r | |
28 | @param Function PCI Function number. Range 0..7.\r | |
29 | @param Register PCI Register number. Range 0..4095.\r | |
30 | \r | |
31 | @return The encode PCI address.\r | |
32 | \r | |
33 | **/\r | |
34 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
35 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
36 | \r | |
37 | /**\r | |
38 | Reads an 8-bit PCI configuration register.\r | |
39 | \r | |
40 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
41 | This function must guarantee that all PCI read and write operations are\r | |
42 | serialized.\r | |
43 | \r | |
44 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
45 | \r | |
46 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
47 | Register.\r | |
48 | \r | |
49 | @return The read value from the PCI configuration register.\r | |
50 | \r | |
51 | **/\r | |
52 | UINT8\r | |
53 | EFIAPI\r | |
54 | PciExpressRead8 (\r | |
55 | IN UINTN Address\r | |
56 | );\r | |
57 | \r | |
58 | /**\r | |
59 | Writes an 8-bit PCI configuration register.\r | |
60 | \r | |
61 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
62 | value specified by Value. Value is returned. This function must guarantee\r | |
63 | that all PCI read and write operations are serialized.\r | |
64 | \r | |
65 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
66 | \r | |
67 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
68 | Register.\r | |
69 | @param Value The value to write.\r | |
70 | \r | |
71 | @return The value written to the PCI configuration register.\r | |
72 | \r | |
73 | **/\r | |
74 | UINT8\r | |
75 | EFIAPI\r | |
76 | PciExpressWrite8 (\r | |
77 | IN UINTN Address,\r | |
94646ec0 | 78 | IN UINT8 Value\r |
fb3df220 | 79 | );\r |
80 | \r | |
81 | /**\r | |
82 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
83 | an 8-bit value.\r | |
84 | \r | |
85 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
86 | bitwise inclusive OR between the read result and the value specified by\r | |
87 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
88 | specified by Address. The value written to the PCI configuration register is\r | |
89 | returned. This function must guarantee that all PCI read and write operations\r | |
90 | are serialized.\r | |
91 | \r | |
92 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
93 | \r | |
94 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
95 | Register.\r | |
96 | @param OrData The value to OR with the PCI configuration register.\r | |
97 | \r | |
98 | @return The value written back to the PCI configuration register.\r | |
99 | \r | |
100 | **/\r | |
101 | UINT8\r | |
102 | EFIAPI\r | |
103 | PciExpressOr8 (\r | |
104 | IN UINTN Address,\r | |
105 | IN UINT8 OrData\r | |
106 | );\r | |
107 | \r | |
108 | /**\r | |
109 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
110 | value.\r | |
111 | \r | |
112 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
113 | bitwise AND between the read result and the value specified by AndData, and\r | |
114 | writes the result to the 8-bit PCI configuration register specified by\r | |
115 | Address. The value written to the PCI configuration register is returned.\r | |
116 | This function must guarantee that all PCI read and write operations are\r | |
117 | serialized.\r | |
118 | \r | |
119 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
120 | \r | |
121 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
122 | Register.\r | |
123 | @param AndData The value to AND with the PCI configuration register.\r | |
124 | \r | |
125 | @return The value written back to the PCI configuration register.\r | |
126 | \r | |
127 | **/\r | |
128 | UINT8\r | |
129 | EFIAPI\r | |
130 | PciExpressAnd8 (\r | |
131 | IN UINTN Address,\r | |
132 | IN UINT8 AndData\r | |
133 | );\r | |
134 | \r | |
135 | /**\r | |
136 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
137 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
138 | \r | |
139 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
140 | bitwise AND between the read result and the value specified by AndData,\r | |
141 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
142 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
143 | configuration register specified by Address. The value written to the PCI\r | |
144 | configuration register is returned. This function must guarantee that all PCI\r | |
145 | read and write operations are serialized.\r | |
146 | \r | |
147 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
148 | \r | |
149 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
150 | Register.\r | |
151 | @param AndData The value to AND with the PCI configuration register.\r | |
152 | @param OrData The value to OR with the result of the AND operation.\r | |
153 | \r | |
154 | @return The value written back to the PCI configuration register.\r | |
155 | \r | |
156 | **/\r | |
157 | UINT8\r | |
158 | EFIAPI\r | |
159 | PciExpressAndThenOr8 (\r | |
160 | IN UINTN Address,\r | |
161 | IN UINT8 AndData,\r | |
162 | IN UINT8 OrData\r | |
163 | );\r | |
164 | \r | |
165 | /**\r | |
166 | Reads a bit field of a PCI configuration register.\r | |
167 | \r | |
168 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
169 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
170 | returned.\r | |
171 | \r | |
172 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
173 | If StartBit is greater than 7, then ASSERT().\r | |
174 | If EndBit is greater than 7, then ASSERT().\r | |
175 | If EndBit is less than StartBit, then ASSERT().\r | |
176 | \r | |
177 | @param Address PCI configuration register to read.\r | |
178 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
179 | Range 0..7.\r | |
180 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
181 | Range 0..7.\r | |
182 | \r | |
183 | @return The value of the bit field read from the PCI configuration register.\r | |
184 | \r | |
185 | **/\r | |
186 | UINT8\r | |
187 | EFIAPI\r | |
188 | PciExpressBitFieldRead8 (\r | |
189 | IN UINTN Address,\r | |
190 | IN UINTN StartBit,\r | |
191 | IN UINTN EndBit\r | |
192 | );\r | |
193 | \r | |
194 | /**\r | |
195 | Writes a bit field to a PCI configuration register.\r | |
196 | \r | |
197 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
198 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
199 | destination PCI configuration register are preserved. The new value of the\r | |
200 | 8-bit register is returned.\r | |
201 | \r | |
202 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
203 | If StartBit is greater than 7, then ASSERT().\r | |
204 | If EndBit is greater than 7, then ASSERT().\r | |
205 | If EndBit is less than StartBit, then ASSERT().\r | |
206 | \r | |
207 | @param Address PCI configuration register to write.\r | |
208 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
209 | Range 0..7.\r | |
210 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
211 | Range 0..7.\r | |
212 | @param Value New value of the bit field.\r | |
213 | \r | |
214 | @return The value written back to the PCI configuration register.\r | |
215 | \r | |
216 | **/\r | |
217 | UINT8\r | |
218 | EFIAPI\r | |
219 | PciExpressBitFieldWrite8 (\r | |
220 | IN UINTN Address,\r | |
221 | IN UINTN StartBit,\r | |
222 | IN UINTN EndBit,\r | |
223 | IN UINT8 Value\r | |
224 | );\r | |
225 | \r | |
226 | /**\r | |
227 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
228 | writes the result back to the bit field in the 8-bit port.\r | |
229 | \r | |
230 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
231 | bitwise inclusive OR between the read result and the value specified by\r | |
232 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
233 | specified by Address. The value written to the PCI configuration register is\r | |
234 | returned. This function must guarantee that all PCI read and write operations\r | |
235 | are serialized. Extra left bits in OrData are stripped.\r | |
236 | \r | |
237 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
238 | If StartBit is greater than 7, then ASSERT().\r | |
239 | If EndBit is greater than 7, then ASSERT().\r | |
240 | If EndBit is less than StartBit, then ASSERT().\r | |
241 | \r | |
242 | @param Address PCI configuration register to write.\r | |
243 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
244 | Range 0..7.\r | |
245 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
246 | Range 0..7.\r | |
247 | @param OrData The value to OR with the PCI configuration register.\r | |
248 | \r | |
249 | @return The value written back to the PCI configuration register.\r | |
250 | \r | |
251 | **/\r | |
252 | UINT8\r | |
253 | EFIAPI\r | |
254 | PciExpressBitFieldOr8 (\r | |
255 | IN UINTN Address,\r | |
256 | IN UINTN StartBit,\r | |
257 | IN UINTN EndBit,\r | |
258 | IN UINT8 OrData\r | |
259 | );\r | |
260 | \r | |
261 | /**\r | |
262 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
263 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
264 | \r | |
265 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
266 | bitwise AND between the read result and the value specified by AndData, and\r | |
267 | writes the result to the 8-bit PCI configuration register specified by\r | |
268 | Address. The value written to the PCI configuration register is returned.\r | |
269 | This function must guarantee that all PCI read and write operations are\r | |
270 | serialized. Extra left bits in AndData are stripped.\r | |
271 | \r | |
272 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
273 | If StartBit is greater than 7, then ASSERT().\r | |
274 | If EndBit is greater than 7, then ASSERT().\r | |
275 | If EndBit is less than StartBit, then ASSERT().\r | |
276 | \r | |
277 | @param Address PCI configuration register to write.\r | |
278 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
279 | Range 0..7.\r | |
280 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
281 | Range 0..7.\r | |
282 | @param AndData The value to AND with the PCI configuration register.\r | |
283 | \r | |
284 | @return The value written back to the PCI configuration register.\r | |
285 | \r | |
286 | **/\r | |
287 | UINT8\r | |
288 | EFIAPI\r | |
289 | PciExpressBitFieldAnd8 (\r | |
290 | IN UINTN Address,\r | |
291 | IN UINTN StartBit,\r | |
292 | IN UINTN EndBit,\r | |
293 | IN UINT8 AndData\r | |
294 | );\r | |
295 | \r | |
296 | /**\r | |
297 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
298 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
299 | 8-bit port.\r | |
300 | \r | |
301 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
302 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
303 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
304 | configuration register specified by Address. The value written to the PCI\r | |
305 | configuration register is returned. This function must guarantee that all PCI\r | |
306 | read and write operations are serialized. Extra left bits in both AndData and\r | |
307 | OrData are stripped.\r | |
308 | \r | |
309 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
310 | If StartBit is greater than 7, then ASSERT().\r | |
311 | If EndBit is greater than 7, then ASSERT().\r | |
312 | If EndBit is less than StartBit, then ASSERT().\r | |
313 | \r | |
314 | @param Address PCI configuration register to write.\r | |
315 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
316 | Range 0..7.\r | |
317 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
318 | Range 0..7.\r | |
319 | @param AndData The value to AND with the PCI configuration register.\r | |
320 | @param OrData The value to OR with the result of the AND operation.\r | |
321 | \r | |
322 | @return The value written back to the PCI configuration register.\r | |
323 | \r | |
324 | **/\r | |
325 | UINT8\r | |
326 | EFIAPI\r | |
327 | PciExpressBitFieldAndThenOr8 (\r | |
328 | IN UINTN Address,\r | |
329 | IN UINTN StartBit,\r | |
330 | IN UINTN EndBit,\r | |
331 | IN UINT8 AndData,\r | |
332 | IN UINT8 OrData\r | |
333 | );\r | |
334 | \r | |
335 | /**\r | |
336 | Reads a 16-bit PCI configuration register.\r | |
337 | \r | |
338 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
339 | This function must guarantee that all PCI read and write operations are\r | |
340 | serialized.\r | |
341 | \r | |
342 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
343 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
344 | \r | |
345 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
346 | Register.\r | |
347 | \r | |
348 | @return The read value from the PCI configuration register.\r | |
349 | \r | |
350 | **/\r | |
351 | UINT16\r | |
352 | EFIAPI\r | |
353 | PciExpressRead16 (\r | |
354 | IN UINTN Address\r | |
355 | );\r | |
356 | \r | |
357 | /**\r | |
358 | Writes a 16-bit PCI configuration register.\r | |
359 | \r | |
360 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
361 | value specified by Value. Value is returned. This function must guarantee\r | |
362 | that all PCI read and write operations are serialized.\r | |
363 | \r | |
364 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
365 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
366 | \r | |
367 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
368 | Register.\r | |
369 | @param Value The value to write.\r | |
370 | \r | |
371 | @return The value written to the PCI configuration register.\r | |
372 | \r | |
373 | **/\r | |
374 | UINT16\r | |
375 | EFIAPI\r | |
376 | PciExpressWrite16 (\r | |
377 | IN UINTN Address,\r | |
94646ec0 | 378 | IN UINT16 Value\r |
fb3df220 | 379 | );\r |
380 | \r | |
381 | /**\r | |
382 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
383 | a 16-bit value.\r | |
384 | \r | |
385 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
386 | bitwise inclusive OR between the read result and the value specified by\r | |
387 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
388 | specified by Address. The value written to the PCI configuration register is\r | |
389 | returned. This function must guarantee that all PCI read and write operations\r | |
390 | are serialized.\r | |
391 | \r | |
392 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
393 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
394 | \r | |
395 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
396 | Register.\r | |
397 | @param OrData The value to OR with the PCI configuration register.\r | |
398 | \r | |
399 | @return The value written back to the PCI configuration register.\r | |
400 | \r | |
401 | **/\r | |
402 | UINT16\r | |
403 | EFIAPI\r | |
404 | PciExpressOr16 (\r | |
405 | IN UINTN Address,\r | |
406 | IN UINT16 OrData\r | |
407 | );\r | |
408 | \r | |
409 | /**\r | |
410 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
411 | value.\r | |
412 | \r | |
413 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
414 | bitwise AND between the read result and the value specified by AndData, and\r | |
415 | writes the result to the 16-bit PCI configuration register specified by\r | |
416 | Address. The value written to the PCI configuration register is returned.\r | |
417 | This function must guarantee that all PCI read and write operations are\r | |
418 | serialized.\r | |
419 | \r | |
420 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
421 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
422 | \r | |
423 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
424 | Register.\r | |
425 | @param AndData The value to AND with the PCI configuration register.\r | |
426 | \r | |
427 | @return The value written back to the PCI configuration register.\r | |
428 | \r | |
429 | **/\r | |
430 | UINT16\r | |
431 | EFIAPI\r | |
432 | PciExpressAnd16 (\r | |
433 | IN UINTN Address,\r | |
434 | IN UINT16 AndData\r | |
435 | );\r | |
436 | \r | |
437 | /**\r | |
438 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
439 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
440 | \r | |
441 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
442 | bitwise AND between the read result and the value specified by AndData,\r | |
443 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
444 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
445 | configuration register specified by Address. The value written to the PCI\r | |
446 | configuration register is returned. This function must guarantee that all PCI\r | |
447 | read and write operations are serialized.\r | |
448 | \r | |
449 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
450 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
451 | \r | |
452 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
453 | Register.\r | |
454 | @param AndData The value to AND with the PCI configuration register.\r | |
455 | @param OrData The value to OR with the result of the AND operation.\r | |
456 | \r | |
457 | @return The value written back to the PCI configuration register.\r | |
458 | \r | |
459 | **/\r | |
460 | UINT16\r | |
461 | EFIAPI\r | |
462 | PciExpressAndThenOr16 (\r | |
463 | IN UINTN Address,\r | |
464 | IN UINT16 AndData,\r | |
465 | IN UINT16 OrData\r | |
466 | );\r | |
467 | \r | |
468 | /**\r | |
469 | Reads a bit field of a PCI configuration register.\r | |
470 | \r | |
471 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
472 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
473 | returned.\r | |
474 | \r | |
475 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
476 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
477 | If StartBit is greater than 15, then ASSERT().\r | |
478 | If EndBit is greater than 15, then ASSERT().\r | |
479 | If EndBit is less than StartBit, then ASSERT().\r | |
480 | \r | |
481 | @param Address PCI configuration register to read.\r | |
482 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
483 | Range 0..15.\r | |
484 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
485 | Range 0..15.\r | |
486 | \r | |
487 | @return The value of the bit field read from the PCI configuration register.\r | |
488 | \r | |
489 | **/\r | |
490 | UINT16\r | |
491 | EFIAPI\r | |
492 | PciExpressBitFieldRead16 (\r | |
493 | IN UINTN Address,\r | |
494 | IN UINTN StartBit,\r | |
495 | IN UINTN EndBit\r | |
496 | );\r | |
497 | \r | |
498 | /**\r | |
499 | Writes a bit field to a PCI configuration register.\r | |
500 | \r | |
501 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
502 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
503 | destination PCI configuration register are preserved. The new value of the\r | |
504 | 16-bit register is returned.\r | |
505 | \r | |
506 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
507 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
508 | If StartBit is greater than 15, then ASSERT().\r | |
509 | If EndBit is greater than 15, then ASSERT().\r | |
510 | If EndBit is less than StartBit, then ASSERT().\r | |
511 | \r | |
512 | @param Address PCI configuration register to write.\r | |
513 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
514 | Range 0..15.\r | |
515 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
516 | Range 0..15.\r | |
517 | @param Value New value of the bit field.\r | |
518 | \r | |
519 | @return The value written back to the PCI configuration register.\r | |
520 | \r | |
521 | **/\r | |
522 | UINT16\r | |
523 | EFIAPI\r | |
524 | PciExpressBitFieldWrite16 (\r | |
525 | IN UINTN Address,\r | |
526 | IN UINTN StartBit,\r | |
527 | IN UINTN EndBit,\r | |
528 | IN UINT16 Value\r | |
529 | );\r | |
530 | \r | |
531 | /**\r | |
532 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
533 | writes the result back to the bit field in the 16-bit port.\r | |
534 | \r | |
535 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
536 | bitwise inclusive OR between the read result and the value specified by\r | |
537 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
538 | specified by Address. The value written to the PCI configuration register is\r | |
539 | returned. This function must guarantee that all PCI read and write operations\r | |
540 | are serialized. Extra left bits in OrData are stripped.\r | |
541 | \r | |
542 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
543 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
544 | If StartBit is greater than 15, then ASSERT().\r | |
545 | If EndBit is greater than 15, then ASSERT().\r | |
546 | If EndBit is less than StartBit, then ASSERT().\r | |
547 | \r | |
548 | @param Address PCI configuration register to write.\r | |
549 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
550 | Range 0..15.\r | |
551 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
552 | Range 0..15.\r | |
553 | @param OrData The value to OR with the PCI configuration register.\r | |
554 | \r | |
555 | @return The value written back to the PCI configuration register.\r | |
556 | \r | |
557 | **/\r | |
558 | UINT16\r | |
559 | EFIAPI\r | |
560 | PciExpressBitFieldOr16 (\r | |
561 | IN UINTN Address,\r | |
562 | IN UINTN StartBit,\r | |
563 | IN UINTN EndBit,\r | |
564 | IN UINT16 OrData\r | |
565 | );\r | |
566 | \r | |
567 | /**\r | |
568 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
569 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
570 | \r | |
571 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
572 | bitwise AND between the read result and the value specified by AndData, and\r | |
573 | writes the result to the 16-bit PCI configuration register specified by\r | |
574 | Address. The value written to the PCI configuration register is returned.\r | |
575 | This function must guarantee that all PCI read and write operations are\r | |
576 | serialized. Extra left bits in AndData are stripped.\r | |
577 | \r | |
578 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
579 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
580 | If StartBit is greater than 15, then ASSERT().\r | |
581 | If EndBit is greater than 15, then ASSERT().\r | |
582 | If EndBit is less than StartBit, then ASSERT().\r | |
583 | \r | |
584 | @param Address PCI configuration register to write.\r | |
585 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
586 | Range 0..15.\r | |
587 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
588 | Range 0..15.\r | |
589 | @param AndData The value to AND with the PCI configuration register.\r | |
590 | \r | |
591 | @return The value written back to the PCI configuration register.\r | |
592 | \r | |
593 | **/\r | |
594 | UINT16\r | |
595 | EFIAPI\r | |
596 | PciExpressBitFieldAnd16 (\r | |
597 | IN UINTN Address,\r | |
598 | IN UINTN StartBit,\r | |
599 | IN UINTN EndBit,\r | |
600 | IN UINT16 AndData\r | |
601 | );\r | |
602 | \r | |
603 | /**\r | |
604 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
605 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
606 | 16-bit port.\r | |
607 | \r | |
608 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
609 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
610 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
611 | configuration register specified by Address. The value written to the PCI\r | |
612 | configuration register is returned. This function must guarantee that all PCI\r | |
613 | read and write operations are serialized. Extra left bits in both AndData and\r | |
614 | OrData are stripped.\r | |
615 | \r | |
616 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
617 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
618 | If StartBit is greater than 15, then ASSERT().\r | |
619 | If EndBit is greater than 15, then ASSERT().\r | |
620 | If EndBit is less than StartBit, then ASSERT().\r | |
621 | \r | |
622 | @param Address PCI configuration register to write.\r | |
623 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
624 | Range 0..15.\r | |
625 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
626 | Range 0..15.\r | |
627 | @param AndData The value to AND with the PCI configuration register.\r | |
628 | @param OrData The value to OR with the result of the AND operation.\r | |
629 | \r | |
630 | @return The value written back to the PCI configuration register.\r | |
631 | \r | |
632 | **/\r | |
633 | UINT16\r | |
634 | EFIAPI\r | |
635 | PciExpressBitFieldAndThenOr16 (\r | |
636 | IN UINTN Address,\r | |
637 | IN UINTN StartBit,\r | |
638 | IN UINTN EndBit,\r | |
639 | IN UINT16 AndData,\r | |
640 | IN UINT16 OrData\r | |
641 | );\r | |
642 | \r | |
643 | /**\r | |
644 | Reads a 32-bit PCI configuration register.\r | |
645 | \r | |
646 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
647 | This function must guarantee that all PCI read and write operations are\r | |
648 | serialized.\r | |
649 | \r | |
650 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
651 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
652 | \r | |
653 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
654 | Register.\r | |
655 | \r | |
656 | @return The read value from the PCI configuration register.\r | |
657 | \r | |
658 | **/\r | |
659 | UINT32\r | |
660 | EFIAPI\r | |
661 | PciExpressRead32 (\r | |
662 | IN UINTN Address\r | |
663 | );\r | |
664 | \r | |
665 | /**\r | |
666 | Writes a 32-bit PCI configuration register.\r | |
667 | \r | |
668 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
669 | value specified by Value. Value is returned. This function must guarantee\r | |
670 | that all PCI read and write operations are serialized.\r | |
671 | \r | |
672 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
673 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
674 | \r | |
675 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
676 | Register.\r | |
677 | @param Value The value to write.\r | |
678 | \r | |
679 | @return The value written to the PCI configuration register.\r | |
680 | \r | |
681 | **/\r | |
682 | UINT32\r | |
683 | EFIAPI\r | |
684 | PciExpressWrite32 (\r | |
685 | IN UINTN Address,\r | |
94646ec0 | 686 | IN UINT32 Value\r |
fb3df220 | 687 | );\r |
688 | \r | |
689 | /**\r | |
690 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
691 | a 32-bit value.\r | |
692 | \r | |
693 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
694 | bitwise inclusive OR between the read result and the value specified by\r | |
695 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
696 | specified by Address. The value written to the PCI configuration register is\r | |
697 | returned. This function must guarantee that all PCI read and write operations\r | |
698 | are serialized.\r | |
699 | \r | |
700 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
701 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
702 | \r | |
703 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
704 | Register.\r | |
705 | @param OrData The value to OR with the PCI configuration register.\r | |
706 | \r | |
707 | @return The value written back to the PCI configuration register.\r | |
708 | \r | |
709 | **/\r | |
710 | UINT32\r | |
711 | EFIAPI\r | |
712 | PciExpressOr32 (\r | |
713 | IN UINTN Address,\r | |
714 | IN UINT32 OrData\r | |
715 | );\r | |
716 | \r | |
717 | /**\r | |
718 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
719 | value.\r | |
720 | \r | |
721 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
722 | bitwise AND between the read result and the value specified by AndData, and\r | |
723 | writes the result to the 32-bit PCI configuration register specified by\r | |
724 | Address. The value written to the PCI configuration register is returned.\r | |
725 | This function must guarantee that all PCI read and write operations are\r | |
726 | serialized.\r | |
727 | \r | |
728 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
729 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
730 | \r | |
731 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
732 | Register.\r | |
733 | @param AndData The value to AND with the PCI configuration register.\r | |
734 | \r | |
735 | @return The value written back to the PCI configuration register.\r | |
736 | \r | |
737 | **/\r | |
738 | UINT32\r | |
739 | EFIAPI\r | |
740 | PciExpressAnd32 (\r | |
741 | IN UINTN Address,\r | |
742 | IN UINT32 AndData\r | |
743 | );\r | |
744 | \r | |
745 | /**\r | |
746 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
747 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
748 | \r | |
749 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
750 | bitwise AND between the read result and the value specified by AndData,\r | |
751 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
752 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
753 | configuration register specified by Address. The value written to the PCI\r | |
754 | configuration register is returned. This function must guarantee that all PCI\r | |
755 | read and write operations are serialized.\r | |
756 | \r | |
757 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
758 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
759 | \r | |
760 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
761 | Register.\r | |
762 | @param AndData The value to AND with the PCI configuration register.\r | |
763 | @param OrData The value to OR with the result of the AND operation.\r | |
764 | \r | |
765 | @return The value written back to the PCI configuration register.\r | |
766 | \r | |
767 | **/\r | |
768 | UINT32\r | |
769 | EFIAPI\r | |
770 | PciExpressAndThenOr32 (\r | |
771 | IN UINTN Address,\r | |
772 | IN UINT32 AndData,\r | |
773 | IN UINT32 OrData\r | |
774 | );\r | |
775 | \r | |
776 | /**\r | |
777 | Reads a bit field of a PCI configuration register.\r | |
778 | \r | |
779 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
780 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
781 | returned.\r | |
782 | \r | |
783 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
784 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
785 | If StartBit is greater than 31, then ASSERT().\r | |
786 | If EndBit is greater than 31, then ASSERT().\r | |
787 | If EndBit is less than StartBit, then ASSERT().\r | |
788 | \r | |
789 | @param Address PCI configuration register to read.\r | |
790 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
791 | Range 0..31.\r | |
792 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
793 | Range 0..31.\r | |
794 | \r | |
795 | @return The value of the bit field read from the PCI configuration register.\r | |
796 | \r | |
797 | **/\r | |
798 | UINT32\r | |
799 | EFIAPI\r | |
800 | PciExpressBitFieldRead32 (\r | |
801 | IN UINTN Address,\r | |
802 | IN UINTN StartBit,\r | |
803 | IN UINTN EndBit\r | |
804 | );\r | |
805 | \r | |
806 | /**\r | |
807 | Writes a bit field to a PCI configuration register.\r | |
808 | \r | |
809 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
810 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
811 | destination PCI configuration register are preserved. The new value of the\r | |
812 | 32-bit register is returned.\r | |
813 | \r | |
814 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
815 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
816 | If StartBit is greater than 31, then ASSERT().\r | |
817 | If EndBit is greater than 31, then ASSERT().\r | |
818 | If EndBit is less than StartBit, then ASSERT().\r | |
819 | \r | |
820 | @param Address PCI configuration register to write.\r | |
821 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
822 | Range 0..31.\r | |
823 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
824 | Range 0..31.\r | |
825 | @param Value New value of the bit field.\r | |
826 | \r | |
827 | @return The value written back to the PCI configuration register.\r | |
828 | \r | |
829 | **/\r | |
830 | UINT32\r | |
831 | EFIAPI\r | |
832 | PciExpressBitFieldWrite32 (\r | |
833 | IN UINTN Address,\r | |
834 | IN UINTN StartBit,\r | |
835 | IN UINTN EndBit,\r | |
836 | IN UINT32 Value\r | |
837 | );\r | |
838 | \r | |
839 | /**\r | |
840 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
841 | writes the result back to the bit field in the 32-bit port.\r | |
842 | \r | |
843 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
844 | bitwise inclusive OR between the read result and the value specified by\r | |
845 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
846 | specified by Address. The value written to the PCI configuration register is\r | |
847 | returned. This function must guarantee that all PCI read and write operations\r | |
848 | are serialized. Extra left bits in OrData are stripped.\r | |
849 | \r | |
850 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
851 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
852 | If StartBit is greater than 31, then ASSERT().\r | |
853 | If EndBit is greater than 31, then ASSERT().\r | |
854 | If EndBit is less than StartBit, then ASSERT().\r | |
855 | \r | |
856 | @param Address PCI configuration register to write.\r | |
857 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
858 | Range 0..31.\r | |
859 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
860 | Range 0..31.\r | |
861 | @param OrData The value to OR with the PCI configuration register.\r | |
862 | \r | |
863 | @return The value written back to the PCI configuration register.\r | |
864 | \r | |
865 | **/\r | |
866 | UINT32\r | |
867 | EFIAPI\r | |
868 | PciExpressBitFieldOr32 (\r | |
869 | IN UINTN Address,\r | |
870 | IN UINTN StartBit,\r | |
871 | IN UINTN EndBit,\r | |
872 | IN UINT32 OrData\r | |
873 | );\r | |
874 | \r | |
875 | /**\r | |
876 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
877 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
878 | \r | |
879 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
880 | bitwise AND between the read result and the value specified by AndData, and\r | |
881 | writes the result to the 32-bit PCI configuration register specified by\r | |
882 | Address. The value written to the PCI configuration register is returned.\r | |
883 | This function must guarantee that all PCI read and write operations are\r | |
884 | serialized. Extra left bits in AndData are stripped.\r | |
885 | \r | |
886 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
887 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
888 | If StartBit is greater than 31, then ASSERT().\r | |
889 | If EndBit is greater than 31, then ASSERT().\r | |
890 | If EndBit is less than StartBit, then ASSERT().\r | |
891 | \r | |
892 | @param Address PCI configuration register to write.\r | |
893 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
894 | Range 0..31.\r | |
895 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
896 | Range 0..31.\r | |
897 | @param AndData The value to AND with the PCI configuration register.\r | |
898 | \r | |
899 | @return The value written back to the PCI configuration register.\r | |
900 | \r | |
901 | **/\r | |
902 | UINT32\r | |
903 | EFIAPI\r | |
904 | PciExpressBitFieldAnd32 (\r | |
905 | IN UINTN Address,\r | |
906 | IN UINTN StartBit,\r | |
907 | IN UINTN EndBit,\r | |
908 | IN UINT32 AndData\r | |
909 | );\r | |
910 | \r | |
911 | /**\r | |
912 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
913 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
914 | 32-bit port.\r | |
915 | \r | |
916 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
917 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
918 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
919 | configuration register specified by Address. The value written to the PCI\r | |
920 | configuration register is returned. This function must guarantee that all PCI\r | |
921 | read and write operations are serialized. Extra left bits in both AndData and\r | |
922 | OrData are stripped.\r | |
923 | \r | |
924 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
925 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
926 | If StartBit is greater than 31, then ASSERT().\r | |
927 | If EndBit is greater than 31, then ASSERT().\r | |
928 | If EndBit is less than StartBit, then ASSERT().\r | |
929 | \r | |
930 | @param Address PCI configuration register to write.\r | |
931 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
932 | Range 0..31.\r | |
933 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
934 | Range 0..31.\r | |
935 | @param AndData The value to AND with the PCI configuration register.\r | |
936 | @param OrData The value to OR with the result of the AND operation.\r | |
937 | \r | |
938 | @return The value written back to the PCI configuration register.\r | |
939 | \r | |
940 | **/\r | |
941 | UINT32\r | |
942 | EFIAPI\r | |
943 | PciExpressBitFieldAndThenOr32 (\r | |
944 | IN UINTN Address,\r | |
945 | IN UINTN StartBit,\r | |
946 | IN UINTN EndBit,\r | |
947 | IN UINT32 AndData,\r | |
948 | IN UINT32 OrData\r | |
949 | );\r | |
950 | \r | |
951 | /**\r | |
952 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
953 | \r | |
954 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
955 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
956 | configuration registers from a single PCI function to be read. Size is\r | |
957 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
958 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
959 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
960 | end of the range.\r | |
961 | \r | |
962 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
963 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
964 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
965 | \r | |
966 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
967 | Function and Register.\r | |
968 | @param Size Size in bytes of the transfer.\r | |
969 | @param Buffer Pointer to a buffer receiving the data read.\r | |
970 | \r | |
9199040c | 971 | @return Size read daata from StartAddress.\r |
fb3df220 | 972 | \r |
973 | **/\r | |
974 | UINTN\r | |
975 | EFIAPI\r | |
976 | PciExpressReadBuffer (\r | |
977 | IN UINTN StartAddress,\r | |
978 | IN UINTN Size,\r | |
979 | OUT VOID *Buffer\r | |
980 | );\r | |
981 | \r | |
982 | /**\r | |
983 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
984 | configuration space.\r | |
985 | \r | |
986 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
987 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
988 | configuration registers from a single PCI function to be written. Size is\r | |
989 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
990 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
991 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
992 | and the end of the range.\r | |
993 | \r | |
994 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
995 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
996 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
997 | \r | |
998 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
999 | Function and Register.\r | |
1000 | @param Size Size in bytes of the transfer.\r | |
1001 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1002 | \r | |
9199040c | 1003 | @return Size written to StartAddress.\r |
fb3df220 | 1004 | \r |
1005 | **/\r | |
1006 | UINTN\r | |
1007 | EFIAPI\r | |
1008 | PciExpressWriteBuffer (\r | |
1009 | IN UINTN StartAddress,\r | |
1010 | IN UINTN Size,\r | |
1011 | IN VOID *Buffer\r | |
1012 | );\r | |
1013 | \r | |
1014 | #endif\r |