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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r |
fb3df220 | 3 | \r |
50a64e5b | 4 | Copyright (c) 2006 - 2008, Intel Corporation\r |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 9 | \r |
50a64e5b | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 12 | \r |
fb3df220 | 13 | **/\r |
14 | \r | |
15 | #ifndef __PCI_SEGMENT_LIB__\r | |
16 | #define __PCI_SEGMENT_LIB__\r | |
17 | \r | |
18 | \r | |
19 | /**\r | |
20 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
21 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r | |
22 | \r | |
23 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
24 | The unused upper bits of Segment, Bus, Device, Function,\r | |
25 | and Register are stripped prior to the generation of the address.\r | |
26 | \r | |
27 | @param Segment PCI Segment number. Range 0..65535.\r | |
28 | @param Bus PCI Bus number. Range 0..255.\r | |
29 | @param Device PCI Device number. Range 0..31.\r | |
30 | @param Function PCI Function number. Range 0..7.\r | |
31 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
32 | \r | |
33 | @return The address that is compatible with the PCI Segment Library functions.\r | |
34 | \r | |
35 | **/\r | |
36 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r | |
37 | ( ((Register) & 0xfff) | \\r | |
38 | (((Function) & 0x07) << 12) | \\r | |
39 | (((Device) & 0x1f) << 15) | \\r | |
40 | (((Bus) & 0xff) << 20) | \\r | |
41 | (LShiftU64((Segment) & 0xffff, 32)) \\r | |
42 | )\r | |
43 | \r | |
44 | /**\r | |
45 | Reads an 8-bit PCI configuration register.\r | |
46 | \r | |
47 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
48 | This function must guarantee that all PCI read and write operations are serialized.\r | |
49 | If any reserved bits in Address are set, then ASSERT().\r | |
50 | \r | |
51 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
52 | \r | |
53 | @return The 8-bit PCI configuration register specified by Address.\r | |
54 | \r | |
55 | **/\r | |
56 | UINT8\r | |
57 | EFIAPI\r | |
58 | PciSegmentRead8 (\r | |
59 | IN UINT64 Address\r | |
ed66e1bc | 60 | );\r |
fb3df220 | 61 | \r |
62 | /**\r | |
63 | Writes an 8-bit PCI configuration register.\r | |
64 | \r | |
65 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
66 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
67 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
68 | \r | |
69 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
70 | @param Value The value to write.\r | |
71 | \r | |
72 | @return The parameter of Value.\r | |
73 | \r | |
74 | **/\r | |
75 | UINT8\r | |
76 | EFIAPI\r | |
77 | PciSegmentWrite8 (\r | |
78 | IN UINT64 Address,\r | |
79 | IN UINT8 Value\r | |
ed66e1bc | 80 | );\r |
fb3df220 | 81 | \r |
82 | /**\r | |
83 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.\r | |
84 | \r | |
85 | Reads the 8-bit PCI configuration register specified by Address,\r | |
86 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
87 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
88 | The value written to the PCI configuration register is returned.\r | |
89 | This function must guarantee that all PCI read and write operations are serialized.\r | |
90 | If any reserved bits in Address are set, then ASSERT().\r | |
91 | \r | |
92 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
93 | @param OrData The value to OR with the PCI configuration register.\r | |
94 | \r | |
95 | @return The value written to the PCI configuration register.\r | |
96 | \r | |
97 | **/\r | |
98 | UINT8\r | |
99 | EFIAPI\r | |
100 | PciSegmentOr8 (\r | |
101 | IN UINT64 Address,\r | |
102 | IN UINT8 OrData\r | |
ed66e1bc | 103 | );\r |
fb3df220 | 104 | \r |
105 | /**\r | |
106 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r | |
107 | \r | |
108 | Reads the 8-bit PCI configuration register specified by Address,\r | |
109 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
110 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
111 | The value written to the PCI configuration register is returned.\r | |
112 | This function must guarantee that all PCI read and write operations are serialized.\r | |
113 | If any reserved bits in Address are set, then ASSERT().\r | |
114 | \r | |
115 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 116 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 117 | \r |
118 | @return The value written to the PCI configuration register.\r | |
119 | \r | |
120 | **/\r | |
121 | UINT8\r | |
122 | EFIAPI\r | |
123 | PciSegmentAnd8 (\r | |
124 | IN UINT64 Address,\r | |
125 | IN UINT8 AndData\r | |
ed66e1bc | 126 | );\r |
fb3df220 | 127 | \r |
128 | /**\r | |
129 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
130 | followed a bitwise inclusive OR with another 8-bit value.\r | |
131 | \r | |
132 | Reads the 8-bit PCI configuration register specified by Address,\r | |
133 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
134 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r | |
135 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
136 | The value written to the PCI configuration register is returned.\r | |
137 | This function must guarantee that all PCI read and write operations are serialized.\r | |
138 | If any reserved bits in Address are set, then ASSERT().\r | |
139 | \r | |
140 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
42eedea9 | 141 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 142 | @param OrData The value to OR with the PCI configuration register.\r |
143 | \r | |
144 | @return The value written to the PCI configuration register.\r | |
145 | \r | |
146 | **/\r | |
147 | UINT8\r | |
148 | EFIAPI\r | |
149 | PciSegmentAndThenOr8 (\r | |
150 | IN UINT64 Address,\r | |
151 | IN UINT8 AndData,\r | |
152 | IN UINT8 OrData\r | |
ed66e1bc | 153 | );\r |
fb3df220 | 154 | \r |
155 | /**\r | |
156 | Reads a bit field of a PCI configuration register.\r | |
157 | \r | |
158 | Reads the bit field in an 8-bit PCI configuration register.\r | |
159 | The bit field is specified by the StartBit and the EndBit.\r | |
160 | The value of the bit field is returned.\r | |
161 | If any reserved bits in Address are set, then ASSERT().\r | |
162 | If StartBit is greater than 7, then ASSERT().\r | |
163 | If EndBit is greater than 7, then ASSERT().\r | |
164 | If EndBit is less than StartBit, then ASSERT().\r | |
165 | \r | |
166 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
167 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
168 | The ordinal of the least significant bit in a byte is bit 0.\r | |
169 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
170 | The ordinal of the most significant bit in a byte is bit 7.\r | |
171 | \r | |
172 | @return The value of the bit field.\r | |
173 | \r | |
174 | **/\r | |
175 | UINT8\r | |
176 | EFIAPI\r | |
177 | PciSegmentBitFieldRead8 (\r | |
178 | IN UINT64 Address,\r | |
179 | IN UINTN StartBit,\r | |
180 | IN UINTN EndBit\r | |
ed66e1bc | 181 | );\r |
fb3df220 | 182 | \r |
183 | /**\r | |
184 | Writes a bit field to a PCI configuration register.\r | |
185 | \r | |
186 | Writes Value to the bit field of the PCI configuration register.\r | |
187 | The bit field is specified by the StartBit and the EndBit.\r | |
188 | All other bits in the destination PCI configuration register are preserved.\r | |
189 | The new value of the 8-bit register is returned.\r | |
190 | If any reserved bits in Address are set, then ASSERT().\r | |
191 | If StartBit is greater than 7, then ASSERT().\r | |
192 | If EndBit is greater than 7, then ASSERT().\r | |
193 | If EndBit is less than StartBit, then ASSERT().\r | |
194 | \r | |
195 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
196 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
197 | The ordinal of the least significant bit in a byte is bit 0.\r | |
198 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
199 | The ordinal of the most significant bit in a byte is bit 7.\r | |
200 | @param Value New value of the bit field.\r | |
201 | \r | |
202 | @return The new value of the 8-bit register.\r | |
203 | \r | |
204 | **/\r | |
205 | UINT8\r | |
206 | EFIAPI\r | |
207 | PciSegmentBitFieldWrite8 (\r | |
208 | IN UINT64 Address,\r | |
209 | IN UINTN StartBit,\r | |
210 | IN UINTN EndBit,\r | |
211 | IN UINT8 Value\r | |
ed66e1bc | 212 | );\r |
fb3df220 | 213 | \r |
214 | /**\r | |
215 | Reads the 8-bit PCI configuration register specified by Address,\r | |
216 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
217 | and writes the result to the 8-bit PCI configuration register specified by Address. \r | |
218 | \r | |
219 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
220 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
221 | The ordinal of the least significant bit in a byte is bit 0.\r | |
222 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
223 | The ordinal of the most significant bit in a byte is bit 7.\r | |
224 | @param OrData The value to OR with the read value from the PCI configuration register.\r | |
225 | \r | |
226 | @return The value written to the PCI configuration register.\r | |
227 | \r | |
228 | **/\r | |
229 | UINT8\r | |
230 | EFIAPI\r | |
231 | PciSegmentBitFieldOr8 (\r | |
232 | IN UINT64 Address,\r | |
233 | IN UINTN StartBit,\r | |
234 | IN UINTN EndBit,\r | |
235 | IN UINT8 OrData\r | |
ed66e1bc | 236 | );\r |
fb3df220 | 237 | \r |
238 | /**\r | |
239 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,\r | |
240 | and writes the result back to the bit field in the 8-bit port.\r | |
241 | \r | |
242 | Reads the 8-bit PCI configuration register specified by Address,\r | |
243 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
244 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
245 | The value written to the PCI configuration register is returned.\r | |
246 | This function must guarantee that all PCI read and write operations are serialized.\r | |
247 | Extra left bits in OrData are stripped.\r | |
248 | If any reserved bits in Address are set, then ASSERT().\r | |
249 | If StartBit is greater than 7, then ASSERT().\r | |
250 | If EndBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is less than StartBit, then ASSERT().\r | |
252 | \r | |
253 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
254 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
255 | The ordinal of the least significant bit in a byte is bit 0.\r | |
256 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
257 | The ordinal of the most significant bit in a byte is bit 7.\r | |
258 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
259 | \r | |
260 | @return The value written to the PCI configuration register.\r | |
261 | \r | |
262 | **/\r | |
263 | UINT8\r | |
264 | EFIAPI\r | |
265 | PciSegmentBitFieldAnd8 (\r | |
266 | IN UINT64 Address,\r | |
267 | IN UINTN StartBit,\r | |
268 | IN UINTN EndBit,\r | |
269 | IN UINT8 AndData\r | |
ed66e1bc | 270 | );\r |
fb3df220 | 271 | \r |
272 | /**\r | |
273 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,\r | |
274 | and writes the result back to the bit field in the 8-bit register.\r | |
275 | \r | |
276 | Reads the 8-bit PCI configuration register specified by Address,\r | |
277 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
278 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
279 | The value written to the PCI configuration register is returned.\r | |
280 | This function must guarantee that all PCI read and write operations are serialized.\r | |
281 | Extra left bits in AndData are stripped.\r | |
282 | If any reserved bits in Address are set, then ASSERT().\r | |
283 | If StartBit is greater than 7, then ASSERT().\r | |
284 | If EndBit is greater than 7, then ASSERT().\r | |
285 | If EndBit is less than StartBit, then ASSERT().\r | |
286 | \r | |
287 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
288 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
289 | The ordinal of the least significant bit in a byte is bit 0.\r | |
290 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
291 | The ordinal of the most significant bit in a byte is bit 7.\r | |
292 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
293 | @param OrData The value to OR with the read value from the PCI configuration register.\r | |
294 | \r | |
295 | @return The value written to the PCI configuration register.\r | |
296 | \r | |
297 | **/\r | |
298 | UINT8\r | |
299 | EFIAPI\r | |
300 | PciSegmentBitFieldAndThenOr8 (\r | |
301 | IN UINT64 Address,\r | |
302 | IN UINTN StartBit,\r | |
303 | IN UINTN EndBit,\r | |
304 | IN UINT8 AndData,\r | |
305 | IN UINT8 OrData\r | |
ed66e1bc | 306 | );\r |
fb3df220 | 307 | \r |
308 | /**\r | |
309 | Reads a 16-bit PCI configuration register.\r | |
310 | \r | |
311 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
312 | This function must guarantee that all PCI read and write operations are serialized.\r | |
313 | If any reserved bits in Address are set, then ASSERT().\r | |
314 | \r | |
315 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
316 | \r | |
317 | @return The 16-bit PCI configuration register specified by Address.\r | |
318 | \r | |
319 | **/\r | |
320 | UINT16\r | |
321 | EFIAPI\r | |
322 | PciSegmentRead16 (\r | |
323 | IN UINT64 Address\r | |
ed66e1bc | 324 | );\r |
fb3df220 | 325 | \r |
326 | /**\r | |
327 | Writes a 16-bit PCI configuration register.\r | |
328 | \r | |
329 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
330 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
331 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
332 | \r | |
333 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
334 | @param Value The value to write.\r | |
335 | \r | |
336 | @return The parameter of Value.\r | |
337 | \r | |
338 | **/\r | |
339 | UINT16\r | |
340 | EFIAPI\r | |
341 | PciSegmentWrite16 (\r | |
342 | IN UINT64 Address,\r | |
343 | IN UINT16 Value\r | |
ed66e1bc | 344 | );\r |
fb3df220 | 345 | \r |
346 | /**\r | |
347 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.\r | |
348 | \r | |
349 | Reads the 16-bit PCI configuration register specified by Address,\r | |
350 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
351 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
352 | The value written to the PCI configuration register is returned.\r | |
353 | This function must guarantee that all PCI read and write operations are serialized.\r | |
354 | If any reserved bits in Address are set, then ASSERT().\r | |
355 | \r | |
356 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
357 | @param OrData The value to OR with the PCI configuration register.\r | |
358 | \r | |
359 | @return The value written to the PCI configuration register.\r | |
360 | \r | |
361 | **/\r | |
362 | UINT16\r | |
363 | EFIAPI\r | |
364 | PciSegmentOr16 (\r | |
365 | IN UINT64 Address,\r | |
366 | IN UINT16 OrData\r | |
ed66e1bc | 367 | );\r |
fb3df220 | 368 | \r |
369 | /**\r | |
370 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r | |
371 | \r | |
372 | Reads the 16-bit PCI configuration register specified by Address,\r | |
373 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
374 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
375 | The value written to the PCI configuration register is returned.\r | |
376 | This function must guarantee that all PCI read and write operations are serialized.\r | |
377 | If any reserved bits in Address are set, then ASSERT().\r | |
378 | \r | |
379 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 380 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 381 | \r |
382 | @return The value written to the PCI configuration register.\r | |
383 | \r | |
384 | **/\r | |
385 | UINT16\r | |
386 | EFIAPI\r | |
387 | PciSegmentAnd16 (\r | |
388 | IN UINT64 Address,\r | |
389 | IN UINT16 AndData\r | |
ed66e1bc | 390 | );\r |
fb3df220 | 391 | \r |
392 | /**\r | |
393 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
394 | followed a bitwise inclusive OR with another 16-bit value.\r | |
395 | \r | |
396 | Reads the 16-bit PCI configuration register specified by Address,\r | |
397 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
398 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r | |
399 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
400 | The value written to the PCI configuration register is returned.\r | |
401 | This function must guarantee that all PCI read and write operations are serialized.\r | |
402 | If any reserved bits in Address are set, then ASSERT().\r | |
403 | \r | |
404 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
42eedea9 | 405 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 406 | @param OrData The value to OR with the PCI configuration register.\r |
407 | \r | |
408 | @return The value written to the PCI configuration register.\r | |
409 | \r | |
410 | **/\r | |
411 | UINT16\r | |
412 | EFIAPI\r | |
413 | PciSegmentAndThenOr16 (\r | |
414 | IN UINT64 Address,\r | |
415 | IN UINT16 AndData,\r | |
416 | IN UINT16 OrData\r | |
ed66e1bc | 417 | );\r |
fb3df220 | 418 | \r |
419 | /**\r | |
420 | Reads a bit field of a PCI configuration register.\r | |
421 | \r | |
422 | Reads the bit field in a 16-bit PCI configuration register.\r | |
423 | The bit field is specified by the StartBit and the EndBit.\r | |
424 | The value of the bit field is returned.\r | |
425 | If any reserved bits in Address are set, then ASSERT().\r | |
426 | If StartBit is greater than 7, then ASSERT().\r | |
427 | If EndBit is greater than 7, then ASSERT().\r | |
428 | If EndBit is less than StartBit, then ASSERT().\r | |
429 | \r | |
430 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
431 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
432 | The ordinal of the least significant bit in a byte is bit 0.\r | |
433 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
434 | The ordinal of the most significant bit in a byte is bit 7.\r | |
435 | \r | |
436 | @return The value of the bit field.\r | |
437 | \r | |
438 | **/\r | |
439 | UINT16\r | |
440 | EFIAPI\r | |
441 | PciSegmentBitFieldRead16 (\r | |
442 | IN UINT64 Address,\r | |
443 | IN UINTN StartBit,\r | |
444 | IN UINTN EndBit\r | |
ed66e1bc | 445 | );\r |
fb3df220 | 446 | \r |
447 | /**\r | |
448 | Writes a bit field to a PCI configuration register.\r | |
449 | \r | |
450 | Writes Value to the bit field of the PCI configuration register.\r | |
451 | The bit field is specified by the StartBit and the EndBit.\r | |
452 | All other bits in the destination PCI configuration register are preserved.\r | |
453 | The new value of the 16-bit register is returned.\r | |
454 | If any reserved bits in Address are set, then ASSERT().\r | |
455 | If StartBit is greater than 7, then ASSERT().\r | |
456 | If EndBit is greater than 7, then ASSERT().\r | |
457 | If EndBit is less than StartBit, then ASSERT().\r | |
458 | \r | |
459 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
460 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
461 | The ordinal of the least significant bit in a byte is bit 0.\r | |
462 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
463 | The ordinal of the most significant bit in a byte is bit 7.\r | |
464 | @param Value New value of the bit field.\r | |
465 | \r | |
466 | @return The new value of the 16-bit register.\r | |
467 | \r | |
468 | **/\r | |
469 | UINT16\r | |
470 | EFIAPI\r | |
471 | PciSegmentBitFieldWrite16 (\r | |
472 | IN UINT64 Address,\r | |
473 | IN UINTN StartBit,\r | |
474 | IN UINTN EndBit,\r | |
475 | IN UINT16 Value\r | |
ed66e1bc | 476 | );\r |
fb3df220 | 477 | \r |
478 | /**\r | |
479 | Reads the 16-bit PCI configuration register specified by Address,\r | |
480 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
481 | and writes the result to the 16-bit PCI configuration register specified by Address. \r | |
482 | \r | |
483 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
484 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
485 | The ordinal of the least significant bit in a byte is bit 0.\r | |
486 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
487 | The ordinal of the most significant bit in a byte is bit 7.\r | |
488 | @param OrData The value to OR with the read value from the PCI configuration register.\r | |
489 | \r | |
490 | @return The value written to the PCI configuration register.\r | |
491 | \r | |
492 | **/\r | |
493 | UINT16\r | |
494 | EFIAPI\r | |
495 | PciSegmentBitFieldOr16 (\r | |
496 | IN UINT64 Address,\r | |
497 | IN UINTN StartBit,\r | |
498 | IN UINTN EndBit,\r | |
499 | IN UINT16 OrData\r | |
ed66e1bc | 500 | );\r |
fb3df220 | 501 | \r |
502 | /**\r | |
503 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r | |
504 | and writes the result back to the bit field in the 16-bit port.\r | |
505 | \r | |
506 | Reads the 16-bit PCI configuration register specified by Address,\r | |
507 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
508 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
509 | The value written to the PCI configuration register is returned.\r | |
510 | This function must guarantee that all PCI read and write operations are serialized.\r | |
511 | Extra left bits in OrData are stripped.\r | |
512 | If any reserved bits in Address are set, then ASSERT().\r | |
513 | If StartBit is greater than 7, then ASSERT().\r | |
514 | If EndBit is greater than 7, then ASSERT().\r | |
515 | If EndBit is less than StartBit, then ASSERT().\r | |
516 | \r | |
517 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
518 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
519 | The ordinal of the least significant bit in a byte is bit 0.\r | |
520 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
521 | The ordinal of the most significant bit in a byte is bit 7.\r | |
522 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
523 | \r | |
524 | @return The value written to the PCI configuration register.\r | |
525 | \r | |
526 | **/\r | |
527 | UINT16\r | |
528 | EFIAPI\r | |
529 | PciSegmentBitFieldAnd16 (\r | |
530 | IN UINT64 Address,\r | |
531 | IN UINTN StartBit,\r | |
532 | IN UINTN EndBit,\r | |
533 | IN UINT16 AndData\r | |
ed66e1bc | 534 | );\r |
fb3df220 | 535 | \r |
536 | /**\r | |
537 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,\r | |
538 | and writes the result back to the bit field in the 16-bit register.\r | |
539 | \r | |
540 | Reads the 16-bit PCI configuration register specified by Address,\r | |
541 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
542 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
543 | The value written to the PCI configuration register is returned.\r | |
544 | This function must guarantee that all PCI read and write operations are serialized.\r | |
545 | Extra left bits in AndData are stripped.\r | |
546 | If any reserved bits in Address are set, then ASSERT().\r | |
547 | If StartBit is greater than 7, then ASSERT().\r | |
548 | If EndBit is greater than 7, then ASSERT().\r | |
549 | If EndBit is less than StartBit, then ASSERT().\r | |
550 | \r | |
551 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
552 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
553 | The ordinal of the least significant bit in a byte is bit 0.\r | |
554 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
555 | The ordinal of the most significant bit in a byte is bit 7.\r | |
556 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
557 | @param OrData The value to OR with the read value from the PCI configuration register.\r | |
558 | \r | |
559 | @return The value written to the PCI configuration register.\r | |
560 | \r | |
561 | **/\r | |
562 | UINT16\r | |
563 | EFIAPI\r | |
564 | PciSegmentBitFieldAndThenOr16 (\r | |
565 | IN UINT64 Address,\r | |
566 | IN UINTN StartBit,\r | |
567 | IN UINTN EndBit,\r | |
568 | IN UINT16 AndData,\r | |
569 | IN UINT16 OrData\r | |
ed66e1bc | 570 | );\r |
fb3df220 | 571 | \r |
572 | /**\r | |
573 | Reads a 32-bit PCI configuration register.\r | |
574 | \r | |
575 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
576 | This function must guarantee that all PCI read and write operations are serialized.\r | |
577 | If any reserved bits in Address are set, then ASSERT().\r | |
578 | \r | |
579 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
580 | \r | |
581 | @return The 32-bit PCI configuration register specified by Address.\r | |
582 | \r | |
583 | **/\r | |
584 | UINT32\r | |
585 | EFIAPI\r | |
586 | PciSegmentRead32 (\r | |
587 | IN UINT64 Address\r | |
ed66e1bc | 588 | );\r |
fb3df220 | 589 | \r |
590 | /**\r | |
591 | Writes a 32-bit PCI configuration register.\r | |
592 | \r | |
593 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
594 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
595 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
596 | \r | |
597 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
598 | @param Value The value to write.\r | |
599 | \r | |
600 | @return The parameter of Value.\r | |
601 | \r | |
602 | **/\r | |
603 | UINT32\r | |
604 | EFIAPI\r | |
605 | PciSegmentWrite32 (\r | |
606 | IN UINT64 Address,\r | |
607 | IN UINT32 Value\r | |
ed66e1bc | 608 | );\r |
fb3df220 | 609 | \r |
610 | /**\r | |
611 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.\r | |
612 | \r | |
613 | Reads the 32-bit PCI configuration register specified by Address,\r | |
614 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
615 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
616 | The value written to the PCI configuration register is returned.\r | |
617 | This function must guarantee that all PCI read and write operations are serialized.\r | |
618 | If any reserved bits in Address are set, then ASSERT().\r | |
619 | \r | |
620 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
621 | @param OrData The value to OR with the PCI configuration register.\r | |
622 | \r | |
623 | @return The value written to the PCI configuration register.\r | |
624 | \r | |
625 | **/\r | |
626 | UINT32\r | |
627 | EFIAPI\r | |
628 | PciSegmentOr32 (\r | |
629 | IN UINT64 Address,\r | |
630 | IN UINT32 OrData\r | |
ed66e1bc | 631 | );\r |
fb3df220 | 632 | \r |
633 | /**\r | |
634 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r | |
635 | \r | |
636 | Reads the 32-bit PCI configuration register specified by Address,\r | |
637 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
638 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
639 | The value written to the PCI configuration register is returned.\r | |
640 | This function must guarantee that all PCI read and write operations are serialized.\r | |
641 | If any reserved bits in Address are set, then ASSERT().\r | |
642 | \r | |
643 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 644 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 645 | \r |
646 | @return The value written to the PCI configuration register.\r | |
647 | \r | |
648 | **/\r | |
649 | UINT32\r | |
650 | EFIAPI\r | |
651 | PciSegmentAnd32 (\r | |
652 | IN UINT64 Address,\r | |
653 | IN UINT32 AndData\r | |
ed66e1bc | 654 | );\r |
fb3df220 | 655 | \r |
656 | /**\r | |
657 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
658 | followed a bitwise inclusive OR with another 32-bit value.\r | |
659 | \r | |
660 | Reads the 32-bit PCI configuration register specified by Address,\r | |
661 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
662 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r | |
663 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
664 | The value written to the PCI configuration register is returned.\r | |
665 | This function must guarantee that all PCI read and write operations are serialized.\r | |
666 | If any reserved bits in Address are set, then ASSERT().\r | |
667 | \r | |
668 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 669 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 670 | @param OrData The value to OR with the PCI configuration register.\r |
671 | \r | |
672 | @return The value written to the PCI configuration register.\r | |
673 | \r | |
674 | **/\r | |
675 | UINT32\r | |
676 | EFIAPI\r | |
677 | PciSegmentAndThenOr32 (\r | |
678 | IN UINT64 Address,\r | |
679 | IN UINT32 AndData,\r | |
680 | IN UINT32 OrData\r | |
ed66e1bc | 681 | );\r |
fb3df220 | 682 | \r |
683 | /**\r | |
684 | Reads a bit field of a PCI configuration register.\r | |
685 | \r | |
686 | Reads the bit field in a 32-bit PCI configuration register.\r | |
687 | The bit field is specified by the StartBit and the EndBit.\r | |
688 | The value of the bit field is returned.\r | |
689 | If any reserved bits in Address are set, then ASSERT().\r | |
690 | If StartBit is greater than 7, then ASSERT().\r | |
691 | If EndBit is greater than 7, then ASSERT().\r | |
692 | If EndBit is less than StartBit, then ASSERT().\r | |
693 | \r | |
694 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
695 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
696 | The ordinal of the least significant bit in a byte is bit 0.\r | |
697 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
698 | The ordinal of the most significant bit in a byte is bit 7.\r | |
699 | \r | |
700 | @return The value of the bit field.\r | |
701 | \r | |
702 | **/\r | |
703 | UINT32\r | |
704 | EFIAPI\r | |
705 | PciSegmentBitFieldRead32 (\r | |
706 | IN UINT64 Address,\r | |
707 | IN UINTN StartBit,\r | |
708 | IN UINTN EndBit\r | |
ed66e1bc | 709 | );\r |
fb3df220 | 710 | \r |
711 | /**\r | |
712 | Writes a bit field to a PCI configuration register.\r | |
713 | \r | |
714 | Writes Value to the bit field of the PCI configuration register.\r | |
715 | The bit field is specified by the StartBit and the EndBit.\r | |
716 | All other bits in the destination PCI configuration register are preserved.\r | |
717 | The new value of the 32-bit register is returned.\r | |
718 | If any reserved bits in Address are set, then ASSERT().\r | |
719 | If StartBit is greater than 7, then ASSERT().\r | |
720 | If EndBit is greater than 7, then ASSERT().\r | |
721 | If EndBit is less than StartBit, then ASSERT().\r | |
722 | \r | |
723 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
724 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
725 | The ordinal of the least significant bit in a byte is bit 0.\r | |
726 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
727 | The ordinal of the most significant bit in a byte is bit 7.\r | |
728 | @param Value New value of the bit field.\r | |
729 | \r | |
730 | @return The new value of the 32-bit register.\r | |
731 | \r | |
732 | **/\r | |
733 | UINT32\r | |
734 | EFIAPI\r | |
735 | PciSegmentBitFieldWrite32 (\r | |
736 | IN UINT64 Address,\r | |
737 | IN UINTN StartBit,\r | |
738 | IN UINTN EndBit,\r | |
739 | IN UINT32 Value\r | |
ed66e1bc | 740 | );\r |
fb3df220 | 741 | \r |
742 | /**\r | |
743 | Reads the 32-bit PCI configuration register specified by Address,\r | |
744 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
745 | and writes the result to the 32-bit PCI configuration register specified by Address. \r | |
746 | \r | |
747 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
748 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
749 | The ordinal of the least significant bit in a byte is bit 0.\r | |
750 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
751 | The ordinal of the most significant bit in a byte is bit 7.\r | |
752 | @param OrData The value to OR with the read value from the PCI configuration register.\r | |
753 | \r | |
754 | @return The value written to the PCI configuration register.\r | |
755 | \r | |
756 | **/\r | |
757 | UINT32\r | |
758 | EFIAPI\r | |
759 | PciSegmentBitFieldOr32 (\r | |
760 | IN UINT64 Address,\r | |
761 | IN UINTN StartBit,\r | |
762 | IN UINTN EndBit,\r | |
763 | IN UINT32 OrData\r | |
ed66e1bc | 764 | );\r |
fb3df220 | 765 | \r |
766 | /**\r | |
767 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,\r | |
768 | and writes the result back to the bit field in the 32-bit port.\r | |
769 | \r | |
770 | Reads the 32-bit PCI configuration register specified by Address,\r | |
771 | performs a bitwise inclusive OR between the read result and the value specified by OrData,\r | |
772 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
773 | The value written to the PCI configuration register is returned.\r | |
774 | This function must guarantee that all PCI read and write operations are serialized.\r | |
775 | Extra left bits in OrData are stripped.\r | |
776 | If any reserved bits in Address are set, then ASSERT().\r | |
777 | If StartBit is greater than 7, then ASSERT().\r | |
778 | If EndBit is greater than 7, then ASSERT().\r | |
779 | If EndBit is less than StartBit, then ASSERT().\r | |
780 | \r | |
781 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
782 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
783 | The ordinal of the least significant bit in a byte is bit 0.\r | |
784 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
785 | The ordinal of the most significant bit in a byte is bit 7.\r | |
786 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
787 | \r | |
788 | @return The value written to the PCI configuration register.\r | |
789 | \r | |
790 | **/\r | |
791 | UINT32\r | |
792 | EFIAPI\r | |
793 | PciSegmentBitFieldAnd32 (\r | |
794 | IN UINT64 Address,\r | |
795 | IN UINTN StartBit,\r | |
796 | IN UINTN EndBit,\r | |
797 | IN UINT32 AndData\r | |
ed66e1bc | 798 | );\r |
fb3df220 | 799 | \r |
800 | /**\r | |
801 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,\r | |
802 | and writes the result back to the bit field in the 32-bit register.\r | |
803 | \r | |
804 | Reads the 32-bit PCI configuration register specified by Address,\r | |
805 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
806 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
807 | The value written to the PCI configuration register is returned.\r | |
808 | This function must guarantee that all PCI read and write operations are serialized.\r | |
809 | Extra left bits in AndData are stripped.\r | |
810 | If any reserved bits in Address are set, then ASSERT().\r | |
811 | If StartBit is greater than 7, then ASSERT().\r | |
812 | If EndBit is greater than 7, then ASSERT().\r | |
813 | If EndBit is less than StartBit, then ASSERT().\r | |
814 | \r | |
815 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
816 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
817 | The ordinal of the least significant bit in a byte is bit 0.\r | |
818 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
819 | The ordinal of the most significant bit in a byte is bit 7.\r | |
820 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
821 | @param OrData The value to OR with the read value from the PCI configuration register.\r | |
822 | \r | |
823 | @return The value written to the PCI configuration register.\r | |
824 | \r | |
825 | **/\r | |
826 | UINT32\r | |
827 | EFIAPI\r | |
828 | PciSegmentBitFieldAndThenOr32 (\r | |
829 | IN UINT64 Address,\r | |
830 | IN UINTN StartBit,\r | |
831 | IN UINTN EndBit,\r | |
832 | IN UINT32 AndData,\r | |
833 | IN UINT32 OrData\r | |
ed66e1bc | 834 | );\r |
fb3df220 | 835 | \r |
836 | /**\r | |
837 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
838 | \r | |
839 | Reads the range of PCI configuration registers specified by StartAddress\r | |
840 | and Size into the buffer specified by Buffer.\r | |
841 | This function only allows the PCI configuration registers from a single PCI function to be read.\r | |
842 | Size is returned.\r | |
843 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
844 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
845 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r | |
846 | If Buffer is NULL, then ASSERT().\r | |
847 | \r | |
848 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
849 | @param Size Size in bytes of the transfer.\r | |
850 | @param Buffer Pointer to a buffer receiving the data read.\r | |
851 | \r | |
852 | @return The paramter of Size.\r | |
853 | \r | |
854 | **/\r | |
855 | UINTN\r | |
856 | EFIAPI\r | |
857 | PciSegmentReadBuffer (\r | |
858 | IN UINT64 StartAddress,\r | |
859 | IN UINTN Size,\r | |
860 | OUT VOID *Buffer\r | |
ed66e1bc | 861 | );\r |
fb3df220 | 862 | \r |
863 | /**\r | |
864 | Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r | |
865 | \r | |
866 | Writes the range of PCI configuration registers specified by StartAddress\r | |
867 | and Size from the buffer specified by Buffer.\r | |
868 | This function only allows the PCI configuration registers from a single PCI function to be written.\r | |
869 | Size is returned.\r | |
870 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
871 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
872 | If (StartAddress + Size - 1) > 0x0FFFFFFF, then ASSERT().\r | |
873 | If Buffer is NULL, then ASSERT().\r | |
874 | \r | |
875 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
876 | @param Size Size in bytes of the transfer.\r | |
877 | @param Buffer Pointer to a buffer containing the data to write.\r | |
878 | \r | |
879 | @return The paramter of Size.\r | |
880 | \r | |
881 | **/\r | |
882 | UINTN\r | |
883 | EFIAPI\r | |
884 | PciSegmentWriteBuffer (\r | |
885 | IN UINT64 StartAddress,\r | |
886 | IN UINTN Size,\r | |
887 | IN VOID *Buffer\r | |
ed66e1bc | 888 | );\r |
fb3df220 | 889 | \r |
890 | #endif\r |