]>
Commit | Line | Data |
---|---|---|
a2285a89 RN |
1 | /** @file\r |
2 | The multiple segments PCI configuration Library Services that carry out\r | |
3 | PCI configuration and enable the PCI operations to be replayed during an\r | |
4 | S3 resume. This library class maps directly on top of the PciSegmentLib class.\r | |
5 | \r | |
6 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a2285a89 RN |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef __S3_PCI_SEGMENT_LIB__\r | |
12 | #define __S3_PCI_SEGMENT_LIB__\r | |
13 | \r | |
a2285a89 RN |
14 | /**\r |
15 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
16 | and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.\r | |
17 | \r | |
18 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
19 | The unused upper bits of Segment, Bus, Device, Function,\r | |
20 | and Register are stripped prior to the generation of the address.\r | |
21 | \r | |
22 | @param Segment PCI Segment number. Range 0..65535.\r | |
23 | @param Bus PCI Bus number. Range 0..255.\r | |
24 | @param Device PCI Device number. Range 0..31.\r | |
25 | @param Function PCI Function number. Range 0..7.\r | |
26 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
27 | \r | |
28 | @return The address that is compatible with the PCI Segment Library functions.\r | |
29 | \r | |
30 | **/\r | |
2f88bd3a | 31 | #define S3_PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \\r |
a2285a89 RN |
32 | ((Segment != 0) ? \\r |
33 | ( ((Register) & 0xfff) | \\r | |
34 | (((Function) & 0x07) << 12) | \\r | |
35 | (((Device) & 0x1f) << 15) | \\r | |
36 | (((Bus) & 0xff) << 20) | \\r | |
37 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r | |
38 | ) : \\r | |
39 | ( ((Register) & 0xfff) | \\r | |
40 | (((Function) & 0x07) << 12) | \\r | |
41 | (((Device) & 0x1f) << 15) | \\r | |
42 | (((Bus) & 0xff) << 20) \\r | |
43 | ) \\r | |
44 | )\r | |
45 | \r | |
46 | /**\r | |
47 | Reads an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
48 | be replayed on S3 resume.\r | |
49 | \r | |
50 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
51 | This function must guarantee that all PCI read and write operations are serialized.\r | |
52 | \r | |
53 | If any reserved bits in Address are set, then ASSERT().\r | |
54 | \r | |
55 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
56 | \r | |
57 | @return The 8-bit PCI configuration register specified by Address.\r | |
58 | \r | |
59 | **/\r | |
60 | UINT8\r | |
61 | EFIAPI\r | |
62 | S3PciSegmentRead8 (\r | |
2f88bd3a | 63 | IN UINT64 Address\r |
a2285a89 RN |
64 | );\r |
65 | \r | |
66 | /**\r | |
67 | Writes an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
68 | be replayed on S3 resume.\r | |
69 | \r | |
70 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
71 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
72 | \r | |
73 | If any reserved bits in Address are set, then ASSERT().\r | |
74 | \r | |
75 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
76 | @param Value The value to write.\r | |
77 | \r | |
78 | @return The value written to the PCI configuration register.\r | |
79 | \r | |
80 | **/\r | |
81 | UINT8\r | |
82 | EFIAPI\r | |
83 | S3PciSegmentWrite8 (\r | |
2f88bd3a MK |
84 | IN UINT64 Address,\r |
85 | IN UINT8 Value\r | |
a2285a89 RN |
86 | );\r |
87 | \r | |
88 | /**\r | |
89 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves\r | |
90 | the value in the S3 script to be replayed on S3 resume.\r | |
91 | \r | |
92 | Reads the 8-bit PCI configuration register specified by Address,\r | |
93 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
94 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
95 | The value written to the PCI configuration register is returned.\r | |
96 | This function must guarantee that all PCI read and write operations are serialized.\r | |
97 | \r | |
98 | If any reserved bits in Address are set, then ASSERT().\r | |
99 | \r | |
100 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
101 | @param OrData The value to OR with the PCI configuration register.\r | |
102 | \r | |
103 | @return The value written to the PCI configuration register.\r | |
104 | \r | |
105 | **/\r | |
106 | UINT8\r | |
107 | EFIAPI\r | |
108 | S3PciSegmentOr8 (\r | |
2f88bd3a MK |
109 | IN UINT64 Address,\r |
110 | IN UINT8 OrData\r | |
a2285a89 RN |
111 | );\r |
112 | \r | |
113 | /**\r | |
114 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and\r | |
115 | saves the value in the S3 script to be replayed on S3 resume.\r | |
116 | \r | |
117 | Reads the 8-bit PCI configuration register specified by Address,\r | |
118 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
119 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
120 | The value written to the PCI configuration register is returned.\r | |
121 | This function must guarantee that all PCI read and write operations are serialized.\r | |
122 | If any reserved bits in Address are set, then ASSERT().\r | |
123 | \r | |
124 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
125 | @param AndData The value to AND with the PCI configuration register.\r | |
126 | \r | |
127 | @return The value written to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | S3PciSegmentAnd8 (\r | |
2f88bd3a MK |
133 | IN UINT64 Address,\r |
134 | IN UINT8 AndData\r | |
a2285a89 RN |
135 | );\r |
136 | \r | |
137 | /**\r | |
138 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
139 | followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to\r | |
140 | be replayed on S3 resume.\r | |
141 | \r | |
142 | Reads the 8-bit PCI configuration register specified by Address,\r | |
143 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
144 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
145 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
146 | The value written to the PCI configuration register is returned.\r | |
147 | This function must guarantee that all PCI read and write operations are serialized.\r | |
148 | \r | |
149 | If any reserved bits in Address are set, then ASSERT().\r | |
150 | \r | |
151 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
152 | @param AndData The value to AND with the PCI configuration register.\r | |
153 | @param OrData The value to OR with the PCI configuration register.\r | |
154 | \r | |
155 | @return The value written to the PCI configuration register.\r | |
156 | \r | |
157 | **/\r | |
158 | UINT8\r | |
159 | EFIAPI\r | |
160 | S3PciSegmentAndThenOr8 (\r | |
2f88bd3a MK |
161 | IN UINT64 Address,\r |
162 | IN UINT8 AndData,\r | |
163 | IN UINT8 OrData\r | |
a2285a89 RN |
164 | );\r |
165 | \r | |
166 | /**\r | |
167 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
168 | S3 script to be replayed on S3 resume.\r | |
169 | \r | |
170 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
171 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
172 | returned.\r | |
173 | \r | |
174 | If any reserved bits in Address are set, then ASSERT().\r | |
175 | If StartBit is greater than 7, then ASSERT().\r | |
176 | If EndBit is greater than 7, then ASSERT().\r | |
177 | If EndBit is less than StartBit, then ASSERT().\r | |
178 | \r | |
179 | @param Address PCI configuration register to read.\r | |
180 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
181 | Range 0..7.\r | |
182 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
183 | Range 0..7.\r | |
184 | \r | |
185 | @return The value of the bit field read from the PCI configuration register.\r | |
186 | \r | |
187 | **/\r | |
188 | UINT8\r | |
189 | EFIAPI\r | |
190 | S3PciSegmentBitFieldRead8 (\r | |
2f88bd3a MK |
191 | IN UINT64 Address,\r |
192 | IN UINTN StartBit,\r | |
193 | IN UINTN EndBit\r | |
a2285a89 RN |
194 | );\r |
195 | \r | |
196 | /**\r | |
197 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
198 | the S3 script to be replayed on S3 resume.\r | |
199 | \r | |
200 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
201 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
202 | destination PCI configuration register are preserved. The new value of the\r | |
203 | 8-bit register is returned.\r | |
204 | \r | |
205 | If any reserved bits in Address are set, then ASSERT().\r | |
206 | If StartBit is greater than 7, then ASSERT().\r | |
207 | If EndBit is greater than 7, then ASSERT().\r | |
208 | If EndBit is less than StartBit, then ASSERT().\r | |
209 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
210 | \r | |
211 | @param Address PCI configuration register to write.\r | |
212 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
213 | Range 0..7.\r | |
214 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
215 | Range 0..7.\r | |
216 | @param Value New value of the bit field.\r | |
217 | \r | |
218 | @return The value written back to the PCI configuration register.\r | |
219 | \r | |
220 | **/\r | |
221 | UINT8\r | |
222 | EFIAPI\r | |
223 | S3PciSegmentBitFieldWrite8 (\r | |
2f88bd3a MK |
224 | IN UINT64 Address,\r |
225 | IN UINTN StartBit,\r | |
226 | IN UINTN EndBit,\r | |
227 | IN UINT8 Value\r | |
a2285a89 RN |
228 | );\r |
229 | \r | |
230 | /**\r | |
231 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes\r | |
232 | the result back to the bit field in the 8-bit port, and saves the value in the\r | |
233 | S3 script to be replayed on S3 resume.\r | |
234 | \r | |
235 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
236 | bitwise OR between the read result and the value specified by\r | |
237 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
238 | specified by Address. The value written to the PCI configuration register is\r | |
239 | returned. This function must guarantee that all PCI read and write operations\r | |
240 | are serialized. Extra left bits in OrData are stripped.\r | |
241 | \r | |
242 | If any reserved bits in Address are set, then ASSERT().\r | |
243 | If StartBit is greater than 7, then ASSERT().\r | |
244 | If EndBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is less than StartBit, then ASSERT().\r | |
246 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
247 | \r | |
248 | @param Address PCI configuration register to write.\r | |
249 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
250 | Range 0..7.\r | |
251 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
252 | Range 0..7.\r | |
253 | @param OrData The value to OR with the PCI configuration register.\r | |
254 | \r | |
255 | @return The value written back to the PCI configuration register.\r | |
256 | \r | |
257 | **/\r | |
258 | UINT8\r | |
259 | EFIAPI\r | |
260 | S3PciSegmentBitFieldOr8 (\r | |
2f88bd3a MK |
261 | IN UINT64 Address,\r |
262 | IN UINTN StartBit,\r | |
263 | IN UINTN EndBit,\r | |
264 | IN UINT8 OrData\r | |
a2285a89 RN |
265 | );\r |
266 | \r | |
267 | /**\r | |
268 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
269 | AND, writes the result back to the bit field in the 8-bit register, and\r | |
270 | saves the value in the S3 script to be replayed on S3 resume.\r | |
271 | \r | |
272 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
273 | bitwise AND between the read result and the value specified by AndData, and\r | |
274 | writes the result to the 8-bit PCI configuration register specified by\r | |
275 | Address. The value written to the PCI configuration register is returned.\r | |
276 | This function must guarantee that all PCI read and write operations are\r | |
277 | serialized. Extra left bits in AndData are stripped.\r | |
278 | \r | |
279 | If any reserved bits in Address are set, then ASSERT().\r | |
280 | If StartBit is greater than 7, then ASSERT().\r | |
281 | If EndBit is greater than 7, then ASSERT().\r | |
282 | If EndBit is less than StartBit, then ASSERT().\r | |
283 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
284 | \r | |
285 | @param Address PCI configuration register to write.\r | |
286 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
287 | Range 0..7.\r | |
288 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
289 | Range 0..7.\r | |
290 | @param AndData The value to AND with the PCI configuration register.\r | |
291 | \r | |
292 | @return The value written back to the PCI configuration register.\r | |
293 | \r | |
294 | **/\r | |
295 | UINT8\r | |
296 | EFIAPI\r | |
297 | S3PciSegmentBitFieldAnd8 (\r | |
2f88bd3a MK |
298 | IN UINT64 Address,\r |
299 | IN UINTN StartBit,\r | |
300 | IN UINTN EndBit,\r | |
301 | IN UINT8 AndData\r | |
a2285a89 RN |
302 | );\r |
303 | \r | |
304 | /**\r | |
305 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
306 | bitwise OR, writes the result back to the bit field in the 8-bit port,\r | |
307 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
308 | \r | |
309 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
310 | bitwise AND followed by a bitwise OR between the read result and\r | |
311 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
312 | configuration register specified by Address. The value written to the PCI\r | |
313 | configuration register is returned. This function must guarantee that all PCI\r | |
314 | read and write operations are serialized. Extra left bits in both AndData and\r | |
315 | OrData are stripped.\r | |
316 | \r | |
317 | If any reserved bits in Address are set, then ASSERT().\r | |
318 | If StartBit is greater than 7, then ASSERT().\r | |
319 | If EndBit is greater than 7, then ASSERT().\r | |
320 | If EndBit is less than StartBit, then ASSERT().\r | |
321 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
322 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
323 | \r | |
324 | @param Address PCI configuration register to write.\r | |
325 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
326 | Range 0..7.\r | |
327 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
328 | Range 0..7.\r | |
329 | @param AndData The value to AND with the PCI configuration register.\r | |
330 | @param OrData The value to OR with the result of the AND operation.\r | |
331 | \r | |
332 | @return The value written back to the PCI configuration register.\r | |
333 | \r | |
334 | **/\r | |
335 | UINT8\r | |
336 | EFIAPI\r | |
337 | S3PciSegmentBitFieldAndThenOr8 (\r | |
2f88bd3a MK |
338 | IN UINT64 Address,\r |
339 | IN UINTN StartBit,\r | |
340 | IN UINTN EndBit,\r | |
341 | IN UINT8 AndData,\r | |
342 | IN UINT8 OrData\r | |
a2285a89 RN |
343 | );\r |
344 | \r | |
345 | /**\r | |
346 | Reads a 16-bit PCI configuration register, and saves the value in the S3 script\r | |
347 | to be replayed on S3 resume.\r | |
348 | \r | |
349 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
350 | This function must guarantee that all PCI read and write operations are serialized.\r | |
351 | \r | |
352 | If any reserved bits in Address are set, then ASSERT().\r | |
353 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
354 | \r | |
355 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
356 | \r | |
357 | @return The 16-bit PCI configuration register specified by Address.\r | |
358 | \r | |
359 | **/\r | |
360 | UINT16\r | |
361 | EFIAPI\r | |
362 | S3PciSegmentRead16 (\r | |
2f88bd3a | 363 | IN UINT64 Address\r |
a2285a89 RN |
364 | );\r |
365 | \r | |
366 | /**\r | |
367 | Writes a 16-bit PCI configuration register, and saves the value in the S3 script to\r | |
368 | be replayed on S3 resume.\r | |
369 | \r | |
370 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
371 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
372 | \r | |
373 | If any reserved bits in Address are set, then ASSERT().\r | |
374 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
375 | \r | |
376 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
377 | @param Value The value to write.\r | |
378 | \r | |
379 | @return The parameter of Value.\r | |
380 | \r | |
381 | **/\r | |
382 | UINT16\r | |
383 | EFIAPI\r | |
384 | S3PciSegmentWrite16 (\r | |
2f88bd3a MK |
385 | IN UINT64 Address,\r |
386 | IN UINT16 Value\r | |
a2285a89 RN |
387 | );\r |
388 | \r | |
389 | /**\r | |
390 | Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit\r | |
391 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
392 | \r | |
393 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
394 | bitwise OR between the read result and the value specified by OrData, and\r | |
395 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
396 | The value written to the PCI configuration register is returned. This function\r | |
397 | must guarantee that all PCI read and write operations are serialized.\r | |
398 | \r | |
399 | If any reserved bits in Address are set, then ASSERT().\r | |
400 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
401 | \r | |
402 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
403 | Register.\r | |
404 | @param OrData The value to OR with the PCI configuration register.\r | |
405 | \r | |
406 | @return The value written back to the PCI configuration register.\r | |
407 | \r | |
408 | **/\r | |
409 | UINT16\r | |
410 | EFIAPI\r | |
411 | S3PciSegmentOr16 (\r | |
2f88bd3a MK |
412 | IN UINT64 Address,\r |
413 | IN UINT16 OrData\r | |
a2285a89 RN |
414 | );\r |
415 | \r | |
416 | /**\r | |
417 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and\r | |
418 | saves the value in the S3 script to be replayed on S3 resume.\r | |
419 | \r | |
420 | Reads the 16-bit PCI configuration register specified by Address,\r | |
421 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
422 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
423 | The value written to the PCI configuration register is returned.\r | |
424 | This function must guarantee that all PCI read and write operations are serialized.\r | |
425 | \r | |
426 | If any reserved bits in Address are set, then ASSERT().\r | |
427 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
428 | \r | |
429 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
430 | @param AndData The value to AND with the PCI configuration register.\r | |
431 | \r | |
432 | @return The value written to the PCI configuration register.\r | |
433 | \r | |
434 | **/\r | |
435 | UINT16\r | |
436 | EFIAPI\r | |
437 | S3PciSegmentAnd16 (\r | |
2f88bd3a MK |
438 | IN UINT64 Address,\r |
439 | IN UINT16 AndData\r | |
a2285a89 RN |
440 | );\r |
441 | \r | |
442 | /**\r | |
443 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
444 | followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to\r | |
445 | be replayed on S3 resume.\r | |
446 | \r | |
447 | Reads the 16-bit PCI configuration register specified by Address,\r | |
448 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
449 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
450 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
451 | The value written to the PCI configuration register is returned.\r | |
452 | This function must guarantee that all PCI read and write operations are serialized.\r | |
453 | \r | |
454 | If any reserved bits in Address are set, then ASSERT().\r | |
455 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
456 | \r | |
457 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
458 | @param AndData The value to AND with the PCI configuration register.\r | |
459 | @param OrData The value to OR with the PCI configuration register.\r | |
460 | \r | |
461 | @return The value written to the PCI configuration register.\r | |
462 | \r | |
463 | **/\r | |
464 | UINT16\r | |
465 | EFIAPI\r | |
466 | S3PciSegmentAndThenOr16 (\r | |
2f88bd3a MK |
467 | IN UINT64 Address,\r |
468 | IN UINT16 AndData,\r | |
469 | IN UINT16 OrData\r | |
a2285a89 RN |
470 | );\r |
471 | \r | |
472 | /**\r | |
473 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
474 | S3 script to be replayed on S3 resume.\r | |
475 | \r | |
476 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
477 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
478 | returned.\r | |
479 | \r | |
480 | If any reserved bits in Address are set, then ASSERT().\r | |
481 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
482 | If StartBit is greater than 15, then ASSERT().\r | |
483 | If EndBit is greater than 15, then ASSERT().\r | |
484 | If EndBit is less than StartBit, then ASSERT().\r | |
485 | \r | |
486 | @param Address PCI configuration register to read.\r | |
487 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
488 | Range 0..15.\r | |
489 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
490 | Range 0..15.\r | |
491 | \r | |
492 | @return The value of the bit field read from the PCI configuration register.\r | |
493 | \r | |
494 | **/\r | |
495 | UINT16\r | |
496 | EFIAPI\r | |
497 | S3PciSegmentBitFieldRead16 (\r | |
2f88bd3a MK |
498 | IN UINT64 Address,\r |
499 | IN UINTN StartBit,\r | |
500 | IN UINTN EndBit\r | |
a2285a89 RN |
501 | );\r |
502 | \r | |
503 | /**\r | |
504 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
505 | the S3 script to be replayed on S3 resume.\r | |
506 | \r | |
507 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
508 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
509 | destination PCI configuration register are preserved. The new value of the\r | |
510 | 16-bit register is returned.\r | |
511 | \r | |
512 | If any reserved bits in Address are set, then ASSERT().\r | |
513 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
514 | If StartBit is greater than 15, then ASSERT().\r | |
515 | If EndBit is greater than 15, then ASSERT().\r | |
516 | If EndBit is less than StartBit, then ASSERT().\r | |
517 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
518 | \r | |
519 | @param Address PCI configuration register to write.\r | |
520 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
521 | Range 0..15.\r | |
522 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
523 | Range 0..15.\r | |
524 | @param Value New value of the bit field.\r | |
525 | \r | |
526 | @return The value written back to the PCI configuration register.\r | |
527 | \r | |
528 | **/\r | |
529 | UINT16\r | |
530 | EFIAPI\r | |
531 | S3PciSegmentBitFieldWrite16 (\r | |
2f88bd3a MK |
532 | IN UINT64 Address,\r |
533 | IN UINTN StartBit,\r | |
534 | IN UINTN EndBit,\r | |
535 | IN UINT16 Value\r | |
a2285a89 RN |
536 | );\r |
537 | \r | |
538 | /**\r | |
539 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
540 | the result back to the bit field in the 16-bit port, and saves the value in the\r | |
541 | S3 script to be replayed on S3 resume.\r | |
542 | \r | |
543 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
544 | bitwise OR between the read result and the value specified by\r | |
545 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
546 | specified by Address. The value written to the PCI configuration register is\r | |
547 | returned. This function must guarantee that all PCI read and write operations\r | |
548 | are serialized. Extra left bits in OrData are stripped.\r | |
549 | \r | |
550 | If any reserved bits in Address are set, then ASSERT().\r | |
551 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
552 | If StartBit is greater than 15, then ASSERT().\r | |
553 | If EndBit is greater than 15, then ASSERT().\r | |
554 | If EndBit is less than StartBit, then ASSERT().\r | |
555 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
556 | \r | |
557 | @param Address PCI configuration register to write.\r | |
558 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
559 | Range 0..15.\r | |
560 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
561 | Range 0..15.\r | |
562 | @param OrData The value to OR with the PCI configuration register.\r | |
563 | \r | |
564 | @return The value written back to the PCI configuration register.\r | |
565 | \r | |
566 | **/\r | |
567 | UINT16\r | |
568 | EFIAPI\r | |
569 | S3PciSegmentBitFieldOr16 (\r | |
2f88bd3a MK |
570 | IN UINT64 Address,\r |
571 | IN UINTN StartBit,\r | |
572 | IN UINTN EndBit,\r | |
573 | IN UINT16 OrData\r | |
a2285a89 RN |
574 | );\r |
575 | \r | |
576 | /**\r | |
577 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
578 | AND, writes the result back to the bit field in the 16-bit register, and\r | |
579 | saves the value in the S3 script to be replayed on S3 resume.\r | |
580 | \r | |
581 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
582 | bitwise AND between the read result and the value specified by AndData, and\r | |
583 | writes the result to the 16-bit PCI configuration register specified by\r | |
584 | Address. The value written to the PCI configuration register is returned.\r | |
585 | This function must guarantee that all PCI read and write operations are\r | |
586 | serialized. Extra left bits in AndData are stripped.\r | |
587 | \r | |
588 | If any reserved bits in Address are set, then ASSERT().\r | |
589 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
590 | If StartBit is greater than 15, then ASSERT().\r | |
591 | If EndBit is greater than 15, then ASSERT().\r | |
592 | If EndBit is less than StartBit, then ASSERT().\r | |
593 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
594 | \r | |
595 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
596 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
597 | Range 0..15.\r | |
598 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
599 | Range 0..15.\r | |
600 | @param AndData The value to AND with the PCI configuration register.\r | |
601 | \r | |
602 | @return The value written back to the PCI configuration register.\r | |
603 | \r | |
604 | **/\r | |
605 | UINT16\r | |
606 | EFIAPI\r | |
607 | S3PciSegmentBitFieldAnd16 (\r | |
2f88bd3a MK |
608 | IN UINT64 Address,\r |
609 | IN UINTN StartBit,\r | |
610 | IN UINTN EndBit,\r | |
611 | IN UINT16 AndData\r | |
a2285a89 RN |
612 | );\r |
613 | \r | |
614 | /**\r | |
615 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
616 | bitwise OR, writes the result back to the bit field in the 16-bit port,\r | |
617 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
618 | \r | |
619 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
620 | bitwise AND followed by a bitwise OR between the read result and\r | |
621 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
622 | configuration register specified by Address. The value written to the PCI\r | |
623 | configuration register is returned. This function must guarantee that all PCI\r | |
624 | read and write operations are serialized. Extra left bits in both AndData and\r | |
625 | OrData are stripped.\r | |
626 | \r | |
627 | If any reserved bits in Address are set, then ASSERT().\r | |
628 | If StartBit is greater than 15, then ASSERT().\r | |
629 | If EndBit is greater than 15, then ASSERT().\r | |
630 | If EndBit is less than StartBit, then ASSERT().\r | |
631 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
632 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
633 | \r | |
634 | @param Address PCI configuration register to write.\r | |
635 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
636 | Range 0..15.\r | |
637 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
638 | Range 0..15.\r | |
639 | @param AndData The value to AND with the PCI configuration register.\r | |
640 | @param OrData The value to OR with the result of the AND operation.\r | |
641 | \r | |
642 | @return The value written back to the PCI configuration register.\r | |
643 | \r | |
644 | **/\r | |
645 | UINT16\r | |
646 | EFIAPI\r | |
647 | S3PciSegmentBitFieldAndThenOr16 (\r | |
2f88bd3a MK |
648 | IN UINT64 Address,\r |
649 | IN UINTN StartBit,\r | |
650 | IN UINTN EndBit,\r | |
651 | IN UINT16 AndData,\r | |
652 | IN UINT16 OrData\r | |
a2285a89 RN |
653 | );\r |
654 | \r | |
655 | /**\r | |
656 | Reads a 32-bit PCI configuration register, and saves the value in the S3 script\r | |
657 | to be replayed on S3 resume.\r | |
658 | \r | |
659 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
660 | This function must guarantee that all PCI read and write operations are serialized.\r | |
661 | \r | |
662 | If any reserved bits in Address are set, then ASSERT().\r | |
663 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
664 | \r | |
665 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
666 | \r | |
667 | @return The 32-bit PCI configuration register specified by Address.\r | |
668 | \r | |
669 | **/\r | |
670 | UINT32\r | |
671 | EFIAPI\r | |
672 | S3PciSegmentRead32 (\r | |
2f88bd3a | 673 | IN UINT64 Address\r |
a2285a89 RN |
674 | );\r |
675 | \r | |
676 | /**\r | |
677 | Writes a 32-bit PCI configuration register, and saves the value in the S3 script to\r | |
678 | be replayed on S3 resume.\r | |
679 | \r | |
680 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
681 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
682 | \r | |
683 | If any reserved bits in Address are set, then ASSERT().\r | |
684 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
685 | \r | |
686 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
687 | @param Value The value to write.\r | |
688 | \r | |
689 | @return The parameter of Value.\r | |
690 | \r | |
691 | **/\r | |
692 | UINT32\r | |
693 | EFIAPI\r | |
694 | S3PciSegmentWrite32 (\r | |
2f88bd3a MK |
695 | IN UINT64 Address,\r |
696 | IN UINT32 Value\r | |
a2285a89 RN |
697 | );\r |
698 | \r | |
699 | /**\r | |
700 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit\r | |
701 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
702 | \r | |
703 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
704 | bitwise OR between the read result and the value specified by OrData, and\r | |
705 | writes the result to the 32-bit PCI configuration register specified by Address.\r | |
706 | The value written to the PCI configuration register is returned. This function\r | |
707 | must guarantee that all PCI read and write operations are serialized.\r | |
708 | \r | |
709 | If any reserved bits in Address are set, then ASSERT().\r | |
710 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
711 | \r | |
712 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and\r | |
713 | Register.\r | |
714 | @param OrData The value to OR with the PCI configuration register.\r | |
715 | \r | |
716 | @return The value written back to the PCI configuration register.\r | |
717 | \r | |
718 | **/\r | |
719 | UINT32\r | |
720 | EFIAPI\r | |
721 | S3PciSegmentOr32 (\r | |
2f88bd3a MK |
722 | IN UINT64 Address,\r |
723 | IN UINT32 OrData\r | |
a2285a89 RN |
724 | );\r |
725 | \r | |
726 | /**\r | |
727 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and\r | |
728 | saves the value in the S3 script to be replayed on S3 resume.\r | |
729 | \r | |
730 | Reads the 32-bit PCI configuration register specified by Address,\r | |
731 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
732 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
733 | The value written to the PCI configuration register is returned.\r | |
734 | This function must guarantee that all PCI read and write operations are serialized.\r | |
735 | \r | |
736 | If any reserved bits in Address are set, then ASSERT().\r | |
737 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
738 | \r | |
739 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
740 | @param AndData The value to AND with the PCI configuration register.\r | |
741 | \r | |
742 | @return The value written to the PCI configuration register.\r | |
743 | \r | |
744 | **/\r | |
745 | UINT32\r | |
746 | EFIAPI\r | |
747 | S3PciSegmentAnd32 (\r | |
2f88bd3a MK |
748 | IN UINT64 Address,\r |
749 | IN UINT32 AndData\r | |
a2285a89 RN |
750 | );\r |
751 | \r | |
752 | /**\r | |
753 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
754 | followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to\r | |
755 | be replayed on S3 resume.\r | |
756 | \r | |
757 | Reads the 32-bit PCI configuration register specified by Address,\r | |
758 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
759 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
760 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
761 | The value written to the PCI configuration register is returned.\r | |
762 | This function must guarantee that all PCI read and write operations are serialized.\r | |
763 | \r | |
764 | If any reserved bits in Address are set, then ASSERT().\r | |
765 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
766 | \r | |
767 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
768 | @param AndData The value to AND with the PCI configuration register.\r | |
769 | @param OrData The value to OR with the PCI configuration register.\r | |
770 | \r | |
771 | @return The value written to the PCI configuration register.\r | |
772 | \r | |
773 | **/\r | |
774 | UINT32\r | |
775 | EFIAPI\r | |
776 | S3PciSegmentAndThenOr32 (\r | |
2f88bd3a MK |
777 | IN UINT64 Address,\r |
778 | IN UINT32 AndData,\r | |
779 | IN UINT32 OrData\r | |
a2285a89 RN |
780 | );\r |
781 | \r | |
782 | /**\r | |
783 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
784 | S3 script to be replayed on S3 resume.\r | |
785 | \r | |
786 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
787 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
788 | returned.\r | |
789 | \r | |
790 | If any reserved bits in Address are set, then ASSERT().\r | |
791 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
792 | If StartBit is greater than 31, then ASSERT().\r | |
793 | If EndBit is greater than 31, then ASSERT().\r | |
794 | If EndBit is less than StartBit, then ASSERT().\r | |
795 | \r | |
796 | @param Address PCI configuration register to read.\r | |
797 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
798 | Range 0..31.\r | |
799 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
800 | Range 0..31.\r | |
801 | \r | |
802 | @return The value of the bit field read from the PCI configuration register.\r | |
803 | \r | |
804 | **/\r | |
805 | UINT32\r | |
806 | EFIAPI\r | |
807 | S3PciSegmentBitFieldRead32 (\r | |
2f88bd3a MK |
808 | IN UINT64 Address,\r |
809 | IN UINTN StartBit,\r | |
810 | IN UINTN EndBit\r | |
a2285a89 RN |
811 | );\r |
812 | \r | |
813 | /**\r | |
814 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
815 | the S3 script to be replayed on S3 resume.\r | |
816 | \r | |
817 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
818 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
819 | destination PCI configuration register are preserved. The new value of the\r | |
820 | 32-bit register is returned.\r | |
821 | \r | |
822 | If any reserved bits in Address are set, then ASSERT().\r | |
823 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
824 | If StartBit is greater than 31, then ASSERT().\r | |
825 | If EndBit is greater than 31, then ASSERT().\r | |
826 | If EndBit is less than StartBit, then ASSERT().\r | |
827 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
828 | \r | |
829 | @param Address PCI configuration register to write.\r | |
830 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
831 | Range 0..31.\r | |
832 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
833 | Range 0..31.\r | |
834 | @param Value New value of the bit field.\r | |
835 | \r | |
836 | @return The value written back to the PCI configuration register.\r | |
837 | \r | |
838 | **/\r | |
839 | UINT32\r | |
840 | EFIAPI\r | |
841 | S3PciSegmentBitFieldWrite32 (\r | |
2f88bd3a MK |
842 | IN UINT64 Address,\r |
843 | IN UINTN StartBit,\r | |
844 | IN UINTN EndBit,\r | |
845 | IN UINT32 Value\r | |
a2285a89 RN |
846 | );\r |
847 | \r | |
848 | /**\r | |
849 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes\r | |
850 | the result back to the bit field in the 32-bit port, and saves the value in the\r | |
851 | S3 script to be replayed on S3 resume.\r | |
852 | \r | |
853 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
854 | bitwise OR between the read result and the value specified by\r | |
855 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
856 | specified by Address. The value written to the PCI configuration register is\r | |
857 | returned. This function must guarantee that all PCI read and write operations\r | |
858 | are serialized. Extra left bits in OrData are stripped.\r | |
859 | \r | |
860 | If any reserved bits in Address are set, then ASSERT().\r | |
861 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
862 | If StartBit is greater than 31, then ASSERT().\r | |
863 | If EndBit is greater than 31, then ASSERT().\r | |
864 | If EndBit is less than StartBit, then ASSERT().\r | |
865 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
866 | \r | |
867 | @param Address PCI configuration register to write.\r | |
868 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
869 | Range 0..31.\r | |
870 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
871 | Range 0..31.\r | |
872 | @param OrData The value to OR with the PCI configuration register.\r | |
873 | \r | |
874 | @return The value written back to the PCI configuration register.\r | |
875 | \r | |
876 | **/\r | |
877 | UINT32\r | |
878 | EFIAPI\r | |
879 | S3PciSegmentBitFieldOr32 (\r | |
2f88bd3a MK |
880 | IN UINT64 Address,\r |
881 | IN UINTN StartBit,\r | |
882 | IN UINTN EndBit,\r | |
883 | IN UINT32 OrData\r | |
a2285a89 RN |
884 | );\r |
885 | \r | |
886 | /**\r | |
887 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
888 | AND, and writes the result back to the bit field in the 32-bit register, and\r | |
889 | saves the value in the S3 script to be replayed on S3 resume.\r | |
890 | \r | |
891 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
892 | bitwise AND between the read result and the value specified by AndData, and\r | |
893 | writes the result to the 32-bit PCI configuration register specified by\r | |
894 | Address. The value written to the PCI configuration register is returned.\r | |
895 | This function must guarantee that all PCI read and write operations are\r | |
896 | serialized. Extra left bits in AndData are stripped.\r | |
897 | \r | |
898 | If any reserved bits in Address are set, then ASSERT().\r | |
899 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
900 | If StartBit is greater than 31, then ASSERT().\r | |
901 | If EndBit is greater than 31, then ASSERT().\r | |
902 | If EndBit is less than StartBit, then ASSERT().\r | |
903 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
904 | \r | |
905 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
906 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
907 | Range 0..31.\r | |
908 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
909 | Range 0..31.\r | |
910 | @param AndData The value to AND with the PCI configuration register.\r | |
911 | \r | |
912 | @return The value written back to the PCI configuration register.\r | |
913 | \r | |
914 | **/\r | |
915 | UINT32\r | |
916 | EFIAPI\r | |
917 | S3PciSegmentBitFieldAnd32 (\r | |
2f88bd3a MK |
918 | IN UINT64 Address,\r |
919 | IN UINTN StartBit,\r | |
920 | IN UINTN EndBit,\r | |
921 | IN UINT32 AndData\r | |
a2285a89 RN |
922 | );\r |
923 | \r | |
924 | /**\r | |
925 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
926 | bitwise OR, writes the result back to the bit field in the 32-bit port,\r | |
927 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
928 | \r | |
929 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
930 | bitwise AND followed by a bitwise OR between the read result and\r | |
931 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
932 | configuration register specified by Address. The value written to the PCI\r | |
933 | configuration register is returned. This function must guarantee that all PCI\r | |
934 | read and write operations are serialized. Extra left bits in both AndData and\r | |
935 | OrData are stripped.\r | |
936 | \r | |
937 | If any reserved bits in Address are set, then ASSERT().\r | |
938 | If StartBit is greater than 31, then ASSERT().\r | |
939 | If EndBit is greater than 31, then ASSERT().\r | |
940 | If EndBit is less than StartBit, then ASSERT().\r | |
941 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
942 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
943 | \r | |
944 | @param Address PCI configuration register to write.\r | |
945 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
946 | Range 0..31.\r | |
947 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
948 | Range 0..31.\r | |
949 | @param AndData The value to AND with the PCI configuration register.\r | |
950 | @param OrData The value to OR with the result of the AND operation.\r | |
951 | \r | |
952 | @return The value written back to the PCI configuration register.\r | |
953 | \r | |
954 | **/\r | |
955 | UINT32\r | |
956 | EFIAPI\r | |
957 | S3PciSegmentBitFieldAndThenOr32 (\r | |
2f88bd3a MK |
958 | IN UINT64 Address,\r |
959 | IN UINTN StartBit,\r | |
960 | IN UINTN EndBit,\r | |
961 | IN UINT32 AndData,\r | |
962 | IN UINT32 OrData\r | |
a2285a89 RN |
963 | );\r |
964 | \r | |
965 | /**\r | |
966 | Reads a range of PCI configuration registers into a caller supplied buffer,\r | |
967 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
968 | \r | |
969 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
970 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
971 | configuration registers from a single PCI function to be read. Size is\r | |
972 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
973 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
974 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
975 | end of the range.\r | |
976 | \r | |
977 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
978 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
979 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
980 | \r | |
981 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
982 | Function and Register.\r | |
983 | @param Size Size in bytes of the transfer.\r | |
984 | @param Buffer Pointer to a buffer receiving the data read.\r | |
985 | \r | |
986 | @return Size\r | |
987 | \r | |
988 | **/\r | |
989 | UINTN\r | |
990 | EFIAPI\r | |
991 | S3PciSegmentReadBuffer (\r | |
2f88bd3a MK |
992 | IN UINT64 StartAddress,\r |
993 | IN UINTN Size,\r | |
994 | OUT VOID *Buffer\r | |
a2285a89 RN |
995 | );\r |
996 | \r | |
997 | /**\r | |
998 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
999 | configuration space, and saves the value in the S3 script to be replayed on S3\r | |
1000 | resume.\r | |
1001 | \r | |
1002 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1003 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1004 | configuration registers from a single PCI function to be written. Size is\r | |
1005 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1006 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1007 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1008 | and the end of the range.\r | |
1009 | \r | |
1010 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1011 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1012 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1013 | \r | |
1014 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1015 | Function and Register.\r | |
1016 | @param Size Size in bytes of the transfer.\r | |
1017 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1018 | \r | |
1019 | @return The parameter of Size.\r | |
1020 | \r | |
1021 | **/\r | |
1022 | UINTN\r | |
1023 | EFIAPI\r | |
1024 | S3PciSegmentWriteBuffer (\r | |
2f88bd3a MK |
1025 | IN UINT64 StartAddress,\r |
1026 | IN UINTN Size,\r | |
1027 | IN VOID *Buffer\r | |
a2285a89 RN |
1028 | );\r |
1029 | \r | |
1030 | #endif\r |