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4006b0b5 | 1 | /** @file\r |
9095d37b | 2 | This PPI manipulates the I2C host controller to perform transactions as a master\r |
4006b0b5 EL |
3 | on the I2C bus using the current state of any switches or multiplexers in the I2C bus.\r |
4 | \r | |
9095d37b | 5 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4006b0b5 EL |
7 | \r |
8 | @par Revision Reference:\r | |
9 | This PPI is introduced in PI Version 1.3.\r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef __I2C_MASTER_PPI_H__\r | |
14 | #define __I2C_MASTER_PPI_H__\r | |
15 | \r | |
16 | #include <Pi/PiI2c.h>\r | |
17 | \r | |
18 | #define EFI_PEI_I2C_MASTER_PPI_GUID \\r | |
19 | { 0xb3bfab9b, 0x9f9c, 0x4e8b, { 0xad, 0x37, 0x7f, 0x8c, 0x51, 0xfc, 0x62, 0x80 }}\r | |
20 | \r | |
21 | typedef struct _EFI_PEI_I2C_MASTER_PPI EFI_PEI_I2C_MASTER_PPI;\r | |
22 | \r | |
23 | /**\r | |
24 | Set the frequency for the I2C clock line.\r | |
9095d37b | 25 | \r |
4006b0b5 EL |
26 | @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.\r |
27 | @param BusClockHertz Pointer to the requested I2C bus clock frequency in Hertz.\r | |
9095d37b | 28 | Upon return this value contains the actual frequency\r |
4006b0b5 EL |
29 | in use by the I2C controller.\r |
30 | \r | |
31 | @retval EFI_SUCCESS The bus frequency was set successfully.\r | |
32 | @retval EFI_INVALID_PARAMETER BusClockHertz is NULL\r | |
33 | @retval EFI_UNSUPPORTED The controller does not support this frequency.\r | |
9095d37b | 34 | \r |
4006b0b5 EL |
35 | **/\r |
36 | typedef\r | |
37 | EFI_STATUS\r | |
38 | (EFIAPI *EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY) (\r | |
39 | IN EFI_PEI_I2C_MASTER_PPI *This,\r | |
40 | IN UINTN *BusClockHertz\r | |
41 | );\r | |
42 | \r | |
43 | /**\r | |
44 | Reset the I2C controller and configure it for use.\r | |
9095d37b | 45 | \r |
4006b0b5 EL |
46 | @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.\r |
47 | \r | |
48 | @retval EFI_SUCCESS The reset completed successfully.\r | |
49 | @retval EFI_DEVICE_ERROR The reset operation failed.\r | |
9095d37b | 50 | \r |
4006b0b5 EL |
51 | **/\r |
52 | typedef\r | |
53 | EFI_STATUS\r | |
54 | (EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET) (\r | |
55 | IN CONST EFI_PEI_I2C_MASTER_PPI *This\r | |
56 | );\r | |
57 | \r | |
58 | /**\r | |
59 | Start an I2C transaction on the host controller.\r | |
9095d37b | 60 | \r |
4006b0b5 EL |
61 | @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.\r |
62 | @param SlaveAddress Address of the device on the I2C bus.\r | |
9095d37b | 63 | Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses,\r |
4006b0b5 | 64 | clear this bit for 7-bit addressing.\r |
9095d37b | 65 | Bits 0-6 are used for 7-bit I2C slave addresses and\r |
4006b0b5 EL |
66 | bits 0-9 are used for 10-bit I2C slave addresses.\r |
67 | @param RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction.\r | |
68 | \r | |
9095d37b LG |
69 | @retval EFI_SUCCESS The transaction completed successfully.\r |
70 | @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too large.\r | |
71 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the transaction.\r | |
72 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
73 | @retval EFI_NO_RESPONSE The I2C device is not responding to the slave address.\r | |
4006b0b5 | 74 | EFI_DEVICE_ERROR will be returned if the controller cannot distinguish when the NACK occurred.\r |
9095d37b LG |
75 | @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter\r |
76 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction\r | |
77 | @retval EFI_UNSUPPORTED The controller does not support the requested transaction.\r | |
78 | \r | |
4006b0b5 EL |
79 | **/\r |
80 | typedef\r | |
81 | EFI_STATUS\r | |
82 | (EFIAPI *EFI_PEI_I2C_MASTER_PPI_START_REQUEST) (\r | |
83 | IN CONST EFI_PEI_I2C_MASTER_PPI *This,\r | |
84 | IN UINTN SlaveAddress,\r | |
85 | IN EFI_I2C_REQUEST_PACKET *RequestPacket\r | |
86 | );\r | |
87 | \r | |
88 | ///\r | |
89 | /// This PPI manipulates the I2C host controller to perform transactions as a master on the I2C bus\r | |
90 | /// using the current state of any switches or multiplexers in the I2C bus.\r | |
91 | ///\r | |
92 | struct _EFI_PEI_I2C_MASTER_PPI {\r | |
93 | EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency;\r | |
94 | EFI_PEI_I2C_MASTER_PPI_RESET Reset;\r | |
95 | EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest;\r | |
96 | CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r | |
97 | EFI_GUID Identifier;\r | |
98 | };\r | |
99 | \r | |
100 | extern EFI_GUID gEfiPeiI2cMasterPpiGuid;\r | |
101 | \r | |
102 | #endif\r |