]>
Commit | Line | Data |
---|---|---|
d1f95000 | 1 | /** @file\r |
4ca9b6c4 | 2 | CPU Architectural Protocol as defined in PI spec Volume 2 DXE\r |
d1f95000 | 3 | \r |
4 | This code abstracts the DXE core from processor implementation details.\r | |
5 | \r | |
b88df761 | 6 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
9df063a0 | 7 | This program and the accompanying materials \r |
d1f95000 | 8 | are licensed and made available under the terms and conditions of the BSD License \r |
9 | which accompanies this distribution. The full text of the license may be found at \r | |
10 | http://opensource.org/licenses/bsd-license.php \r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
14 | \r | |
d1f95000 | 15 | **/\r |
16 | \r | |
17 | #ifndef __ARCH_PROTOCOL_CPU_H__\r | |
18 | #define __ARCH_PROTOCOL_CPU_H__\r | |
19 | \r | |
20 | #include <Protocol/DebugSupport.h>\r | |
21 | \r | |
22 | #define EFI_CPU_ARCH_PROTOCOL_GUID \\r | |
23 | { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r | |
24 | \r | |
25 | typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r | |
26 | \r | |
9319d2c2 LG |
27 | ///\r |
28 | /// The type of flush operation\r | |
29 | ///\r | |
d1f95000 | 30 | typedef enum {\r |
31 | EfiCpuFlushTypeWriteBackInvalidate,\r | |
32 | EfiCpuFlushTypeWriteBack,\r | |
33 | EfiCpuFlushTypeInvalidate,\r | |
34 | EfiCpuMaxFlushType\r | |
35 | } EFI_CPU_FLUSH_TYPE;\r | |
36 | \r | |
9319d2c2 LG |
37 | ///\r |
38 | /// The type of processor INIT.\r | |
39 | ///\r | |
d1f95000 | 40 | typedef enum {\r |
41 | EfiCpuInit,\r | |
42 | EfiCpuMaxInitType\r | |
43 | } EFI_CPU_INIT_TYPE;\r | |
44 | \r | |
45 | /**\r | |
46 | EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r | |
47 | \r | |
48 | @param InterruptType Defines the type of interrupt or exception that\r | |
49 | occurred on the processor.This parameter is processor architecture specific.\r | |
50 | @param SystemContext A pointer to the processor context when\r | |
51 | the interrupt occurred on the processor.\r | |
52 | \r | |
53 | @return None\r | |
54 | \r | |
55 | **/\r | |
56 | typedef\r | |
57 | VOID\r | |
8b13229b | 58 | (EFIAPI *EFI_CPU_INTERRUPT_HANDLER)(\r |
d1f95000 | 59 | IN CONST EFI_EXCEPTION_TYPE InterruptType,\r |
60 | IN CONST EFI_SYSTEM_CONTEXT SystemContext\r | |
61 | );\r | |
62 | \r | |
63 | /**\r | |
64 | This function flushes the range of addresses from Start to Start+Length \r | |
65 | from the processor's data cache. If Start is not aligned to a cache line \r | |
66 | boundary, then the bytes before Start to the preceding cache line boundary \r | |
67 | are also flushed. If Start+Length is not aligned to a cache line boundary, \r | |
68 | then the bytes past Start+Length to the end of the next cache line boundary \r | |
69 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r | |
70 | supported. If the data cache is fully coherent with all DMA operations, then \r | |
71 | this function can just return EFI_SUCCESS. If the processor does not support \r | |
72 | flushing a range of the data cache, then the entire data cache can be flushed.\r | |
73 | \r | |
74 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
75 | @param Start The beginning physical address to flush from the processor's data\r | |
76 | cache.\r | |
77 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
78 | function may flush more bytes than Length specifies depending upon\r | |
79 | the granularity of the flush operation that the processor supports.\r | |
80 | @param FlushType Specifies the type of flush operation to perform.\r | |
81 | \r | |
82 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
83 | the processor's data cache.\r | |
b88df761 | 84 | @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r |
d1f95000 | 85 | by FlushType.\r |
86 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
87 | from the processor's data cache.\r | |
88 | \r | |
89 | **/\r | |
90 | typedef\r | |
91 | EFI_STATUS\r | |
8b13229b | 92 | (EFIAPI *EFI_CPU_FLUSH_DATA_CACHE)(\r |
d1f95000 | 93 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
94 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
95 | IN UINT64 Length,\r | |
96 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
97 | );\r | |
98 | \r | |
99 | \r | |
100 | /**\r | |
101 | This function enables interrupt processing by the processor. \r | |
102 | \r | |
103 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
104 | \r | |
105 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
106 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
107 | \r | |
108 | **/\r | |
109 | typedef\r | |
110 | EFI_STATUS\r | |
8b13229b | 111 | (EFIAPI *EFI_CPU_ENABLE_INTERRUPT)(\r |
d1f95000 | 112 | IN EFI_CPU_ARCH_PROTOCOL *This\r |
113 | );\r | |
114 | \r | |
115 | \r | |
116 | /**\r | |
117 | This function disables interrupt processing by the processor.\r | |
118 | \r | |
119 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
120 | \r | |
121 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
122 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
123 | \r | |
124 | **/\r | |
125 | typedef\r | |
126 | EFI_STATUS\r | |
8b13229b | 127 | (EFIAPI *EFI_CPU_DISABLE_INTERRUPT)(\r |
d1f95000 | 128 | IN EFI_CPU_ARCH_PROTOCOL *This\r |
129 | );\r | |
130 | \r | |
131 | \r | |
132 | /**\r | |
133 | This function retrieves the processor's current interrupt state a returns it in \r | |
134 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r | |
135 | are currently disabled, then FALSE is returned.\r | |
136 | \r | |
137 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
138 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
139 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
140 | \r | |
141 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
142 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
143 | \r | |
144 | **/\r | |
145 | typedef\r | |
146 | EFI_STATUS\r | |
8b13229b | 147 | (EFIAPI *EFI_CPU_GET_INTERRUPT_STATE)(\r |
d1f95000 | 148 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
149 | OUT BOOLEAN *State\r | |
150 | );\r | |
151 | \r | |
152 | \r | |
153 | /**\r | |
154 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
155 | processor will be reset, and control will not be returned to the caller. If InitType is \r | |
156 | not supported by this processor, or the processor cannot programmatically generate an \r | |
157 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r | |
158 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r | |
159 | \r | |
160 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
161 | @param InitType The type of processor INIT to perform.\r | |
162 | \r | |
163 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
164 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
165 | by this processor.\r | |
166 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
167 | \r | |
168 | **/\r | |
169 | typedef\r | |
170 | EFI_STATUS\r | |
8b13229b | 171 | (EFIAPI *EFI_CPU_INIT)(\r |
d1f95000 | 172 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
173 | IN EFI_CPU_INIT_TYPE InitType\r | |
174 | );\r | |
175 | \r | |
176 | \r | |
177 | /**\r | |
178 | This function registers and enables the handler specified by InterruptHandler for a processor \r | |
179 | interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r | |
180 | handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r | |
181 | The installed handler is called once for each processor interrupt or exception.\r | |
182 | \r | |
183 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
184 | @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r | |
185 | are enabled and FALSE if interrupts are disabled.\r | |
186 | @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r | |
187 | when a processor interrupt occurs. If this parameter is NULL, then the handler\r | |
188 | will be uninstalled.\r | |
189 | \r | |
190 | @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r | |
191 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r | |
192 | previously installed.\r | |
193 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r | |
194 | previously installed.\r | |
195 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r | |
196 | \r | |
197 | **/\r | |
198 | typedef\r | |
199 | EFI_STATUS\r | |
8b13229b | 200 | (EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER)(\r |
d1f95000 | 201 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
202 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
203 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
204 | );\r | |
205 | \r | |
206 | \r | |
207 | /**\r | |
208 | This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r | |
209 | \r | |
210 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
211 | @param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r | |
212 | must be between 0 and NumberOfTimers-1.\r | |
213 | @param TimerValue Pointer to the returned timer value.\r | |
214 | @param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r | |
f1004231 LG |
215 | of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is\r |
216 | returned. This parameter is optional and may be NULL.\r | |
d1f95000 | 217 | \r |
218 | @retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r | |
219 | @retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r | |
220 | @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r | |
221 | @retval EFI_UNSUPPORTED The processor does not have any readable timers.\r | |
222 | \r | |
223 | **/\r | |
224 | typedef\r | |
225 | EFI_STATUS\r | |
8b13229b | 226 | (EFIAPI *EFI_CPU_GET_TIMER_VALUE)(\r |
d1f95000 | 227 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
228 | IN UINT32 TimerIndex,\r | |
229 | OUT UINT64 *TimerValue,\r | |
230 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
231 | );\r | |
232 | \r | |
233 | \r | |
234 | /**\r | |
235 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
236 | Length from their current attributes to the attributes specified by Attributes.\r | |
237 | \r | |
238 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
239 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
240 | @param Length The size in bytes of the memory region.\r | |
241 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
242 | \r | |
243 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
244 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
245 | BaseAddress and Length cannot be modified.\r | |
246 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
4ec21e8b | 247 | Attributes specified an illegal combination of attributes that\r |
248 | cannot be set together.\r | |
d1f95000 | 249 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r |
250 | the memory resource range.\r | |
251 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
252 | resource range specified by BaseAddress and Length.\r | |
253 | The bit mask of attributes is not support for the memory resource\r | |
254 | range specified by BaseAddress and Length.\r | |
255 | \r | |
256 | **/\r | |
257 | typedef\r | |
258 | EFI_STATUS\r | |
8b13229b | 259 | (EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES)(\r |
d1f95000 | 260 | IN EFI_CPU_ARCH_PROTOCOL *This,\r |
261 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
262 | IN UINT64 Length,\r | |
263 | IN UINT64 Attributes\r | |
264 | );\r | |
265 | \r | |
266 | \r | |
44717a39 | 267 | ///\r |
268 | /// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r | |
269 | /// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r | |
270 | /// vectors and exception vectors, reading internal processor timers, resetting the processor, and\r | |
271 | /// determining the processor frequency.\r | |
272 | ///\r | |
d1f95000 | 273 | struct _EFI_CPU_ARCH_PROTOCOL {\r |
274 | EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r | |
275 | EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r | |
276 | EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r | |
277 | EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r | |
278 | EFI_CPU_INIT Init;\r | |
279 | EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r | |
280 | EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r | |
281 | EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r | |
8b6c989b | 282 | ///\r |
283 | /// The number of timers that are available in a processor. The value in this \r | |
284 | /// field is a constant that must not be modified after the CPU Architectural \r | |
285 | /// Protocol is installed. All consumers must treat this as a read-only field.\r | |
286 | ///\r | |
d1f95000 | 287 | UINT32 NumberOfTimers;\r |
8b6c989b | 288 | ///\r |
289 | /// The size, in bytes, of the alignment required for DMA buffer allocations. \r | |
290 | /// This is typically the size of the largest data cache line in the platform. \r | |
291 | /// The value in this field is a constant that must not be modified after the \r | |
292 | /// CPU Architectural Protocol is installed. All consumers must treat this as \r | |
293 | /// a read-only field. \r | |
294 | ///\r | |
d1f95000 | 295 | UINT32 DmaBufferAlignment;\r |
296 | };\r | |
297 | \r | |
298 | extern EFI_GUID gEfiCpuArchProtocolGuid;\r | |
299 | \r | |
300 | #endif\r |