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25a1f91d | 1 | /** @file\r |
2 | This files describes the CPU I/O 2 Protocol.\r | |
3 | \r | |
4 | This protocol provides an I/O abstraction for a system processor. This protocol\r | |
5 | is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.\r | |
6 | The I/O or memory primitives can be used by the consumer of the protocol to materialize\r | |
7 | bus-specific configuration cycles, such as the transitional configuration address and data\r | |
8 | ports for PCI. Only drivers that require direct access to the entire system should use this \r | |
9 | protocol. \r | |
10 | \r | |
11 | Note: This is a boot-services only protocol and it may not be used by runtime drivers after\r | |
12 | ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime\r | |
13 | protocol and can be used by runtime drivers after ExitBootServices().\r | |
14 | \r | |
80ae2a58 | 15 | Copyright (c) 2007 - 2010, Intel Corporation\r |
25a1f91d | 16 | All rights reserved. This program and the accompanying materials\r |
17 | are licensed and made available under the terms and conditions of the BSD License\r | |
18 | which accompanies this distribution. The full text of the license may be found at\r | |
19 | http://opensource.org/licenses/bsd-license.php\r | |
20 | \r | |
21 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
22 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
23 | \r | |
24 | @par Revision Reference:\r | |
25 | This Protocol is defined in UEFI Platform Initialization Specification 1.2 \r | |
26 | Volume 5: Standards\r | |
27 | \r | |
28 | **/\r | |
29 | \r | |
30 | #ifndef __CPU_IO2_H__\r | |
31 | #define __CPU_IO2_H__\r | |
32 | \r | |
25a1f91d | 33 | #define EFI_CPU_IO2_PROTOCOL_GUID \\r |
34 | { \\r | |
35 | 0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \\r | |
36 | }\r | |
37 | \r | |
38 | typedef struct _EFI_CPU_IO2_PROTOCOL EFI_CPU_IO2_PROTOCOL;\r | |
39 | \r | |
25a1f91d | 40 | ///\r |
41 | /// Enumeration that defines the width of the I/O operation.\r | |
42 | ///\r | |
43 | typedef enum {\r | |
44 | EfiCpuIoWidthUint8,\r | |
45 | EfiCpuIoWidthUint16,\r | |
46 | EfiCpuIoWidthUint32,\r | |
47 | EfiCpuIoWidthUint64,\r | |
48 | EfiCpuIoWidthFifoUint8,\r | |
49 | EfiCpuIoWidthFifoUint16,\r | |
50 | EfiCpuIoWidthFifoUint32,\r | |
51 | EfiCpuIoWidthFifoUint64,\r | |
52 | EfiCpuIoWidthFillUint8,\r | |
53 | EfiCpuIoWidthFillUint16,\r | |
54 | EfiCpuIoWidthFillUint32,\r | |
55 | EfiCpuIoWidthFillUint64,\r | |
56 | EfiCpuIoWidthMaximum\r | |
57 | } EFI_CPU_IO_PROTOCOL_WIDTH;\r | |
58 | \r | |
25a1f91d | 59 | /**\r |
60 | Enables a driver to access registers in the PI CPU I/O space. \r | |
61 | \r | |
0b70a697 | 62 | The Io.Read() and Io.Write() functions enable a driver to access PCI controller \r |
63 | registers in the PI CPU I/O space. \r | |
25a1f91d | 64 | \r |
0b70a697 | 65 | The I/O operations are carried out exactly as requested. The caller is responsible \r |
66 | for satisfying any alignment and I/O width restrictions that a PI System on a \r | |
67 | platform might require. For example on some platforms, width requests of \r | |
68 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r | |
69 | be handled by the driver.\r | |
25a1f91d | 70 | \r |
71 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r | |
0b70a697 | 72 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r |
73 | each of the Count operations that is performed.\r | |
25a1f91d | 74 | \r |
75 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r | |
76 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r | |
0b70a697 | 77 | incremented for each of the Count operations that is performed. The read or \r |
78 | write operation is performed Count times on the same Address.\r | |
25a1f91d | 79 | \r |
80 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r | |
81 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r | |
0b70a697 | 82 | incremented for each of the Count operations that is performed. The read or \r |
83 | write operation is performed Count times from the first element of Buffer.\r | |
25a1f91d | 84 | \r |
0b70a697 | 85 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r |
86 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
87 | @param[in] Address The base address of the I/O operation. \r | |
88 | @param[in] Count The number of I/O operations to perform. The number \r | |
89 | of bytes moved is Width size * Count, starting at Address.\r | |
90 | @param[in, out] Buffer For read operations, the destination buffer to store the results.\r | |
91 | For write operations, the source buffer from which to write data.\r | |
25a1f91d | 92 | \r |
0b70a697 | 93 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r |
94 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
95 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
96 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
97 | @retval EFI_UNSUPPORTED The address range specified by Address, Width, \r | |
98 | and Count is not valid for this PI system.\r | |
25a1f91d | 99 | \r |
100 | **/\r | |
101 | typedef\r | |
102 | EFI_STATUS\r | |
103 | (EFIAPI *EFI_CPU_IO_PROTOCOL_IO_MEM)(\r | |
104 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
105 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
106 | IN UINT64 Address,\r | |
107 | IN UINTN Count,\r | |
108 | IN OUT VOID *Buffer\r | |
109 | );\r | |
110 | \r | |
25a1f91d | 111 | ///\r |
112 | /// Service for read and write accesses.\r | |
113 | ///\r | |
114 | typedef struct {\r | |
115 | ///\r | |
116 | /// This service provides the various modalities of memory and I/O read.\r | |
117 | ///\r | |
118 | EFI_CPU_IO_PROTOCOL_IO_MEM Read;\r | |
119 | ///\r | |
120 | /// This service provides the various modalities of memory and I/O write.\r | |
121 | ///\r | |
122 | EFI_CPU_IO_PROTOCOL_IO_MEM Write;\r | |
123 | } EFI_CPU_IO_PROTOCOL_ACCESS;\r | |
124 | \r | |
25a1f91d | 125 | ///\r |
126 | /// Provides the basic memory and I/O interfaces that are used to abstract\r | |
127 | /// accesses to devices in a system.\r | |
128 | ///\r | |
129 | struct _EFI_CPU_IO2_PROTOCOL {\r | |
130 | ///\r | |
131 | /// Enables a driver to access memory-mapped registers in the EFI system memory space.\r | |
132 | ///\r | |
133 | EFI_CPU_IO_PROTOCOL_ACCESS Mem;\r | |
134 | ///\r | |
135 | /// Enables a driver to access registers in the EFI CPU I/O space.\r | |
136 | ///\r | |
137 | EFI_CPU_IO_PROTOCOL_ACCESS Io;\r | |
138 | };\r | |
139 | \r | |
140 | extern EFI_GUID gEfiCpuIo2ProtocolGuid;\r | |
141 | \r | |
142 | #endif\r |