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d1f95000 | 1 | /** @file\r |
9095d37b | 2 | EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,\r |
4ca9b6c4 | 3 | and DMA interfaces that a driver uses to access its PCI controller.\r |
d1f95000 | 4 | \r |
9095d37b | 5 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
d1f95000 | 7 | \r |
d1f95000 | 8 | **/\r |
9 | \r | |
10 | #ifndef __PCI_IO_H__\r | |
11 | #define __PCI_IO_H__\r | |
12 | \r | |
99e8ed21 | 13 | ///\r |
14 | /// Global ID for the PCI I/O Protocol\r | |
15 | ///\r | |
d1f95000 | 16 | #define EFI_PCI_IO_PROTOCOL_GUID \\r |
17 | { \\r | |
18 | 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r | |
19 | }\r | |
20 | \r | |
21 | typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r | |
22 | \r | |
99e8ed21 | 23 | ///\r |
9319d2c2 LG |
24 | /// *******************************************************\r |
25 | /// EFI_PCI_IO_PROTOCOL_WIDTH\r | |
26 | /// *******************************************************\r | |
99e8ed21 | 27 | ///\r |
d1f95000 | 28 | typedef enum {\r |
29 | EfiPciIoWidthUint8 = 0,\r | |
30 | EfiPciIoWidthUint16,\r | |
31 | EfiPciIoWidthUint32,\r | |
32 | EfiPciIoWidthUint64,\r | |
33 | EfiPciIoWidthFifoUint8,\r | |
34 | EfiPciIoWidthFifoUint16,\r | |
35 | EfiPciIoWidthFifoUint32,\r | |
36 | EfiPciIoWidthFifoUint64,\r | |
37 | EfiPciIoWidthFillUint8,\r | |
38 | EfiPciIoWidthFillUint16,\r | |
39 | EfiPciIoWidthFillUint32,\r | |
40 | EfiPciIoWidthFillUint64,\r | |
41 | EfiPciIoWidthMaximum\r | |
42 | } EFI_PCI_IO_PROTOCOL_WIDTH;\r | |
43 | \r | |
44 | //\r | |
45 | // Complete PCI address generater\r | |
46 | //\r | |
cce6f7aa | 47 | #define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r |
48 | #define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r | |
49 | #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r | |
50 | #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r | |
51 | #define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r | |
52 | #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r | |
53 | #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r | |
54 | #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r | |
55 | #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r | |
630b4187 | 56 | #define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r |
cce6f7aa | 57 | #define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r |
58 | #define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r | |
59 | #define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r | |
60 | #define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r | |
61 | #define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r | |
62 | #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r | |
63 | #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r | |
64 | #define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r | |
65 | #define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r | |
66 | #define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r | |
e0ee9d93 | 67 | #define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r |
d1f95000 | 68 | \r |
69 | #define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r | |
70 | #define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r | |
71 | \r | |
99e8ed21 | 72 | ///\r |
73 | /// *******************************************************\r | |
74 | /// EFI_PCI_IO_PROTOCOL_OPERATION\r | |
75 | /// *******************************************************\r | |
76 | ///\r | |
d1f95000 | 77 | typedef enum {\r |
992f22b9 LG |
78 | ///\r |
79 | /// A read operation from system memory by a bus master.\r | |
80 | ///\r | |
d1f95000 | 81 | EfiPciIoOperationBusMasterRead,\r |
992f22b9 LG |
82 | ///\r |
83 | /// A write operation from system memory by a bus master.\r | |
84 | ///\r | |
d1f95000 | 85 | EfiPciIoOperationBusMasterWrite,\r |
992f22b9 LG |
86 | ///\r |
87 | /// Provides both read and write access to system memory by both the processor and a\r | |
1bf79370 | 88 | /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r |
992f22b9 | 89 | ///\r |
d1f95000 | 90 | EfiPciIoOperationBusMasterCommonBuffer,\r |
91 | EfiPciIoOperationMaximum\r | |
92 | } EFI_PCI_IO_PROTOCOL_OPERATION;\r | |
93 | \r | |
99e8ed21 | 94 | ///\r |
95 | /// *******************************************************\r | |
96 | /// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r | |
97 | /// *******************************************************\r | |
98 | ///\r | |
d1f95000 | 99 | typedef enum {\r |
992f22b9 | 100 | ///\r |
1bf79370 | 101 | /// Retrieve the PCI controller's current attributes, and return them in Result.\r |
992f22b9 | 102 | ///\r |
d1f95000 | 103 | EfiPciIoAttributeOperationGet,\r |
992f22b9 | 104 | ///\r |
1bf79370 | 105 | /// Set the PCI controller's current attributes to Attributes.\r |
992f22b9 | 106 | ///\r |
d1f95000 | 107 | EfiPciIoAttributeOperationSet,\r |
992f22b9 LG |
108 | ///\r |
109 | /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.\r | |
110 | ///\r | |
d1f95000 | 111 | EfiPciIoAttributeOperationEnable,\r |
992f22b9 LG |
112 | ///\r |
113 | /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.\r | |
114 | ///\r | |
d1f95000 | 115 | EfiPciIoAttributeOperationDisable,\r |
992f22b9 LG |
116 | ///\r |
117 | /// Retrieve the PCI controller's supported attributes, and return them in Result.\r | |
118 | ///\r | |
d1f95000 | 119 | EfiPciIoAttributeOperationSupported,\r |
120 | EfiPciIoAttributeOperationMaximum\r | |
121 | } EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r | |
122 | \r | |
9095d37b | 123 | /**\r |
630b4187 | 124 | Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r |
9095d37b LG |
125 | satisfied or after a defined duration.\r |
126 | \r | |
d1f95000 | 127 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
128 | @param Width Signifies the width of the memory or I/O operations.\r | |
129 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
9095d37b | 130 | base address for the memory operation to perform.\r |
d1f95000 | 131 | @param Offset The offset within the selected BAR to start the memory operation.\r |
132 | @param Mask Mask used for the polling criteria.\r | |
133 | @param Value The comparison value used for the polling exit criteria.\r | |
134 | @param Delay The number of 100 ns units to poll.\r | |
135 | @param Result Pointer to the last value read from the memory location.\r | |
9095d37b | 136 | \r |
d1f95000 | 137 | @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r |
138 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
139 | @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r | |
140 | @retval EFI_TIMEOUT Delay expired before a match occurred.\r | |
141 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
142 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
9095d37b | 143 | \r |
d1f95000 | 144 | **/\r |
145 | typedef\r | |
146 | EFI_STATUS\r | |
8b13229b | 147 | (EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)(\r |
d1f95000 | 148 | IN EFI_PCI_IO_PROTOCOL *This,\r |
149 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
150 | IN UINT8 BarIndex,\r | |
151 | IN UINT64 Offset,\r | |
152 | IN UINT64 Mask,\r | |
153 | IN UINT64 Value,\r | |
154 | IN UINT64 Delay,\r | |
155 | OUT UINT64 *Result\r | |
156 | );\r | |
157 | \r | |
9095d37b | 158 | /**\r |
d1f95000 | 159 | Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r |
9095d37b | 160 | \r |
d1f95000 | 161 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
162 | @param Width Signifies the width of the memory or I/O operations.\r | |
163 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r | |
9095d37b LG |
164 | base address for the memory or I/O operation to perform.\r |
165 | @param Offset The offset within the selected BAR to start the memory or I/O operation.\r | |
d1f95000 | 166 | @param Count The number of memory or I/O operations to perform.\r |
167 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
9095d37b LG |
168 | operations, the source buffer to write data from.\r |
169 | \r | |
d1f95000 | 170 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
171 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
172 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
9095d37b | 173 | valid for the PCI BAR specified by BarIndex.\r |
d1f95000 | 174 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
175 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
9095d37b | 176 | \r |
d1f95000 | 177 | **/\r |
178 | typedef\r | |
179 | EFI_STATUS\r | |
8b13229b | 180 | (EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)(\r |
d1f95000 | 181 | IN EFI_PCI_IO_PROTOCOL *This,\r |
182 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
183 | IN UINT8 BarIndex,\r | |
184 | IN UINT64 Offset,\r | |
185 | IN UINTN Count,\r | |
186 | IN OUT VOID *Buffer\r | |
187 | );\r | |
188 | \r | |
189 | typedef struct {\r | |
992f22b9 LG |
190 | ///\r |
191 | /// Read PCI controller registers in the PCI memory or I/O space.\r | |
192 | ///\r | |
d1f95000 | 193 | EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r |
992f22b9 LG |
194 | ///\r |
195 | /// Write PCI controller registers in the PCI memory or I/O space.\r | |
196 | ///\r | |
d1f95000 | 197 | EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r |
198 | } EFI_PCI_IO_PROTOCOL_ACCESS;\r | |
199 | \r | |
9095d37b | 200 | /**\r |
d1f95000 | 201 | Enable a PCI driver to access PCI controller registers in PCI configuration space.\r |
9095d37b LG |
202 | \r |
203 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
d1f95000 | 204 | @param Width Signifies the width of the memory operations.\r |
205 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
206 | @param Count The number of PCI configuration operations to perform.\r | |
207 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
208 | operations, the source buffer to write data from.\r | |
9095d37b LG |
209 | \r |
210 | \r | |
d1f95000 | 211 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
212 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
213 | valid for the PCI configuration header of the PCI controller.\r | |
9095d37b LG |
214 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r |
215 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
216 | \r | |
d1f95000 | 217 | **/\r |
218 | typedef\r | |
219 | EFI_STATUS\r | |
8b13229b | 220 | (EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)(\r |
d1f95000 | 221 | IN EFI_PCI_IO_PROTOCOL *This,\r |
222 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
223 | IN UINT32 Offset,\r | |
224 | IN UINTN Count,\r | |
225 | IN OUT VOID *Buffer\r | |
226 | );\r | |
227 | \r | |
228 | typedef struct {\r | |
992f22b9 LG |
229 | ///\r |
230 | /// Read PCI controller registers in PCI configuration space.\r | |
231 | ///\r | |
d1f95000 | 232 | EFI_PCI_IO_PROTOCOL_CONFIG Read;\r |
992f22b9 LG |
233 | ///\r |
234 | /// Write PCI controller registers in PCI configuration space.\r | |
235 | ///\r | |
d1f95000 | 236 | EFI_PCI_IO_PROTOCOL_CONFIG Write;\r |
237 | } EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r | |
238 | \r | |
9095d37b | 239 | /**\r |
d1f95000 | 240 | Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r |
241 | memory space.\r | |
9095d37b | 242 | \r |
d1f95000 | 243 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
244 | @param Width Signifies the width of the memory operations.\r | |
245 | @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r | |
9095d37b | 246 | base address for the memory operation to perform.\r |
d1f95000 | 247 | @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r |
9095d37b | 248 | start the memory writes for the copy operation.\r |
d1f95000 | 249 | @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r |
9095d37b | 250 | base address for the memory operation to perform.\r |
d1f95000 | 251 | @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r |
9095d37b | 252 | the memory reads for the copy operation.\r |
d1f95000 | 253 | @param Count The number of memory operations to perform. Bytes moved is Width\r |
9095d37b LG |
254 | size * Count, starting at DestOffset and SrcOffset.\r |
255 | \r | |
d1f95000 | 256 | @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r |
257 | @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r | |
258 | @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r | |
259 | @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r | |
9095d37b | 260 | is not valid for the PCI BAR specified by DestBarIndex.\r |
d1f95000 | 261 | @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r |
9095d37b | 262 | not valid for the PCI BAR specified by SrcBarIndex.\r |
d1f95000 | 263 | @retval EFI_INVALID_PARAMETER Width is invalid.\r |
264 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
9095d37b | 265 | \r |
d1f95000 | 266 | **/\r |
267 | typedef\r | |
268 | EFI_STATUS\r | |
8b13229b | 269 | (EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)(\r |
d1f95000 | 270 | IN EFI_PCI_IO_PROTOCOL *This,\r |
271 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
272 | IN UINT8 DestBarIndex,\r | |
273 | IN UINT64 DestOffset,\r | |
274 | IN UINT8 SrcBarIndex,\r | |
275 | IN UINT64 SrcOffset,\r | |
276 | IN UINTN Count\r | |
277 | );\r | |
278 | \r | |
9095d37b | 279 | /**\r |
630b4187 | 280 | Provides the PCI controller-specific addresses needed to access system memory.\r |
9095d37b | 281 | \r |
d1f95000 | 282 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
283 | @param Operation Indicates if the bus master is going to read or write to system memory.\r | |
284 | @param HostAddress The system memory address to map to the PCI controller.\r | |
285 | @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r | |
9095d37b | 286 | that were mapped.\r |
d1f95000 | 287 | @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r |
9095d37b | 288 | access the hosts HostAddress.\r |
d1f95000 | 289 | @param Mapping A resulting value to pass to Unmap().\r |
9095d37b | 290 | \r |
d1f95000 | 291 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r |
9095d37b | 292 | @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r |
d1f95000 | 293 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
294 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
295 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r | |
9095d37b | 296 | \r |
d1f95000 | 297 | **/\r |
298 | typedef\r | |
299 | EFI_STATUS\r | |
8b13229b | 300 | (EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)(\r |
d1f95000 | 301 | IN EFI_PCI_IO_PROTOCOL *This,\r |
302 | IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r | |
303 | IN VOID *HostAddress,\r | |
304 | IN OUT UINTN *NumberOfBytes,\r | |
305 | OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r | |
306 | OUT VOID **Mapping\r | |
307 | );\r | |
308 | \r | |
9095d37b | 309 | /**\r |
d1f95000 | 310 | Completes the Map() operation and releases any corresponding resources.\r |
9095d37b LG |
311 | \r |
312 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
d1f95000 | 313 | @param Mapping The mapping value returned from Map().\r |
9095d37b | 314 | \r |
d1f95000 | 315 | @retval EFI_SUCCESS The range was unmapped.\r |
316 | @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r | |
9095d37b | 317 | \r |
d1f95000 | 318 | **/\r |
319 | typedef\r | |
320 | EFI_STATUS\r | |
8b13229b | 321 | (EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)(\r |
d1f95000 | 322 | IN EFI_PCI_IO_PROTOCOL *This,\r |
323 | IN VOID *Mapping\r | |
324 | );\r | |
325 | \r | |
9095d37b | 326 | /**\r |
d1f95000 | 327 | Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r |
595ba42d | 328 | or EfiPciOperationBusMasterCommonBuffer64 mapping.\r |
9095d37b | 329 | \r |
d1f95000 | 330 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r |
331 | @param Type This parameter is not used and must be ignored.\r | |
332 | @param MemoryType The type of memory to allocate, EfiBootServicesData or\r | |
9095d37b LG |
333 | EfiRuntimeServicesData.\r |
334 | @param Pages The number of pages to allocate.\r | |
d1f95000 | 335 | @param HostAddress A pointer to store the base system memory address of the\r |
9095d37b | 336 | allocated range.\r |
d1f95000 | 337 | @param Attributes The requested bit mask of attributes for the allocated range.\r |
9095d37b | 338 | \r |
d1f95000 | 339 | @retval EFI_SUCCESS The requested memory pages were allocated.\r |
340 | @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r | |
595ba42d | 341 | MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r |
d1f95000 | 342 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
9095d37b LG |
343 | @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r |
344 | \r | |
d1f95000 | 345 | **/\r |
346 | typedef\r | |
347 | EFI_STATUS\r | |
8b13229b | 348 | (EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)(\r |
d1f95000 | 349 | IN EFI_PCI_IO_PROTOCOL *This,\r |
350 | IN EFI_ALLOCATE_TYPE Type,\r | |
351 | IN EFI_MEMORY_TYPE MemoryType,\r | |
352 | IN UINTN Pages,\r | |
353 | OUT VOID **HostAddress,\r | |
354 | IN UINT64 Attributes\r | |
355 | );\r | |
356 | \r | |
9095d37b | 357 | /**\r |
d1f95000 | 358 | Frees memory that was allocated with AllocateBuffer().\r |
9095d37b LG |
359 | \r |
360 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
361 | @param Pages The number of pages to free.\r | |
362 | @param HostAddress The base system memory address of the allocated range.\r | |
363 | \r | |
d1f95000 | 364 | @retval EFI_SUCCESS The requested memory pages were freed.\r |
365 | @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r | |
366 | was not allocated with AllocateBuffer().\r | |
9095d37b | 367 | \r |
d1f95000 | 368 | **/\r |
369 | typedef\r | |
370 | EFI_STATUS\r | |
8b13229b | 371 | (EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)(\r |
d1f95000 | 372 | IN EFI_PCI_IO_PROTOCOL *This,\r |
373 | IN UINTN Pages,\r | |
374 | IN VOID *HostAddress\r | |
375 | );\r | |
376 | \r | |
9095d37b | 377 | /**\r |
d1f95000 | 378 | Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r |
9095d37b LG |
379 | \r |
380 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
381 | \r | |
d1f95000 | 382 | @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r |
9095d37b | 383 | bridge to system memory.\r |
d1f95000 | 384 | @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r |
9095d37b LG |
385 | host bridge due to a hardware error.\r |
386 | \r | |
d1f95000 | 387 | **/\r |
388 | typedef\r | |
389 | EFI_STATUS\r | |
8b13229b | 390 | (EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)(\r |
d1f95000 | 391 | IN EFI_PCI_IO_PROTOCOL *This\r |
392 | );\r | |
393 | \r | |
9095d37b | 394 | /**\r |
d1f95000 | 395 | Retrieves this PCI controller's current PCI bus number, device number, and function number.\r |
9095d37b LG |
396 | \r |
397 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
d1f95000 | 398 | @param SegmentNumber The PCI controller's current PCI segment number.\r |
399 | @param BusNumber The PCI controller's current PCI bus number.\r | |
400 | @param DeviceNumber The PCI controller's current PCI device number.\r | |
401 | @param FunctionNumber The PCI controller's current PCI function number.\r | |
9095d37b LG |
402 | \r |
403 | @retval EFI_SUCCESS The PCI controller location was returned.\r | |
404 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
405 | \r | |
d1f95000 | 406 | **/\r |
407 | typedef\r | |
408 | EFI_STATUS\r | |
8b13229b | 409 | (EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)(\r |
d1f95000 | 410 | IN EFI_PCI_IO_PROTOCOL *This,\r |
411 | OUT UINTN *SegmentNumber,\r | |
412 | OUT UINTN *BusNumber,\r | |
413 | OUT UINTN *DeviceNumber,\r | |
414 | OUT UINTN *FunctionNumber\r | |
415 | );\r | |
416 | \r | |
9095d37b | 417 | /**\r |
d1f95000 | 418 | Performs an operation on the attributes that this PCI controller supports. The operations include\r |
9095d37b LG |
419 | getting the set of supported attributes, retrieving the current attributes, setting the current\r |
420 | attributes, enabling attributes, and disabling attributes.\r | |
421 | \r | |
422 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
d1f95000 | 423 | @param Operation The operation to perform on the attributes for this PCI controller.\r |
424 | @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r | |
9095d37b | 425 | operations.\r |
d1f95000 | 426 | @param Result A pointer to the result mask of attributes that are returned for the Get\r |
9095d37b LG |
427 | and Supported operations.\r |
428 | \r | |
d1f95000 | 429 | @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r |
9095d37b LG |
430 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r |
431 | @retval EFI_UNSUPPORTED one or more of the bits set in\r | |
d1f95000 | 432 | Attributes are not supported by this PCI controller or one of\r |
433 | its parent bridges when Operation is Set, Enable or Disable.\r | |
9095d37b | 434 | \r |
d1f95000 | 435 | **/\r |
436 | typedef\r | |
437 | EFI_STATUS\r | |
8b13229b | 438 | (EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)(\r |
d1f95000 | 439 | IN EFI_PCI_IO_PROTOCOL *This,\r |
440 | IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r | |
441 | IN UINT64 Attributes,\r | |
442 | OUT UINT64 *Result OPTIONAL\r | |
443 | );\r | |
444 | \r | |
51312091 | 445 | /**\r |
d1f95000 | 446 | Gets the attributes that this PCI controller supports setting on a BAR using\r |
447 | SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r | |
51312091 DB |
448 | \r |
449 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
d1f95000 | 450 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
451 | base address for resource range. The legal range for this field is 0..5.\r | |
452 | @param Supports A pointer to the mask of attributes that this PCI controller supports\r | |
51312091 DB |
453 | setting for this BAR with SetBarAttributes().\r |
454 | @param Resources A pointer to the resource descriptors that describe the current\r | |
455 | configuration of this BAR of the PCI controller.\r | |
9095d37b | 456 | \r |
51312091 DB |
457 | @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r |
458 | controller supports are returned in Supports. If Resources\r | |
459 | is not NULL, then the resource descriptors that the PCI\r | |
460 | controller is currently using are returned in Resources.\r | |
d1f95000 | 461 | @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r |
462 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
463 | @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r | |
51312091 | 464 | Resources.\r |
d1f95000 | 465 | **/\r |
466 | typedef\r | |
467 | EFI_STATUS\r | |
8b13229b | 468 | (EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(\r |
d1f95000 | 469 | IN EFI_PCI_IO_PROTOCOL *This,\r |
470 | IN UINT8 BarIndex,\r | |
471 | OUT UINT64 *Supports, OPTIONAL\r | |
472 | OUT VOID **Resources OPTIONAL\r | |
473 | );\r | |
474 | \r | |
9095d37b | 475 | /**\r |
d1f95000 | 476 | Sets the attributes for a range of a BAR on a PCI controller.\r |
9095d37b LG |
477 | \r |
478 | @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
d1f95000 | 479 | @param Attributes The mask of attributes to set for the resource range specified by\r |
9095d37b | 480 | BarIndex, Offset, and Length.\r |
d1f95000 | 481 | @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r |
482 | base address for resource range. The legal range for this field is 0..5.\r | |
483 | @param Offset A pointer to the BAR relative base address of the resource range to be\r | |
9095d37b | 484 | modified by the attributes specified by Attributes.\r |
d1f95000 | 485 | @param Length A pointer to the length of the resource range to be modified by the\r |
9095d37b LG |
486 | attributes specified by Attributes.\r |
487 | \r | |
488 | @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r | |
489 | range specified by BarIndex, Offset, and Length were\r | |
d1f95000 | 490 | set on the PCI controller, and the actual resource range is returned\r |
9095d37b | 491 | in Offset and Length.\r |
d1f95000 | 492 | @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r |
493 | @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r | |
494 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r | |
9095d37b LG |
495 | resource range specified by BarIndex, Offset, and\r |
496 | Length.\r | |
497 | \r | |
d1f95000 | 498 | **/\r |
499 | typedef\r | |
500 | EFI_STATUS\r | |
8b13229b | 501 | (EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)(\r |
d1f95000 | 502 | IN EFI_PCI_IO_PROTOCOL *This,\r |
503 | IN UINT64 Attributes,\r | |
504 | IN UINT8 BarIndex,\r | |
505 | IN OUT UINT64 *Offset,\r | |
506 | IN OUT UINT64 *Length\r | |
507 | );\r | |
508 | \r | |
44717a39 | 509 | ///\r |
9095d37b LG |
510 | /// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,\r |
511 | /// and DMA interfaces used to abstract accesses to PCI controllers.\r | |
512 | /// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.\r | |
513 | /// A device driver that wishes to manage a PCI controller in a system will have to\r | |
514 | /// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.\r | |
44717a39 | 515 | ///\r |
d1f95000 | 516 | struct _EFI_PCI_IO_PROTOCOL {\r |
517 | EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r | |
518 | EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r | |
519 | EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r | |
520 | EFI_PCI_IO_PROTOCOL_ACCESS Io;\r | |
521 | EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r | |
522 | EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r | |
523 | EFI_PCI_IO_PROTOCOL_MAP Map;\r | |
524 | EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r | |
525 | EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r | |
526 | EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r | |
527 | EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r | |
528 | EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r | |
529 | EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r | |
530 | EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r | |
531 | EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r | |
9095d37b | 532 | \r |
cce6f7aa | 533 | ///\r |
534 | /// The size, in bytes, of the ROM image.\r | |
535 | ///\r | |
d1f95000 | 536 | UINT64 RomSize;\r |
cce6f7aa | 537 | \r |
538 | ///\r | |
9095d37b LG |
539 | /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible\r |
540 | /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.\r | |
541 | /// The contents of this buffer are either from the PCI option ROM that can be accessed\r | |
542 | /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.\r | |
543 | /// The Attributes() function can be used to determine from which of these two sources\r | |
cce6f7aa | 544 | /// the RomImage buffer was initialized.\r |
9095d37b | 545 | ///\r |
d1f95000 | 546 | VOID *RomImage;\r |
547 | };\r | |
548 | \r | |
549 | extern EFI_GUID gEfiPciIoProtocolGuid;\r | |
550 | \r | |
551 | #endif\r |