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1 | /** @file\r |
2 | CPUID leaf definitions.\r | |
3 | \r | |
4 | Provides defines for CPUID leaf indexes. Data structures are provided for\r | |
5 | registers returned by a CPUID leaf that contain one or more bit fields.\r | |
6 | If a register returned is a single 32-bit value, then a data structure is\r | |
7 | not provided for that register.\r | |
8 | \r | |
9 | Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r | |
890d2bd2 | 10 | \r |
0acd8697 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
b15cbd9c BS |
12 | \r |
13 | @par Specification Reference:\r | |
788421d5 | 14 | AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34\r |
b15cbd9c BS |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __AMD_CPUID_H__\r | |
19 | #define __AMD_CPUID_H__\r | |
20 | \r | |
21 | /**\r | |
890d2bd2 LD |
22 | CPUID Signature Information\r |
23 | \r | |
24 | @param EAX CPUID_SIGNATURE (0x00)\r | |
25 | \r | |
26 | @retval EAX Returns the highest value the CPUID instruction recognizes for\r | |
27 | returning basic processor information. The value is returned is\r | |
28 | processor specific.\r | |
29 | @retval EBX First 4 characters of a vendor identification string.\r | |
30 | @retval ECX Last 4 characters of a vendor identification string.\r | |
31 | @retval EDX Middle 4 characters of a vendor identification string.\r | |
32 | \r | |
33 | **/\r | |
34 | \r | |
35 | ///\r | |
36 | /// @{ CPUID signature values returned by AMD processors\r | |
37 | ///\r | |
38 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')\r | |
39 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')\r | |
40 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')\r | |
41 | ///\r | |
42 | /// @}\r | |
43 | ///\r | |
44 | \r | |
890d2bd2 LD |
45 | /**\r |
46 | CPUID Extended Processor Signature and Features\r | |
47 | \r | |
48 | @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r | |
49 | \r | |
50 | @retval EAX Extended Family, Model, Stepping Identifiers\r | |
51 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.\r | |
52 | @retval EBX Brand Identifier\r | |
53 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.\r | |
54 | @retval ECX Extended Feature Identifiers\r | |
55 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.\r | |
56 | @retval EDX Extended Feature Identifiers\r | |
57 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.\r | |
58 | **/\r | |
59 | \r | |
60 | /**\r | |
61 | CPUID Extended Processor Signature and Features EAX for CPUID leaf\r | |
62 | #CPUID_EXTENDED_CPU_SIG.\r | |
63 | **/\r | |
64 | typedef union {\r | |
65 | ///\r | |
66 | /// Individual bit fields\r | |
67 | ///\r | |
68 | struct {\r | |
69 | ///\r | |
70 | /// [Bits 3:0] Stepping.\r | |
71 | ///\r | |
2f88bd3a | 72 | UINT32 Stepping : 4;\r |
890d2bd2 LD |
73 | ///\r |
74 | /// [Bits 7:4] Base Model.\r | |
75 | ///\r | |
2f88bd3a | 76 | UINT32 BaseModel : 4;\r |
890d2bd2 LD |
77 | ///\r |
78 | /// [Bits 11:8] Base Family.\r | |
79 | ///\r | |
2f88bd3a | 80 | UINT32 BaseFamily : 4;\r |
890d2bd2 LD |
81 | ///\r |
82 | /// [Bit 15:12] Reserved.\r | |
83 | ///\r | |
2f88bd3a | 84 | UINT32 Reserved1 : 4;\r |
890d2bd2 LD |
85 | ///\r |
86 | /// [Bits 19:16] Extended Model.\r | |
87 | ///\r | |
2f88bd3a | 88 | UINT32 ExtModel : 4;\r |
890d2bd2 LD |
89 | ///\r |
90 | /// [Bits 27:20] Extended Family.\r | |
91 | ///\r | |
2f88bd3a | 92 | UINT32 ExtFamily : 8;\r |
890d2bd2 LD |
93 | ///\r |
94 | /// [Bit 31:28] Reserved.\r | |
95 | ///\r | |
2f88bd3a | 96 | UINT32 Reserved2 : 4;\r |
890d2bd2 LD |
97 | } Bits;\r |
98 | ///\r | |
99 | /// All bit fields as a 32-bit value\r | |
100 | ///\r | |
2f88bd3a | 101 | UINT32 Uint32;\r |
890d2bd2 LD |
102 | } CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r |
103 | \r | |
104 | /**\r | |
105 | CPUID Extended Processor Signature and Features EBX for CPUID leaf\r | |
106 | #CPUID_EXTENDED_CPU_SIG.\r | |
107 | **/\r | |
108 | typedef union {\r | |
109 | ///\r | |
110 | /// Individual bit fields\r | |
111 | ///\r | |
112 | struct {\r | |
113 | ///\r | |
114 | /// [Bits 27:0] Reserved.\r | |
115 | ///\r | |
2f88bd3a | 116 | UINT32 Reserved : 28;\r |
890d2bd2 LD |
117 | ///\r |
118 | /// [Bit 31:28] Package Type.\r | |
119 | ///\r | |
2f88bd3a | 120 | UINT32 PkgType : 4;\r |
890d2bd2 LD |
121 | } Bits;\r |
122 | ///\r | |
123 | /// All bit fields as a 32-bit value\r | |
124 | ///\r | |
2f88bd3a | 125 | UINT32 Uint32;\r |
890d2bd2 LD |
126 | } CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r |
127 | \r | |
128 | /**\r | |
129 | CPUID Extended Processor Signature and Features ECX for CPUID leaf\r | |
130 | #CPUID_EXTENDED_CPU_SIG.\r | |
131 | **/\r | |
132 | typedef union {\r | |
133 | ///\r | |
134 | /// Individual bit fields\r | |
135 | ///\r | |
136 | struct {\r | |
137 | ///\r | |
138 | /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r | |
139 | ///\r | |
2f88bd3a | 140 | UINT32 LAHF_SAHF : 1;\r |
890d2bd2 LD |
141 | ///\r |
142 | /// [Bit 1] Core multi-processing legacy mode.\r | |
143 | ///\r | |
2f88bd3a | 144 | UINT32 CmpLegacy : 1;\r |
890d2bd2 LD |
145 | ///\r |
146 | /// [Bit 2] Secure Virtual Mode feature.\r | |
147 | ///\r | |
2f88bd3a | 148 | UINT32 SVM : 1;\r |
890d2bd2 LD |
149 | ///\r |
150 | /// [Bit 3] Extended APIC register space.\r | |
151 | ///\r | |
2f88bd3a | 152 | UINT32 ExtApicSpace : 1;\r |
890d2bd2 LD |
153 | ///\r |
154 | /// [Bit 4] LOCK MOV CR0 means MOV CR8.\r | |
155 | ///\r | |
2f88bd3a | 156 | UINT32 AltMovCr8 : 1;\r |
890d2bd2 LD |
157 | ///\r |
158 | /// [Bit 5] LZCNT instruction support.\r | |
159 | ///\r | |
2f88bd3a | 160 | UINT32 LZCNT : 1;\r |
890d2bd2 LD |
161 | ///\r |
162 | /// [Bit 6] SSE4A instruction support.\r | |
163 | ///\r | |
2f88bd3a | 164 | UINT32 SSE4A : 1;\r |
890d2bd2 LD |
165 | ///\r |
166 | /// [Bit 7] Misaligned SSE Mode.\r | |
167 | ///\r | |
2f88bd3a | 168 | UINT32 MisAlignSse : 1;\r |
890d2bd2 LD |
169 | ///\r |
170 | /// [Bit 8] ThreeDNow Prefetch instructions.\r | |
171 | ///\r | |
2f88bd3a | 172 | UINT32 PREFETCHW : 1;\r |
890d2bd2 LD |
173 | ///\r |
174 | /// [Bit 9] OS Visible Work-around support.\r | |
175 | ///\r | |
2f88bd3a | 176 | UINT32 OSVW : 1;\r |
890d2bd2 LD |
177 | ///\r |
178 | /// [Bit 10] Instruction Based Sampling.\r | |
179 | ///\r | |
2f88bd3a | 180 | UINT32 IBS : 1;\r |
890d2bd2 LD |
181 | ///\r |
182 | /// [Bit 11] Extended Operation Support.\r | |
183 | ///\r | |
2f88bd3a | 184 | UINT32 XOP : 1;\r |
890d2bd2 LD |
185 | ///\r |
186 | /// [Bit 12] SKINIT and STGI support.\r | |
187 | ///\r | |
2f88bd3a | 188 | UINT32 SKINIT : 1;\r |
890d2bd2 LD |
189 | ///\r |
190 | /// [Bit 13] Watchdog Timer support.\r | |
191 | ///\r | |
2f88bd3a | 192 | UINT32 WDT : 1;\r |
890d2bd2 LD |
193 | ///\r |
194 | /// [Bit 14] Reserved.\r | |
195 | ///\r | |
2f88bd3a | 196 | UINT32 Reserved1 : 1;\r |
890d2bd2 LD |
197 | ///\r |
198 | /// [Bit 15] Lightweight Profiling support.\r | |
199 | ///\r | |
2f88bd3a | 200 | UINT32 LWP : 1;\r |
890d2bd2 LD |
201 | ///\r |
202 | /// [Bit 16] 4-Operand FMA instruction support.\r | |
203 | ///\r | |
2f88bd3a | 204 | UINT32 FMA4 : 1;\r |
890d2bd2 LD |
205 | ///\r |
206 | /// [Bit 17] Translation Cache Extension.\r | |
207 | ///\r | |
2f88bd3a | 208 | UINT32 TCE : 1;\r |
890d2bd2 LD |
209 | ///\r |
210 | /// [Bit 21:18] Reserved.\r | |
211 | ///\r | |
2f88bd3a | 212 | UINT32 Reserved2 : 4;\r |
890d2bd2 LD |
213 | ///\r |
214 | /// [Bit 22] Topology Extensions support.\r | |
215 | ///\r | |
2f88bd3a | 216 | UINT32 TopologyExtensions : 1;\r |
890d2bd2 LD |
217 | ///\r |
218 | /// [Bit 23] Core Performance Counter Extensions.\r | |
219 | ///\r | |
2f88bd3a | 220 | UINT32 PerfCtrExtCore : 1;\r |
890d2bd2 LD |
221 | ///\r |
222 | /// [Bit 25:24] Reserved.\r | |
223 | ///\r | |
2f88bd3a | 224 | UINT32 Reserved3 : 2;\r |
890d2bd2 LD |
225 | ///\r |
226 | /// [Bit 26] Data Breakpoint Extension.\r | |
227 | ///\r | |
2f88bd3a | 228 | UINT32 DataBreakpointExtension : 1;\r |
890d2bd2 LD |
229 | ///\r |
230 | /// [Bit 27] Performance Time-Stamp Counter.\r | |
231 | ///\r | |
2f88bd3a | 232 | UINT32 PerfTsc : 1;\r |
890d2bd2 LD |
233 | ///\r |
234 | /// [Bit 28] L3 Performance Counter Extensions.\r | |
235 | ///\r | |
2f88bd3a | 236 | UINT32 PerfCtrExtL3 : 1;\r |
890d2bd2 LD |
237 | ///\r |
238 | /// [Bit 29] MWAITX and MONITORX capability.\r | |
239 | ///\r | |
2f88bd3a | 240 | UINT32 MwaitExtended : 1;\r |
890d2bd2 LD |
241 | ///\r |
242 | /// [Bit 31:30] Reserved.\r | |
243 | ///\r | |
2f88bd3a | 244 | UINT32 Reserved4 : 2;\r |
890d2bd2 LD |
245 | } Bits;\r |
246 | ///\r | |
247 | /// All bit fields as a 32-bit value\r | |
248 | ///\r | |
2f88bd3a | 249 | UINT32 Uint32;\r |
890d2bd2 LD |
250 | } CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r |
251 | \r | |
252 | /**\r | |
253 | CPUID Extended Processor Signature and Features EDX for CPUID leaf\r | |
254 | #CPUID_EXTENDED_CPU_SIG.\r | |
255 | **/\r | |
256 | typedef union {\r | |
257 | ///\r | |
258 | /// Individual bit fields\r | |
259 | ///\r | |
260 | struct {\r | |
261 | ///\r | |
262 | /// [Bit 0] x87 floating point unit on-chip.\r | |
263 | ///\r | |
2f88bd3a | 264 | UINT32 FPU : 1;\r |
890d2bd2 LD |
265 | ///\r |
266 | /// [Bit 1] Virtual-mode enhancements.\r | |
267 | ///\r | |
2f88bd3a | 268 | UINT32 VME : 1;\r |
890d2bd2 LD |
269 | ///\r |
270 | /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r | |
271 | ///\r | |
2f88bd3a | 272 | UINT32 DE : 1;\r |
890d2bd2 LD |
273 | ///\r |
274 | /// [Bit 3] Page-size extensions (4 MB pages).\r | |
275 | ///\r | |
2f88bd3a | 276 | UINT32 PSE : 1;\r |
890d2bd2 LD |
277 | ///\r |
278 | /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r | |
279 | ///\r | |
2f88bd3a | 280 | UINT32 TSC : 1;\r |
890d2bd2 LD |
281 | ///\r |
282 | /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r | |
283 | ///\r | |
2f88bd3a | 284 | UINT32 MSR : 1;\r |
890d2bd2 LD |
285 | ///\r |
286 | /// [Bit 6] Physical-address extensions (PAE).\r | |
287 | ///\r | |
2f88bd3a | 288 | UINT32 PAE : 1;\r |
890d2bd2 LD |
289 | ///\r |
290 | /// [Bit 7] Machine check exception, CR4.MCE.\r | |
291 | ///\r | |
2f88bd3a | 292 | UINT32 MCE : 1;\r |
890d2bd2 LD |
293 | ///\r |
294 | /// [Bit 8] CMPXCHG8B instruction.\r | |
295 | ///\r | |
2f88bd3a | 296 | UINT32 CMPXCHG8B : 1;\r |
890d2bd2 LD |
297 | ///\r |
298 | /// [Bit 9] APIC exists and is enabled.\r | |
299 | ///\r | |
2f88bd3a | 300 | UINT32 APIC : 1;\r |
890d2bd2 LD |
301 | ///\r |
302 | /// [Bit 10] Reserved.\r | |
303 | ///\r | |
2f88bd3a | 304 | UINT32 Reserved1 : 1;\r |
890d2bd2 LD |
305 | ///\r |
306 | /// [Bit 11] SYSCALL and SYSRET instructions.\r | |
307 | ///\r | |
2f88bd3a | 308 | UINT32 SYSCALL_SYSRET : 1;\r |
890d2bd2 LD |
309 | ///\r |
310 | /// [Bit 12] Memory-type range registers.\r | |
311 | ///\r | |
2f88bd3a | 312 | UINT32 MTRR : 1;\r |
890d2bd2 LD |
313 | ///\r |
314 | /// [Bit 13] Page global extension, CR4.PGE.\r | |
315 | ///\r | |
2f88bd3a | 316 | UINT32 PGE : 1;\r |
890d2bd2 LD |
317 | ///\r |
318 | /// [Bit 14] Machine check architecture, MCG_CAP.\r | |
319 | ///\r | |
2f88bd3a | 320 | UINT32 MCA : 1;\r |
890d2bd2 LD |
321 | ///\r |
322 | /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r | |
323 | ///\r | |
2f88bd3a | 324 | UINT32 CMOV : 1;\r |
890d2bd2 LD |
325 | ///\r |
326 | /// [Bit 16] Page attribute table.\r | |
327 | ///\r | |
2f88bd3a | 328 | UINT32 PAT : 1;\r |
890d2bd2 LD |
329 | ///\r |
330 | /// [Bit 17] Page-size extensions.\r | |
331 | ///\r | |
2f88bd3a | 332 | UINT32 PSE36 : 1;\r |
890d2bd2 LD |
333 | ///\r |
334 | /// [Bit 19:18] Reserved.\r | |
335 | ///\r | |
2f88bd3a | 336 | UINT32 Reserved2 : 2;\r |
890d2bd2 LD |
337 | ///\r |
338 | /// [Bit 20] No-execute page protection.\r | |
339 | ///\r | |
2f88bd3a | 340 | UINT32 NX : 1;\r |
890d2bd2 LD |
341 | ///\r |
342 | /// [Bit 21] Reserved.\r | |
343 | ///\r | |
2f88bd3a | 344 | UINT32 Reserved3 : 1;\r |
890d2bd2 LD |
345 | ///\r |
346 | /// [Bit 22] AMD Extensions to MMX instructions.\r | |
347 | ///\r | |
2f88bd3a | 348 | UINT32 MmxExt : 1;\r |
890d2bd2 LD |
349 | ///\r |
350 | /// [Bit 23] MMX instructions.\r | |
351 | ///\r | |
2f88bd3a | 352 | UINT32 MMX : 1;\r |
890d2bd2 LD |
353 | ///\r |
354 | /// [Bit 24] FXSAVE and FXRSTOR instructions.\r | |
355 | ///\r | |
2f88bd3a | 356 | UINT32 FFSR : 1;\r |
890d2bd2 LD |
357 | ///\r |
358 | /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r | |
359 | ///\r | |
2f88bd3a | 360 | UINT32 FFXSR : 1;\r |
890d2bd2 LD |
361 | ///\r |
362 | /// [Bit 26] 1-GByte large page support.\r | |
363 | ///\r | |
2f88bd3a | 364 | UINT32 Page1GB : 1;\r |
890d2bd2 | 365 | ///\r |
788421d5 | 366 | /// [Bit 27] RDTSCP instructions.\r |
890d2bd2 | 367 | ///\r |
2f88bd3a | 368 | UINT32 RDTSCP : 1;\r |
890d2bd2 LD |
369 | ///\r |
370 | /// [Bit 28] Reserved.\r | |
371 | ///\r | |
2f88bd3a | 372 | UINT32 Reserved4 : 1;\r |
890d2bd2 LD |
373 | ///\r |
374 | /// [Bit 29] Long Mode.\r | |
375 | ///\r | |
2f88bd3a | 376 | UINT32 LM : 1;\r |
890d2bd2 LD |
377 | ///\r |
378 | /// [Bit 30] 3DNow! instructions.\r | |
379 | ///\r | |
2f88bd3a | 380 | UINT32 ThreeDNow : 1;\r |
890d2bd2 LD |
381 | ///\r |
382 | /// [Bit 31] AMD Extensions to 3DNow! instructions.\r | |
383 | ///\r | |
2f88bd3a | 384 | UINT32 ThreeDNowExt : 1;\r |
890d2bd2 LD |
385 | } Bits;\r |
386 | ///\r | |
387 | /// All bit fields as a 32-bit value\r | |
388 | ///\r | |
2f88bd3a | 389 | UINT32 Uint32;\r |
890d2bd2 LD |
390 | } CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r |
391 | \r | |
890d2bd2 LD |
392 | /**\r |
393 | CPUID Linear Physical Address Size\r | |
394 | \r | |
395 | @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r | |
b15cbd9c | 396 | \r |
890d2bd2 LD |
397 | @retval EAX Linear/Physical Address Size described by the type\r |
398 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.\r | |
399 | @retval EBX Linear/Physical Address Size described by the type\r | |
400 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.\r | |
401 | @retval ECX Linear/Physical Address Size described by the type\r | |
402 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.\r | |
403 | @retval EDX Reserved.\r | |
404 | **/\r | |
405 | \r | |
406 | /**\r | |
407 | CPUID Linear Physical Address Size EAX for CPUID leaf\r | |
408 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
409 | **/\r | |
410 | typedef union {\r | |
411 | ///\r | |
412 | /// Individual bit fields\r | |
413 | ///\r | |
414 | struct {\r | |
415 | ///\r | |
416 | /// [Bits 7:0] Maximum physical byte address size in bits.\r | |
417 | ///\r | |
2f88bd3a | 418 | UINT32 PhysicalAddressBits : 8;\r |
890d2bd2 LD |
419 | ///\r |
420 | /// [Bits 15:8] Maximum linear byte address size in bits.\r | |
421 | ///\r | |
2f88bd3a | 422 | UINT32 LinearAddressBits : 8;\r |
890d2bd2 LD |
423 | ///\r |
424 | /// [Bits 23:16] Maximum guest physical byte address size in bits.\r | |
425 | ///\r | |
2f88bd3a | 426 | UINT32 GuestPhysAddrSize : 8;\r |
890d2bd2 LD |
427 | ///\r |
428 | /// [Bit 31:24] Reserved.\r | |
429 | ///\r | |
2f88bd3a | 430 | UINT32 Reserved : 8;\r |
890d2bd2 LD |
431 | } Bits;\r |
432 | ///\r | |
433 | /// All bit fields as a 32-bit value\r | |
434 | ///\r | |
2f88bd3a | 435 | UINT32 Uint32;\r |
890d2bd2 LD |
436 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r |
437 | \r | |
438 | /**\r | |
439 | CPUID Linear Physical Address Size EBX for CPUID leaf\r | |
440 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
441 | **/\r | |
442 | typedef union {\r | |
443 | ///\r | |
444 | /// Individual bit fields\r | |
445 | ///\r | |
446 | struct {\r | |
447 | ///\r | |
448 | /// [Bits 0] Clear Zero Instruction.\r | |
449 | ///\r | |
2f88bd3a | 450 | UINT32 CLZERO : 1;\r |
890d2bd2 LD |
451 | ///\r |
452 | /// [Bits 1] Instructions retired count support.\r | |
453 | ///\r | |
2f88bd3a | 454 | UINT32 IRPerf : 1;\r |
890d2bd2 LD |
455 | ///\r |
456 | /// [Bits 2] Restore error pointers for XSave instructions.\r | |
457 | ///\r | |
2f88bd3a | 458 | UINT32 XSaveErPtr : 1;\r |
890d2bd2 LD |
459 | ///\r |
460 | /// [Bit 31:3] Reserved.\r | |
461 | ///\r | |
2f88bd3a | 462 | UINT32 Reserved : 29;\r |
890d2bd2 LD |
463 | } Bits;\r |
464 | ///\r | |
465 | /// All bit fields as a 32-bit value\r | |
466 | ///\r | |
2f88bd3a | 467 | UINT32 Uint32;\r |
890d2bd2 LD |
468 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r |
469 | \r | |
470 | /**\r | |
471 | CPUID Linear Physical Address Size ECX for CPUID leaf\r | |
472 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
473 | **/\r | |
474 | typedef union {\r | |
475 | ///\r | |
476 | /// Individual bit fields\r | |
477 | ///\r | |
478 | struct {\r | |
479 | ///\r | |
480 | /// [Bits 7:0] Number of threads - 1.\r | |
481 | ///\r | |
2f88bd3a | 482 | UINT32 NC : 8;\r |
890d2bd2 LD |
483 | ///\r |
484 | /// [Bit 11:8] Reserved.\r | |
485 | ///\r | |
2f88bd3a | 486 | UINT32 Reserved1 : 4;\r |
890d2bd2 LD |
487 | ///\r |
488 | /// [Bits 15:12] APIC ID size.\r | |
489 | ///\r | |
2f88bd3a | 490 | UINT32 ApicIdCoreIdSize : 4;\r |
890d2bd2 LD |
491 | ///\r |
492 | /// [Bits 17:16] Performance time-stamp counter size.\r | |
493 | ///\r | |
2f88bd3a | 494 | UINT32 PerfTscSize : 2;\r |
890d2bd2 LD |
495 | ///\r |
496 | /// [Bit 31:18] Reserved.\r | |
497 | ///\r | |
2f88bd3a | 498 | UINT32 Reserved2 : 14;\r |
890d2bd2 LD |
499 | } Bits;\r |
500 | ///\r | |
501 | /// All bit fields as a 32-bit value\r | |
502 | ///\r | |
2f88bd3a | 503 | UINT32 Uint32;\r |
890d2bd2 LD |
504 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r |
505 | \r | |
890d2bd2 LD |
506 | /**\r |
507 | CPUID AMD Processor Topology\r | |
508 | \r | |
509 | @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)\r | |
510 | \r | |
511 | @retval EAX Extended APIC ID described by the type\r | |
512 | CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.\r | |
788421d5 | 513 | @retval EBX Core Identifiers described by the type\r |
890d2bd2 | 514 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.\r |
788421d5 | 515 | @retval ECX Node Identifiers described by the type\r |
890d2bd2 LD |
516 | CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r |
517 | @retval EDX Reserved.\r | |
518 | **/\r | |
2f88bd3a | 519 | #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r |
890d2bd2 LD |
520 | \r |
521 | /**\r | |
522 | CPUID AMD Processor Topology EAX for CPUID leaf\r | |
523 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
524 | **/\r | |
525 | typedef union {\r | |
526 | ///\r | |
527 | /// Individual bit fields\r | |
528 | ///\r | |
529 | struct {\r | |
530 | ///\r | |
531 | /// [Bit 31:0] Extended APIC Id.\r | |
532 | ///\r | |
2f88bd3a | 533 | UINT32 ExtendedApicId;\r |
890d2bd2 LD |
534 | } Bits;\r |
535 | ///\r | |
536 | /// All bit fields as a 32-bit value\r | |
537 | ///\r | |
2f88bd3a | 538 | UINT32 Uint32;\r |
890d2bd2 LD |
539 | } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r |
540 | \r | |
541 | /**\r | |
542 | CPUID AMD Processor Topology EBX for CPUID leaf\r | |
543 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
544 | **/\r | |
545 | typedef union {\r | |
546 | ///\r | |
547 | /// Individual bit fields\r | |
548 | ///\r | |
549 | struct {\r | |
550 | ///\r | |
551 | /// [Bits 7:0] Core Id.\r | |
552 | ///\r | |
2f88bd3a | 553 | UINT32 CoreId : 8;\r |
890d2bd2 LD |
554 | ///\r |
555 | /// [Bits 15:8] Threads per core.\r | |
556 | ///\r | |
2f88bd3a | 557 | UINT32 ThreadsPerCore : 8;\r |
890d2bd2 LD |
558 | ///\r |
559 | /// [Bit 31:16] Reserved.\r | |
560 | ///\r | |
2f88bd3a | 561 | UINT32 Reserved : 16;\r |
890d2bd2 LD |
562 | } Bits;\r |
563 | ///\r | |
564 | /// All bit fields as a 32-bit value\r | |
565 | ///\r | |
2f88bd3a | 566 | UINT32 Uint32;\r |
890d2bd2 LD |
567 | } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r |
568 | \r | |
569 | /**\r | |
570 | CPUID AMD Processor Topology ECX for CPUID leaf\r | |
571 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
572 | **/\r | |
573 | typedef union {\r | |
574 | ///\r | |
575 | /// Individual bit fields\r | |
576 | ///\r | |
577 | struct {\r | |
578 | ///\r | |
579 | /// [Bits 7:0] Node Id.\r | |
580 | ///\r | |
2f88bd3a | 581 | UINT32 NodeId : 8;\r |
890d2bd2 LD |
582 | ///\r |
583 | /// [Bits 10:8] Nodes per processor.\r | |
584 | ///\r | |
2f88bd3a | 585 | UINT32 NodesPerProcessor : 3;\r |
890d2bd2 LD |
586 | ///\r |
587 | /// [Bit 31:11] Reserved.\r | |
588 | ///\r | |
2f88bd3a | 589 | UINT32 Reserved : 21;\r |
890d2bd2 LD |
590 | } Bits;\r |
591 | ///\r | |
592 | /// All bit fields as a 32-bit value\r | |
593 | ///\r | |
2f88bd3a | 594 | UINT32 Uint32;\r |
890d2bd2 LD |
595 | } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r |
596 | \r | |
890d2bd2 LD |
597 | /**\r |
598 | CPUID Memory Encryption Information\r | |
b15cbd9c BS |
599 | \r |
600 | @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r | |
601 | \r | |
602 | @retval EAX Returns the memory encryption feature support status.\r | |
603 | @retval EBX If memory encryption feature is present then return\r | |
604 | the page table bit number used to enable memory encryption support\r | |
605 | and reducing of physical address space in bits.\r | |
890d2bd2 LD |
606 | @retval ECX Returns number of encrypted guest supported simultaneously.\r |
607 | @retval EDX Returns minimum SEV enabled and SEV disabled ASID.\r | |
b15cbd9c BS |
608 | \r |
609 | <b>Example usage</b>\r | |
610 | @code\r | |
611 | UINT32 Eax;\r | |
612 | UINT32 Ebx;\r | |
613 | UINT32 Ecx;\r | |
614 | UINT32 Edx;\r | |
615 | \r | |
616 | AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r | |
617 | @endcode\r | |
618 | **/\r | |
619 | \r | |
2f88bd3a | 620 | #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r |
b15cbd9c BS |
621 | \r |
622 | /**\r | |
623 | CPUID Memory Encryption support information EAX for CPUID leaf\r | |
624 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
625 | **/\r | |
626 | typedef union {\r | |
627 | ///\r | |
628 | /// Individual bit fields\r | |
629 | ///\r | |
630 | struct {\r | |
631 | ///\r | |
632 | /// [Bit 0] Secure Memory Encryption (Sme) Support\r | |
633 | ///\r | |
2f88bd3a | 634 | UINT32 SmeBit : 1;\r |
b15cbd9c BS |
635 | \r |
636 | ///\r | |
637 | /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r | |
638 | ///\r | |
2f88bd3a | 639 | UINT32 SevBit : 1;\r |
b15cbd9c BS |
640 | \r |
641 | ///\r | |
642 | /// [Bit 2] Page flush MSR support\r | |
643 | ///\r | |
2f88bd3a | 644 | UINT32 PageFlushMsrBit : 1;\r |
b15cbd9c BS |
645 | \r |
646 | ///\r | |
647 | /// [Bit 3] Encrypted state support\r | |
648 | ///\r | |
2f88bd3a | 649 | UINT32 SevEsBit : 1;\r |
b15cbd9c BS |
650 | \r |
651 | ///\r | |
890d2bd2 | 652 | /// [Bit 31:4] Reserved\r |
b15cbd9c | 653 | ///\r |
2f88bd3a | 654 | UINT32 ReservedBits : 28;\r |
b15cbd9c BS |
655 | } Bits;\r |
656 | ///\r | |
657 | /// All bit fields as a 32-bit value\r | |
658 | ///\r | |
2f88bd3a | 659 | UINT32 Uint32;\r |
b15cbd9c BS |
660 | } CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r |
661 | \r | |
662 | /**\r | |
663 | CPUID Memory Encryption support information EBX for CPUID leaf\r | |
664 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
665 | **/\r | |
666 | typedef union {\r | |
667 | ///\r | |
668 | /// Individual bit fields\r | |
669 | ///\r | |
670 | struct {\r | |
671 | ///\r | |
890d2bd2 | 672 | /// [Bit 5:0] Page table bit number used to enable memory encryption\r |
b15cbd9c | 673 | ///\r |
2f88bd3a | 674 | UINT32 PtePosBits : 6;\r |
b15cbd9c BS |
675 | \r |
676 | ///\r | |
890d2bd2 LD |
677 | /// [Bit 11:6] Reduction of system physical address space bits when\r |
678 | /// memory encryption is enabled\r | |
b15cbd9c | 679 | ///\r |
2f88bd3a | 680 | UINT32 ReducedPhysBits : 5;\r |
b15cbd9c BS |
681 | \r |
682 | ///\r | |
890d2bd2 | 683 | /// [Bit 31:12] Reserved\r |
b15cbd9c | 684 | ///\r |
2f88bd3a | 685 | UINT32 ReservedBits : 21;\r |
b15cbd9c BS |
686 | } Bits;\r |
687 | ///\r | |
688 | /// All bit fields as a 32-bit value\r | |
689 | ///\r | |
2f88bd3a | 690 | UINT32 Uint32;\r |
b15cbd9c BS |
691 | } CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r |
692 | \r | |
693 | /**\r | |
694 | CPUID Memory Encryption support information ECX for CPUID leaf\r | |
695 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
696 | **/\r | |
697 | typedef union {\r | |
698 | ///\r | |
699 | /// Individual bit fields\r | |
700 | ///\r | |
701 | struct {\r | |
702 | ///\r | |
890d2bd2 | 703 | /// [Bit 31:0] Number of encrypted guest supported simultaneously\r |
b15cbd9c | 704 | ///\r |
2f88bd3a | 705 | UINT32 NumGuests;\r |
b15cbd9c BS |
706 | } Bits;\r |
707 | ///\r | |
708 | /// All bit fields as a 32-bit value\r | |
709 | ///\r | |
2f88bd3a | 710 | UINT32 Uint32;\r |
b15cbd9c BS |
711 | } CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r |
712 | \r | |
713 | /**\r | |
714 | CPUID Memory Encryption support information EDX for CPUID leaf\r | |
715 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
716 | **/\r | |
717 | typedef union {\r | |
718 | ///\r | |
719 | /// Individual bit fields\r | |
720 | ///\r | |
721 | struct {\r | |
722 | ///\r | |
890d2bd2 | 723 | /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r |
b15cbd9c | 724 | ///\r |
2f88bd3a | 725 | UINT32 MinAsid;\r |
b15cbd9c BS |
726 | } Bits;\r |
727 | ///\r | |
728 | /// All bit fields as a 32-bit value\r | |
729 | ///\r | |
2f88bd3a | 730 | UINT32 Uint32;\r |
b15cbd9c BS |
731 | } CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r |
732 | \r | |
733 | #endif\r |