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1 | /** @file\r |
2 | CPUID leaf definitions.\r | |
3 | \r | |
4 | Provides defines for CPUID leaf indexes. Data structures are provided for\r | |
5 | registers returned by a CPUID leaf that contain one or more bit fields.\r | |
6 | If a register returned is a single 32-bit value, then a data structure is\r | |
7 | not provided for that register.\r | |
8 | \r | |
9 | Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r | |
890d2bd2 | 10 | \r |
0acd8697 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
b15cbd9c BS |
12 | \r |
13 | @par Specification Reference:\r | |
14 | AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef __AMD_CPUID_H__\r | |
19 | #define __AMD_CPUID_H__\r | |
20 | \r | |
21 | /**\r | |
890d2bd2 LD |
22 | CPUID Signature Information\r |
23 | \r | |
24 | @param EAX CPUID_SIGNATURE (0x00)\r | |
25 | \r | |
26 | @retval EAX Returns the highest value the CPUID instruction recognizes for\r | |
27 | returning basic processor information. The value is returned is\r | |
28 | processor specific.\r | |
29 | @retval EBX First 4 characters of a vendor identification string.\r | |
30 | @retval ECX Last 4 characters of a vendor identification string.\r | |
31 | @retval EDX Middle 4 characters of a vendor identification string.\r | |
32 | \r | |
33 | **/\r | |
34 | \r | |
35 | ///\r | |
36 | /// @{ CPUID signature values returned by AMD processors\r | |
37 | ///\r | |
38 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')\r | |
39 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')\r | |
40 | #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')\r | |
41 | ///\r | |
42 | /// @}\r | |
43 | ///\r | |
44 | \r | |
45 | \r | |
46 | /**\r | |
47 | CPUID Extended Processor Signature and Features\r | |
48 | \r | |
49 | @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r | |
50 | \r | |
51 | @retval EAX Extended Family, Model, Stepping Identifiers\r | |
52 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.\r | |
53 | @retval EBX Brand Identifier\r | |
54 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.\r | |
55 | @retval ECX Extended Feature Identifiers\r | |
56 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.\r | |
57 | @retval EDX Extended Feature Identifiers\r | |
58 | described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.\r | |
59 | **/\r | |
60 | \r | |
61 | /**\r | |
62 | CPUID Extended Processor Signature and Features EAX for CPUID leaf\r | |
63 | #CPUID_EXTENDED_CPU_SIG.\r | |
64 | **/\r | |
65 | typedef union {\r | |
66 | ///\r | |
67 | /// Individual bit fields\r | |
68 | ///\r | |
69 | struct {\r | |
70 | ///\r | |
71 | /// [Bits 3:0] Stepping.\r | |
72 | ///\r | |
73 | UINT32 Stepping:4;\r | |
74 | ///\r | |
75 | /// [Bits 7:4] Base Model.\r | |
76 | ///\r | |
77 | UINT32 BaseModel:4;\r | |
78 | ///\r | |
79 | /// [Bits 11:8] Base Family.\r | |
80 | ///\r | |
81 | UINT32 BaseFamily:4;\r | |
82 | ///\r | |
83 | /// [Bit 15:12] Reserved.\r | |
84 | ///\r | |
85 | UINT32 Reserved1:4;\r | |
86 | ///\r | |
87 | /// [Bits 19:16] Extended Model.\r | |
88 | ///\r | |
89 | UINT32 ExtModel:4;\r | |
90 | ///\r | |
91 | /// [Bits 27:20] Extended Family.\r | |
92 | ///\r | |
93 | UINT32 ExtFamily:8;\r | |
94 | ///\r | |
95 | /// [Bit 31:28] Reserved.\r | |
96 | ///\r | |
97 | UINT32 Reserved2:4;\r | |
98 | } Bits;\r | |
99 | ///\r | |
100 | /// All bit fields as a 32-bit value\r | |
101 | ///\r | |
102 | UINT32 Uint32;\r | |
103 | } CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r | |
104 | \r | |
105 | /**\r | |
106 | CPUID Extended Processor Signature and Features EBX for CPUID leaf\r | |
107 | #CPUID_EXTENDED_CPU_SIG.\r | |
108 | **/\r | |
109 | typedef union {\r | |
110 | ///\r | |
111 | /// Individual bit fields\r | |
112 | ///\r | |
113 | struct {\r | |
114 | ///\r | |
115 | /// [Bits 27:0] Reserved.\r | |
116 | ///\r | |
117 | UINT32 Reserved:28;\r | |
118 | ///\r | |
119 | /// [Bit 31:28] Package Type.\r | |
120 | ///\r | |
121 | UINT32 PkgType:4;\r | |
122 | } Bits;\r | |
123 | ///\r | |
124 | /// All bit fields as a 32-bit value\r | |
125 | ///\r | |
126 | UINT32 Uint32;\r | |
127 | } CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r | |
128 | \r | |
129 | /**\r | |
130 | CPUID Extended Processor Signature and Features ECX for CPUID leaf\r | |
131 | #CPUID_EXTENDED_CPU_SIG.\r | |
132 | **/\r | |
133 | typedef union {\r | |
134 | ///\r | |
135 | /// Individual bit fields\r | |
136 | ///\r | |
137 | struct {\r | |
138 | ///\r | |
139 | /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r | |
140 | ///\r | |
141 | UINT32 LAHF_SAHF:1;\r | |
142 | ///\r | |
143 | /// [Bit 1] Core multi-processing legacy mode.\r | |
144 | ///\r | |
145 | UINT32 CmpLegacy:1;\r | |
146 | ///\r | |
147 | /// [Bit 2] Secure Virtual Mode feature.\r | |
148 | ///\r | |
149 | UINT32 SVM:1;\r | |
150 | ///\r | |
151 | /// [Bit 3] Extended APIC register space.\r | |
152 | ///\r | |
153 | UINT32 ExtApicSpace:1;\r | |
154 | ///\r | |
155 | /// [Bit 4] LOCK MOV CR0 means MOV CR8.\r | |
156 | ///\r | |
157 | UINT32 AltMovCr8:1;\r | |
158 | ///\r | |
159 | /// [Bit 5] LZCNT instruction support.\r | |
160 | ///\r | |
161 | UINT32 LZCNT:1;\r | |
162 | ///\r | |
163 | /// [Bit 6] SSE4A instruction support.\r | |
164 | ///\r | |
165 | UINT32 SSE4A:1;\r | |
166 | ///\r | |
167 | /// [Bit 7] Misaligned SSE Mode.\r | |
168 | ///\r | |
169 | UINT32 MisAlignSse:1;\r | |
170 | ///\r | |
171 | /// [Bit 8] ThreeDNow Prefetch instructions.\r | |
172 | ///\r | |
173 | UINT32 PREFETCHW:1;\r | |
174 | ///\r | |
175 | /// [Bit 9] OS Visible Work-around support.\r | |
176 | ///\r | |
177 | UINT32 OSVW:1;\r | |
178 | ///\r | |
179 | /// [Bit 10] Instruction Based Sampling.\r | |
180 | ///\r | |
181 | UINT32 IBS:1;\r | |
182 | ///\r | |
183 | /// [Bit 11] Extended Operation Support.\r | |
184 | ///\r | |
185 | UINT32 XOP:1;\r | |
186 | ///\r | |
187 | /// [Bit 12] SKINIT and STGI support.\r | |
188 | ///\r | |
189 | UINT32 SKINIT:1;\r | |
190 | ///\r | |
191 | /// [Bit 13] Watchdog Timer support.\r | |
192 | ///\r | |
193 | UINT32 WDT:1;\r | |
194 | ///\r | |
195 | /// [Bit 14] Reserved.\r | |
196 | ///\r | |
197 | UINT32 Reserved1:1;\r | |
198 | ///\r | |
199 | /// [Bit 15] Lightweight Profiling support.\r | |
200 | ///\r | |
201 | UINT32 LWP:1;\r | |
202 | ///\r | |
203 | /// [Bit 16] 4-Operand FMA instruction support.\r | |
204 | ///\r | |
205 | UINT32 FMA4:1;\r | |
206 | ///\r | |
207 | /// [Bit 17] Translation Cache Extension.\r | |
208 | ///\r | |
209 | UINT32 TCE:1;\r | |
210 | ///\r | |
211 | /// [Bit 21:18] Reserved.\r | |
212 | ///\r | |
213 | UINT32 Reserved2:4;\r | |
214 | ///\r | |
215 | /// [Bit 22] Topology Extensions support.\r | |
216 | ///\r | |
217 | UINT32 TopologyExtensions:1;\r | |
218 | ///\r | |
219 | /// [Bit 23] Core Performance Counter Extensions.\r | |
220 | ///\r | |
221 | UINT32 PerfCtrExtCore:1;\r | |
222 | ///\r | |
223 | /// [Bit 25:24] Reserved.\r | |
224 | ///\r | |
225 | UINT32 Reserved3:2;\r | |
226 | ///\r | |
227 | /// [Bit 26] Data Breakpoint Extension.\r | |
228 | ///\r | |
229 | UINT32 DataBreakpointExtension:1;\r | |
230 | ///\r | |
231 | /// [Bit 27] Performance Time-Stamp Counter.\r | |
232 | ///\r | |
233 | UINT32 PerfTsc:1;\r | |
234 | ///\r | |
235 | /// [Bit 28] L3 Performance Counter Extensions.\r | |
236 | ///\r | |
237 | UINT32 PerfCtrExtL3:1;\r | |
238 | ///\r | |
239 | /// [Bit 29] MWAITX and MONITORX capability.\r | |
240 | ///\r | |
241 | UINT32 MwaitExtended:1;\r | |
242 | ///\r | |
243 | /// [Bit 31:30] Reserved.\r | |
244 | ///\r | |
245 | UINT32 Reserved4:2;\r | |
246 | } Bits;\r | |
247 | ///\r | |
248 | /// All bit fields as a 32-bit value\r | |
249 | ///\r | |
250 | UINT32 Uint32;\r | |
251 | } CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r | |
252 | \r | |
253 | /**\r | |
254 | CPUID Extended Processor Signature and Features EDX for CPUID leaf\r | |
255 | #CPUID_EXTENDED_CPU_SIG.\r | |
256 | **/\r | |
257 | typedef union {\r | |
258 | ///\r | |
259 | /// Individual bit fields\r | |
260 | ///\r | |
261 | struct {\r | |
262 | ///\r | |
263 | /// [Bit 0] x87 floating point unit on-chip.\r | |
264 | ///\r | |
265 | UINT32 FPU:1;\r | |
266 | ///\r | |
267 | /// [Bit 1] Virtual-mode enhancements.\r | |
268 | ///\r | |
269 | UINT32 VME:1;\r | |
270 | ///\r | |
271 | /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r | |
272 | ///\r | |
273 | UINT32 DE:1;\r | |
274 | ///\r | |
275 | /// [Bit 3] Page-size extensions (4 MB pages).\r | |
276 | ///\r | |
277 | UINT32 PSE:1;\r | |
278 | ///\r | |
279 | /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r | |
280 | ///\r | |
281 | UINT32 TSC:1;\r | |
282 | ///\r | |
283 | /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r | |
284 | ///\r | |
285 | UINT32 MSR:1;\r | |
286 | ///\r | |
287 | /// [Bit 6] Physical-address extensions (PAE).\r | |
288 | ///\r | |
289 | UINT32 PAE:1;\r | |
290 | ///\r | |
291 | /// [Bit 7] Machine check exception, CR4.MCE.\r | |
292 | ///\r | |
293 | UINT32 MCE:1;\r | |
294 | ///\r | |
295 | /// [Bit 8] CMPXCHG8B instruction.\r | |
296 | ///\r | |
297 | UINT32 CMPXCHG8B:1;\r | |
298 | ///\r | |
299 | /// [Bit 9] APIC exists and is enabled.\r | |
300 | ///\r | |
301 | UINT32 APIC:1;\r | |
302 | ///\r | |
303 | /// [Bit 10] Reserved.\r | |
304 | ///\r | |
305 | UINT32 Reserved1:1;\r | |
306 | ///\r | |
307 | /// [Bit 11] SYSCALL and SYSRET instructions.\r | |
308 | ///\r | |
309 | UINT32 SYSCALL_SYSRET:1;\r | |
310 | ///\r | |
311 | /// [Bit 12] Memory-type range registers.\r | |
312 | ///\r | |
313 | UINT32 MTRR:1;\r | |
314 | ///\r | |
315 | /// [Bit 13] Page global extension, CR4.PGE.\r | |
316 | ///\r | |
317 | UINT32 PGE:1;\r | |
318 | ///\r | |
319 | /// [Bit 14] Machine check architecture, MCG_CAP.\r | |
320 | ///\r | |
321 | UINT32 MCA:1;\r | |
322 | ///\r | |
323 | /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r | |
324 | ///\r | |
325 | UINT32 CMOV:1;\r | |
326 | ///\r | |
327 | /// [Bit 16] Page attribute table.\r | |
328 | ///\r | |
329 | UINT32 PAT:1;\r | |
330 | ///\r | |
331 | /// [Bit 17] Page-size extensions.\r | |
332 | ///\r | |
333 | UINT32 PSE36 : 1;\r | |
334 | ///\r | |
335 | /// [Bit 19:18] Reserved.\r | |
336 | ///\r | |
337 | UINT32 Reserved2:2;\r | |
338 | ///\r | |
339 | /// [Bit 20] No-execute page protection.\r | |
340 | ///\r | |
341 | UINT32 NX:1;\r | |
342 | ///\r | |
343 | /// [Bit 21] Reserved.\r | |
344 | ///\r | |
345 | UINT32 Reserved3:1;\r | |
346 | ///\r | |
347 | /// [Bit 22] AMD Extensions to MMX instructions.\r | |
348 | ///\r | |
349 | UINT32 MmxExt:1;\r | |
350 | ///\r | |
351 | /// [Bit 23] MMX instructions.\r | |
352 | ///\r | |
353 | UINT32 MMX:1;\r | |
354 | ///\r | |
355 | /// [Bit 24] FXSAVE and FXRSTOR instructions.\r | |
356 | ///\r | |
357 | UINT32 FFSR:1;\r | |
358 | ///\r | |
359 | /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r | |
360 | ///\r | |
361 | UINT32 FFXSR:1;\r | |
362 | ///\r | |
363 | /// [Bit 26] 1-GByte large page support.\r | |
364 | ///\r | |
365 | UINT32 Page1GB:1;\r | |
366 | ///\r | |
367 | /// [Bit 27] RDTSCP intructions.\r | |
368 | ///\r | |
369 | UINT32 RDTSCP:1;\r | |
370 | ///\r | |
371 | /// [Bit 28] Reserved.\r | |
372 | ///\r | |
373 | UINT32 Reserved4:1;\r | |
374 | ///\r | |
375 | /// [Bit 29] Long Mode.\r | |
376 | ///\r | |
377 | UINT32 LM:1;\r | |
378 | ///\r | |
379 | /// [Bit 30] 3DNow! instructions.\r | |
380 | ///\r | |
381 | UINT32 ThreeDNow:1;\r | |
382 | ///\r | |
383 | /// [Bit 31] AMD Extensions to 3DNow! instructions.\r | |
384 | ///\r | |
385 | UINT32 ThreeDNowExt:1;\r | |
386 | } Bits;\r | |
387 | ///\r | |
388 | /// All bit fields as a 32-bit value\r | |
389 | ///\r | |
390 | UINT32 Uint32;\r | |
391 | } CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r | |
392 | \r | |
393 | \r | |
394 | /**\r | |
395 | CPUID Linear Physical Address Size\r | |
396 | \r | |
397 | @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r | |
b15cbd9c | 398 | \r |
890d2bd2 LD |
399 | @retval EAX Linear/Physical Address Size described by the type\r |
400 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.\r | |
401 | @retval EBX Linear/Physical Address Size described by the type\r | |
402 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.\r | |
403 | @retval ECX Linear/Physical Address Size described by the type\r | |
404 | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.\r | |
405 | @retval EDX Reserved.\r | |
406 | **/\r | |
407 | \r | |
408 | /**\r | |
409 | CPUID Linear Physical Address Size EAX for CPUID leaf\r | |
410 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
411 | **/\r | |
412 | typedef union {\r | |
413 | ///\r | |
414 | /// Individual bit fields\r | |
415 | ///\r | |
416 | struct {\r | |
417 | ///\r | |
418 | /// [Bits 7:0] Maximum physical byte address size in bits.\r | |
419 | ///\r | |
420 | UINT32 PhysicalAddressBits:8;\r | |
421 | ///\r | |
422 | /// [Bits 15:8] Maximum linear byte address size in bits.\r | |
423 | ///\r | |
424 | UINT32 LinearAddressBits:8;\r | |
425 | ///\r | |
426 | /// [Bits 23:16] Maximum guest physical byte address size in bits.\r | |
427 | ///\r | |
428 | UINT32 GuestPhysAddrSize:8;\r | |
429 | ///\r | |
430 | /// [Bit 31:24] Reserved.\r | |
431 | ///\r | |
432 | UINT32 Reserved:8;\r | |
433 | } Bits;\r | |
434 | ///\r | |
435 | /// All bit fields as a 32-bit value\r | |
436 | ///\r | |
437 | UINT32 Uint32;\r | |
438 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r | |
439 | \r | |
440 | /**\r | |
441 | CPUID Linear Physical Address Size EBX for CPUID leaf\r | |
442 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
443 | **/\r | |
444 | typedef union {\r | |
445 | ///\r | |
446 | /// Individual bit fields\r | |
447 | ///\r | |
448 | struct {\r | |
449 | ///\r | |
450 | /// [Bits 0] Clear Zero Instruction.\r | |
451 | ///\r | |
452 | UINT32 CLZERO:1;\r | |
453 | ///\r | |
454 | /// [Bits 1] Instructions retired count support.\r | |
455 | ///\r | |
456 | UINT32 IRPerf:1;\r | |
457 | ///\r | |
458 | /// [Bits 2] Restore error pointers for XSave instructions.\r | |
459 | ///\r | |
460 | UINT32 XSaveErPtr:1;\r | |
461 | ///\r | |
462 | /// [Bit 31:3] Reserved.\r | |
463 | ///\r | |
464 | UINT32 Reserved:29;\r | |
465 | } Bits;\r | |
466 | ///\r | |
467 | /// All bit fields as a 32-bit value\r | |
468 | ///\r | |
469 | UINT32 Uint32;\r | |
470 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r | |
471 | \r | |
472 | /**\r | |
473 | CPUID Linear Physical Address Size ECX for CPUID leaf\r | |
474 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
475 | **/\r | |
476 | typedef union {\r | |
477 | ///\r | |
478 | /// Individual bit fields\r | |
479 | ///\r | |
480 | struct {\r | |
481 | ///\r | |
482 | /// [Bits 7:0] Number of threads - 1.\r | |
483 | ///\r | |
484 | UINT32 NC:8;\r | |
485 | ///\r | |
486 | /// [Bit 11:8] Reserved.\r | |
487 | ///\r | |
488 | UINT32 Reserved1:4;\r | |
489 | ///\r | |
490 | /// [Bits 15:12] APIC ID size.\r | |
491 | ///\r | |
492 | UINT32 ApicIdCoreIdSize:4;\r | |
493 | ///\r | |
494 | /// [Bits 17:16] Performance time-stamp counter size.\r | |
495 | ///\r | |
496 | UINT32 PerfTscSize:2;\r | |
497 | ///\r | |
498 | /// [Bit 31:18] Reserved.\r | |
499 | ///\r | |
500 | UINT32 Reserved2:14;\r | |
501 | } Bits;\r | |
502 | ///\r | |
503 | /// All bit fields as a 32-bit value\r | |
504 | ///\r | |
505 | UINT32 Uint32;\r | |
506 | } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r | |
507 | \r | |
508 | \r | |
509 | /**\r | |
510 | CPUID AMD Processor Topology\r | |
511 | \r | |
512 | @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)\r | |
513 | \r | |
514 | @retval EAX Extended APIC ID described by the type\r | |
515 | CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.\r | |
516 | @retval EBX Core Indentifiers described by the type\r | |
517 | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.\r | |
518 | @retval ECX Node Indentifiers described by the type\r | |
519 | CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r | |
520 | @retval EDX Reserved.\r | |
521 | **/\r | |
522 | #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r | |
523 | \r | |
524 | /**\r | |
525 | CPUID AMD Processor Topology EAX for CPUID leaf\r | |
526 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
527 | **/\r | |
528 | typedef union {\r | |
529 | ///\r | |
530 | /// Individual bit fields\r | |
531 | ///\r | |
532 | struct {\r | |
533 | ///\r | |
534 | /// [Bit 31:0] Extended APIC Id.\r | |
535 | ///\r | |
536 | UINT32 ExtendedApicId;\r | |
537 | } Bits;\r | |
538 | ///\r | |
539 | /// All bit fields as a 32-bit value\r | |
540 | ///\r | |
541 | UINT32 Uint32;\r | |
542 | } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r | |
543 | \r | |
544 | /**\r | |
545 | CPUID AMD Processor Topology EBX for CPUID leaf\r | |
546 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
547 | **/\r | |
548 | typedef union {\r | |
549 | ///\r | |
550 | /// Individual bit fields\r | |
551 | ///\r | |
552 | struct {\r | |
553 | ///\r | |
554 | /// [Bits 7:0] Core Id.\r | |
555 | ///\r | |
556 | UINT32 CoreId:8;\r | |
557 | ///\r | |
558 | /// [Bits 15:8] Threads per core.\r | |
559 | ///\r | |
560 | UINT32 ThreadsPerCore:8;\r | |
561 | ///\r | |
562 | /// [Bit 31:16] Reserved.\r | |
563 | ///\r | |
564 | UINT32 Reserved:16;\r | |
565 | } Bits;\r | |
566 | ///\r | |
567 | /// All bit fields as a 32-bit value\r | |
568 | ///\r | |
569 | UINT32 Uint32;\r | |
570 | } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r | |
571 | \r | |
572 | /**\r | |
573 | CPUID AMD Processor Topology ECX for CPUID leaf\r | |
574 | #CPUID_AMD_PROCESSOR_TOPOLOGY.\r | |
575 | **/\r | |
576 | typedef union {\r | |
577 | ///\r | |
578 | /// Individual bit fields\r | |
579 | ///\r | |
580 | struct {\r | |
581 | ///\r | |
582 | /// [Bits 7:0] Node Id.\r | |
583 | ///\r | |
584 | UINT32 NodeId:8;\r | |
585 | ///\r | |
586 | /// [Bits 10:8] Nodes per processor.\r | |
587 | ///\r | |
588 | UINT32 NodesPerProcessor:3;\r | |
589 | ///\r | |
590 | /// [Bit 31:11] Reserved.\r | |
591 | ///\r | |
592 | UINT32 Reserved:21;\r | |
593 | } Bits;\r | |
594 | ///\r | |
595 | /// All bit fields as a 32-bit value\r | |
596 | ///\r | |
597 | UINT32 Uint32;\r | |
598 | } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r | |
599 | \r | |
600 | \r | |
601 | /**\r | |
602 | CPUID Memory Encryption Information\r | |
b15cbd9c BS |
603 | \r |
604 | @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r | |
605 | \r | |
606 | @retval EAX Returns the memory encryption feature support status.\r | |
607 | @retval EBX If memory encryption feature is present then return\r | |
608 | the page table bit number used to enable memory encryption support\r | |
609 | and reducing of physical address space in bits.\r | |
890d2bd2 LD |
610 | @retval ECX Returns number of encrypted guest supported simultaneously.\r |
611 | @retval EDX Returns minimum SEV enabled and SEV disabled ASID.\r | |
b15cbd9c BS |
612 | \r |
613 | <b>Example usage</b>\r | |
614 | @code\r | |
615 | UINT32 Eax;\r | |
616 | UINT32 Ebx;\r | |
617 | UINT32 Ecx;\r | |
618 | UINT32 Edx;\r | |
619 | \r | |
620 | AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r | |
621 | @endcode\r | |
622 | **/\r | |
623 | \r | |
624 | #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r | |
625 | \r | |
626 | /**\r | |
627 | CPUID Memory Encryption support information EAX for CPUID leaf\r | |
628 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
629 | **/\r | |
630 | typedef union {\r | |
631 | ///\r | |
632 | /// Individual bit fields\r | |
633 | ///\r | |
634 | struct {\r | |
635 | ///\r | |
636 | /// [Bit 0] Secure Memory Encryption (Sme) Support\r | |
637 | ///\r | |
638 | UINT32 SmeBit:1;\r | |
639 | \r | |
640 | ///\r | |
641 | /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r | |
642 | ///\r | |
643 | UINT32 SevBit:1;\r | |
644 | \r | |
645 | ///\r | |
646 | /// [Bit 2] Page flush MSR support\r | |
647 | ///\r | |
648 | UINT32 PageFlushMsrBit:1;\r | |
649 | \r | |
650 | ///\r | |
651 | /// [Bit 3] Encrypted state support\r | |
652 | ///\r | |
653 | UINT32 SevEsBit:1;\r | |
654 | \r | |
655 | ///\r | |
890d2bd2 | 656 | /// [Bit 31:4] Reserved\r |
b15cbd9c BS |
657 | ///\r |
658 | UINT32 ReservedBits:28;\r | |
659 | } Bits;\r | |
660 | ///\r | |
661 | /// All bit fields as a 32-bit value\r | |
662 | ///\r | |
663 | UINT32 Uint32;\r | |
664 | } CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r | |
665 | \r | |
666 | /**\r | |
667 | CPUID Memory Encryption support information EBX for CPUID leaf\r | |
668 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
669 | **/\r | |
670 | typedef union {\r | |
671 | ///\r | |
672 | /// Individual bit fields\r | |
673 | ///\r | |
674 | struct {\r | |
675 | ///\r | |
890d2bd2 | 676 | /// [Bit 5:0] Page table bit number used to enable memory encryption\r |
b15cbd9c BS |
677 | ///\r |
678 | UINT32 PtePosBits:6;\r | |
679 | \r | |
680 | ///\r | |
890d2bd2 LD |
681 | /// [Bit 11:6] Reduction of system physical address space bits when\r |
682 | /// memory encryption is enabled\r | |
b15cbd9c BS |
683 | ///\r |
684 | UINT32 ReducedPhysBits:5;\r | |
685 | \r | |
686 | ///\r | |
890d2bd2 | 687 | /// [Bit 31:12] Reserved\r |
b15cbd9c BS |
688 | ///\r |
689 | UINT32 ReservedBits:21;\r | |
690 | } Bits;\r | |
691 | ///\r | |
692 | /// All bit fields as a 32-bit value\r | |
693 | ///\r | |
694 | UINT32 Uint32;\r | |
695 | } CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r | |
696 | \r | |
697 | /**\r | |
698 | CPUID Memory Encryption support information ECX for CPUID leaf\r | |
699 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
700 | **/\r | |
701 | typedef union {\r | |
702 | ///\r | |
703 | /// Individual bit fields\r | |
704 | ///\r | |
705 | struct {\r | |
706 | ///\r | |
890d2bd2 | 707 | /// [Bit 31:0] Number of encrypted guest supported simultaneously\r |
b15cbd9c BS |
708 | ///\r |
709 | UINT32 NumGuests;\r | |
710 | } Bits;\r | |
711 | ///\r | |
712 | /// All bit fields as a 32-bit value\r | |
713 | ///\r | |
714 | UINT32 Uint32;\r | |
715 | } CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r | |
716 | \r | |
717 | /**\r | |
718 | CPUID Memory Encryption support information EDX for CPUID leaf\r | |
719 | #CPUID_MEMORY_ENCRYPTION_INFO.\r | |
720 | **/\r | |
721 | typedef union {\r | |
722 | ///\r | |
723 | /// Individual bit fields\r | |
724 | ///\r | |
725 | struct {\r | |
726 | ///\r | |
890d2bd2 | 727 | /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r |
b15cbd9c BS |
728 | ///\r |
729 | UINT32 MinAsid;\r | |
730 | } Bits;\r | |
731 | ///\r | |
732 | /// All bit fields as a 32-bit value\r | |
733 | ///\r | |
734 | UINT32 Uint32;\r | |
735 | } CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r | |
736 | \r | |
737 | #endif\r |