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1 | /** @file\r |
2 | MSR Definitions.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r | |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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11 | \r |
12 | @par Specification Reference:\r | |
13 | AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
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17 | #ifndef __FAM17_MSR_H__\r |
18 | #define __FAM17_MSR_H__\r | |
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19 | \r |
20 | /**\r | |
21 | Secure Encrypted Virtualization (SEV) status register\r | |
22 | \r | |
23 | **/\r | |
24 | #define MSR_SEV_STATUS 0xc0010131\r | |
25 | \r | |
26 | /**\r | |
27 | MSR information returned for #MSR_SEV_STATUS\r | |
28 | **/\r | |
29 | typedef union {\r | |
30 | ///\r | |
31 | /// Individual bit fields\r | |
32 | ///\r | |
33 | struct {\r | |
34 | ///\r | |
35 | /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r | |
36 | ///\r | |
37 | UINT32 SevBit:1;\r | |
38 | \r | |
39 | ///\r | |
40 | /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r | |
41 | ///\r | |
42 | UINT32 SevEsBit:1;\r | |
43 | \r | |
44 | UINT32 Reserved:30;\r | |
45 | } Bits;\r | |
46 | ///\r | |
47 | /// All bit fields as a 32-bit value\r | |
48 | ///\r | |
49 | UINT32 Uint32;\r | |
50 | ///\r | |
51 | /// All bit fields as a 64-bit value\r | |
52 | ///\r | |
53 | UINT64 Uint64;\r | |
54 | } MSR_SEV_STATUS_REGISTER;\r | |
55 | \r | |
56 | #endif\r |