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878ddf1f | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
9f84a609 | 15 | /**\r |
16 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
17 | calling CPU.\r | |
18 | \r | |
19 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
20 | calling CPU.\r | |
21 | \r | |
22 | **/\r | |
878ddf1f | 23 | VOID\r |
24 | EFIAPI\r | |
25 | InvalidateInstructionCache (\r | |
26 | VOID\r | |
27 | )\r | |
28 | {\r | |
29 | }\r | |
30 | \r | |
9f84a609 | 31 | /**\r |
32 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
33 | of the calling CPU.\r | |
34 | \r | |
35 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
36 | Address is not aligned on a cache line boundary, then entire instruction\r | |
37 | cache line containing Address is invalidated. If Address + Length is not\r | |
38 | aligned on a cache line boundary, then the entire instruction cache line\r | |
39 | containing Address + Length -1 is invalidated. This function may choose to\r | |
40 | invalidate the entire instruction cache if that is more efficient than\r | |
41 | invalidating the specified range. If Length is 0, the no instruction cache\r | |
42 | lines are invalidated. Address is returned.\r | |
43 | \r | |
44 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
45 | \r | |
46 | @param Address The base address of the instruction cache lines to\r | |
47 | invalidate. If the CPU is in a physical addressing mode, then\r | |
48 | Address is a physical address. If the CPU is in a virtual\r | |
49 | addressing mode, then Address is a virtual address.\r | |
50 | \r | |
51 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
52 | \r | |
53 | @return Address\r | |
54 | \r | |
55 | **/\r | |
878ddf1f | 56 | VOID *\r |
57 | EFIAPI\r | |
58 | InvalidateInstructionCacheRange (\r | |
59 | IN VOID *Address,\r | |
60 | IN UINTN Length\r | |
61 | )\r | |
62 | {\r | |
9f84a609 | 63 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
878ddf1f | 64 | return Address;\r |
65 | }\r | |
66 | \r | |
9f84a609 | 67 | /**\r |
68 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
69 | of the calling CPU.\r | |
70 | \r | |
71 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
72 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
73 | written back to system memory, and also invalidates all the data cache lines\r | |
74 | in the cache coherency domain of the calling CPU.\r | |
75 | \r | |
76 | **/\r | |
878ddf1f | 77 | VOID\r |
78 | EFIAPI\r | |
79 | WriteBackInvalidateDataCache (\r | |
80 | VOID\r | |
81 | )\r | |
82 | {\r | |
83 | }\r | |
84 | \r | |
9f84a609 | 85 | /**\r |
86 | Writes Back and Invalidates a range of data cache lines in the cache\r | |
87 | coherency domain of the calling CPU.\r | |
88 | \r | |
89 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
90 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
91 | cache line containing Address is written back and invalidated. If Address +\r | |
92 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
93 | line containing Address + Length -1 is written back and invalidated. This\r | |
94 | function may choose to write back and invalidate the entire data cache if\r | |
95 | that is more efficient than writing back and invalidating the specified\r | |
96 | range. If Length is 0, the no data cache lines are written back and\r | |
97 | invalidated. Address is returned.\r | |
98 | \r | |
99 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
100 | \r | |
101 | @param Address The base address of the data cache lines to write back and\r | |
102 | invalidate. If the CPU is in a physical addressing mode, then\r | |
103 | Address is a physical address. If the CPU is in a virtual\r | |
104 | addressing mode, then Address is a virtual address.\r | |
105 | @param Length The number of bytes to write back and invalidate from the\r | |
106 | data cache.\r | |
107 | \r | |
108 | @return Address\r | |
109 | \r | |
110 | **/\r | |
878ddf1f | 111 | VOID *\r |
112 | EFIAPI\r | |
113 | WriteBackInvalidateDataCacheRange (\r | |
114 | IN VOID *Address,\r | |
115 | IN UINTN Length\r | |
116 | )\r | |
117 | {\r | |
9f84a609 | 118 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
878ddf1f | 119 | return Address;\r |
120 | }\r | |
121 | \r | |
9f84a609 | 122 | /**\r |
123 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
124 | CPU.\r | |
125 | \r | |
126 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
127 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
128 | system memory. This function may also invalidate all the data cache lines in\r | |
129 | the cache coherency domain of the calling CPU.\r | |
130 | \r | |
131 | **/\r | |
878ddf1f | 132 | VOID\r |
133 | EFIAPI\r | |
134 | WriteBackDataCache (\r | |
135 | VOID\r | |
136 | )\r | |
137 | {\r | |
138 | }\r | |
139 | \r | |
9f84a609 | 140 | /**\r |
141 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
142 | calling CPU.\r | |
143 | \r | |
144 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
145 | is not aligned on a cache line boundary, then entire data cache line\r | |
146 | containing Address is written back. If Address + Length is not aligned on a\r | |
147 | cache line boundary, then the entire data cache line containing Address +\r | |
148 | Length -1 is written back. This function may choose to write back the entire\r | |
149 | data cache if that is more efficient than writing back the specified range.\r | |
150 | If Length is 0, the no data cache lines are written back. This function may\r | |
151 | also invalidate all the data cache lines in the specified range of the cache\r | |
152 | coherency domain of the calling CPU. Address is returned.\r | |
153 | \r | |
154 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
155 | \r | |
156 | @param Address The base address of the data cache lines to write back. If\r | |
157 | the CPU is in a physical addressing mode, then Address is a\r | |
158 | physical address. If the CPU is in a virtual addressing\r | |
159 | mode, then Address is a virtual address.\r | |
160 | @param Length The number of bytes to write back from the data cache.\r | |
161 | \r | |
162 | @return Address\r | |
163 | \r | |
164 | **/\r | |
878ddf1f | 165 | VOID *\r |
166 | EFIAPI\r | |
167 | WriteBackDataCacheRange (\r | |
168 | IN VOID *Address,\r | |
169 | IN UINTN Length\r | |
170 | )\r | |
171 | {\r | |
9f84a609 | 172 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
878ddf1f | 173 | return Address;\r |
174 | }\r | |
175 | \r | |
9f84a609 | 176 | /**\r |
177 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
178 | CPU.\r | |
179 | \r | |
180 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
181 | CPU. This function must be used with care because dirty cache lines are not\r | |
182 | written back to system memory. It is typically used for cache diagnostics. If\r | |
183 | the CPU does not support invalidation of the entire data cache, then a write\r | |
184 | back and invalidate operation should be performed on the entire data cache.\r | |
185 | \r | |
186 | **/\r | |
878ddf1f | 187 | VOID\r |
188 | EFIAPI\r | |
189 | InvalidateDataCache (\r | |
190 | VOID\r | |
191 | )\r | |
192 | {\r | |
193 | }\r | |
194 | \r | |
9f84a609 | 195 | /**\r |
196 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
197 | calling CPU.\r | |
198 | \r | |
199 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
200 | is not aligned on a cache line boundary, then entire data cache line\r | |
201 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
202 | cache line boundary, then the entire data cache line containing Address +\r | |
203 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
204 | outside the specified range. If Length is 0, the no data cache lines are\r | |
205 | invalidated. Address is returned. This function must be used with care\r | |
206 | because dirty cache lines are not written back to system memory. It is\r | |
207 | typically used for cache diagnostics. If the CPU does not support\r | |
208 | invalidation of a data cache range, then a write back and invalidate\r | |
209 | operation should be performed on the data cache range.\r | |
210 | \r | |
211 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
212 | \r | |
213 | @param Address The base address of the data cache lines to invalidate. If\r | |
214 | the CPU is in a physical addressing mode, then Address is a\r | |
215 | physical address. If the CPU is in a virtual addressing mode,\r | |
216 | then Address is a virtual address.\r | |
217 | @param Length The number of bytes to invalidate from the data cache.\r | |
218 | \r | |
219 | @return Address\r | |
220 | \r | |
221 | **/\r | |
878ddf1f | 222 | VOID *\r |
223 | EFIAPI\r | |
224 | InvalidateDataCacheRange (\r | |
225 | IN VOID *Address,\r | |
226 | IN UINTN Length\r | |
227 | )\r | |
228 | {\r | |
9f84a609 | 229 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
878ddf1f | 230 | return Address;\r |
231 | }\r |