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e1f414b6 | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
2f7c0ad1 HT |
4 | Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
e1f414b6 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
35a17154 | 8 | http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
f734a10a A |
15 | #include <Base.h>\r |
16 | #include <Library/DebugLib.h>\r | |
e1f414b6 | 17 | \r |
18 | /**\r | |
19 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
20 | calling CPU.\r | |
21 | \r | |
e1f414b6 | 22 | **/\r |
23 | VOID\r | |
24 | EFIAPI\r | |
25 | InvalidateInstructionCache (\r | |
26 | VOID\r | |
27 | )\r | |
28 | {\r | |
29 | }\r | |
30 | \r | |
31 | /**\r | |
32 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
33 | of the calling CPU.\r | |
34 | \r | |
35 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
36 | Address is not aligned on a cache line boundary, then entire instruction\r | |
37 | cache line containing Address is invalidated. If Address + Length is not\r | |
38 | aligned on a cache line boundary, then the entire instruction cache line\r | |
39 | containing Address + Length -1 is invalidated. This function may choose to\r | |
40 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 41 | invalidating the specified range. If Length is 0, then no instruction cache\r |
e1f414b6 | 42 | lines are invalidated. Address is returned.\r |
43 | \r | |
44 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
45 | \r | |
46 | @param Address The base address of the instruction cache lines to\r | |
47 | invalidate. If the CPU is in a physical addressing mode, then\r | |
48 | Address is a physical address. If the CPU is in a virtual\r | |
49 | addressing mode, then Address is a virtual address.\r | |
50 | \r | |
51 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
52 | \r | |
eb1c78db | 53 | @return Address.\r |
e1f414b6 | 54 | \r |
55 | **/\r | |
56 | VOID *\r | |
57 | EFIAPI\r | |
58 | InvalidateInstructionCacheRange (\r | |
59 | IN VOID *Address,\r | |
60 | IN UINTN Length\r | |
61 | )\r | |
62 | {\r | |
63 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
64 | return Address;\r | |
65 | }\r | |
66 | \r | |
67 | /**\r | |
35a17154 | 68 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 69 | of the calling CPU.\r |
70 | \r | |
35a17154 | 71 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 72 | of the calling CPU. This function guarantees that all dirty cache lines are\r |
73 | written back to system memory, and also invalidates all the data cache lines\r | |
74 | in the cache coherency domain of the calling CPU.\r | |
75 | \r | |
76 | **/\r | |
77 | VOID\r | |
78 | EFIAPI\r | |
79 | WriteBackInvalidateDataCache (\r | |
80 | VOID\r | |
81 | )\r | |
82 | {\r | |
83 | }\r | |
84 | \r | |
85 | /**\r | |
35a17154 | 86 | Writes back and invalidates a range of data cache lines in the cache\r |
e1f414b6 | 87 | coherency domain of the calling CPU.\r |
88 | \r | |
89 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
90 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
91 | cache line containing Address is written back and invalidated. If Address +\r | |
92 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
93 | line containing Address + Length -1 is written back and invalidated. This\r | |
94 | function may choose to write back and invalidate the entire data cache if\r | |
95 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 96 | range. If Length is 0, then no data cache lines are written back and\r |
e1f414b6 | 97 | invalidated. Address is returned.\r |
98 | \r | |
99 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
100 | \r | |
101 | @param Address The base address of the data cache lines to write back and\r | |
102 | invalidate. If the CPU is in a physical addressing mode, then\r | |
103 | Address is a physical address. If the CPU is in a virtual\r | |
104 | addressing mode, then Address is a virtual address.\r | |
105 | @param Length The number of bytes to write back and invalidate from the\r | |
106 | data cache.\r | |
107 | \r | |
38bbd3d9 | 108 | @return Address of cache invalidation.\r |
e1f414b6 | 109 | \r |
110 | **/\r | |
111 | VOID *\r | |
112 | EFIAPI\r | |
113 | WriteBackInvalidateDataCacheRange (\r | |
114 | IN VOID *Address,\r | |
115 | IN UINTN Length\r | |
116 | )\r | |
117 | {\r | |
118 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
119 | return Address;\r | |
120 | }\r | |
121 | \r | |
122 | /**\r | |
35a17154 | 123 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 124 | CPU.\r |
125 | \r | |
35a17154 | 126 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 127 | CPU. This function guarantees that all dirty cache lines are written back to\r |
128 | system memory. This function may also invalidate all the data cache lines in\r | |
129 | the cache coherency domain of the calling CPU.\r | |
130 | \r | |
131 | **/\r | |
132 | VOID\r | |
133 | EFIAPI\r | |
134 | WriteBackDataCache (\r | |
135 | VOID\r | |
136 | )\r | |
137 | {\r | |
138 | }\r | |
139 | \r | |
140 | /**\r | |
35a17154 | 141 | Writes back a range of data cache lines in the cache coherency domain of the\r |
e1f414b6 | 142 | calling CPU.\r |
143 | \r | |
35a17154 | 144 | Writes back the data cache lines specified by Address and Length. If Address\r |
e1f414b6 | 145 | is not aligned on a cache line boundary, then entire data cache line\r |
146 | containing Address is written back. If Address + Length is not aligned on a\r | |
147 | cache line boundary, then the entire data cache line containing Address +\r | |
148 | Length -1 is written back. This function may choose to write back the entire\r | |
149 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 150 | If Length is 0, then no data cache lines are written back. This function may\r |
e1f414b6 | 151 | also invalidate all the data cache lines in the specified range of the cache\r |
152 | coherency domain of the calling CPU. Address is returned.\r | |
153 | \r | |
154 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
155 | \r | |
156 | @param Address The base address of the data cache lines to write back. If\r | |
157 | the CPU is in a physical addressing mode, then Address is a\r | |
158 | physical address. If the CPU is in a virtual addressing\r | |
159 | mode, then Address is a virtual address.\r | |
160 | @param Length The number of bytes to write back from the data cache.\r | |
161 | \r | |
ad400b07 | 162 | @return Address of cache written in main memory.\r |
e1f414b6 | 163 | \r |
164 | **/\r | |
165 | VOID *\r | |
166 | EFIAPI\r | |
167 | WriteBackDataCacheRange (\r | |
168 | IN VOID *Address,\r | |
169 | IN UINTN Length\r | |
170 | )\r | |
171 | {\r | |
172 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
173 | return Address;\r | |
174 | }\r | |
175 | \r | |
176 | /**\r | |
177 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
178 | CPU.\r | |
179 | \r | |
180 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
181 | CPU. This function must be used with care because dirty cache lines are not\r | |
182 | written back to system memory. It is typically used for cache diagnostics. If\r | |
183 | the CPU does not support invalidation of the entire data cache, then a write\r | |
184 | back and invalidate operation should be performed on the entire data cache.\r | |
185 | \r | |
186 | **/\r | |
187 | VOID\r | |
188 | EFIAPI\r | |
189 | InvalidateDataCache (\r | |
190 | VOID\r | |
191 | )\r | |
192 | {\r | |
193 | }\r | |
194 | \r | |
195 | /**\r | |
196 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
197 | calling CPU.\r | |
198 | \r | |
199 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
200 | is not aligned on a cache line boundary, then entire data cache line\r | |
201 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
202 | cache line boundary, then the entire data cache line containing Address +\r | |
203 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 204 | outside the specified range. If Length is 0, then no data cache lines are\r |
e1f414b6 | 205 | invalidated. Address is returned. This function must be used with care\r |
206 | because dirty cache lines are not written back to system memory. It is\r | |
207 | typically used for cache diagnostics. If the CPU does not support\r | |
208 | invalidation of a data cache range, then a write back and invalidate\r | |
209 | operation should be performed on the data cache range.\r | |
210 | \r | |
211 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
212 | \r | |
213 | @param Address The base address of the data cache lines to invalidate. If\r | |
214 | the CPU is in a physical addressing mode, then Address is a\r | |
215 | physical address. If the CPU is in a virtual addressing mode,\r | |
216 | then Address is a virtual address.\r | |
217 | @param Length The number of bytes to invalidate from the data cache.\r | |
218 | \r | |
eb1c78db | 219 | @return Address.\r |
e1f414b6 | 220 | \r |
221 | **/\r | |
222 | VOID *\r | |
223 | EFIAPI\r | |
224 | InvalidateDataCacheRange (\r | |
225 | IN VOID *Address,\r | |
226 | IN UINTN Length\r | |
227 | )\r | |
228 | {\r | |
229 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r | |
230 | return Address;\r | |
231 | }\r |