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e1f414b6 | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
2f7c0ad1 HT |
4 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
e1f414b6 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
35a17154 | 8 | http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
f734a10a | 15 | #include <Base.h>\r |
a73480f6 | 16 | #include <Library/CacheMaintenanceLib.h>\r |
f734a10a A |
17 | #include <Library/BaseLib.h>\r |
18 | #include <Library/DebugLib.h>\r | |
fa73b3be | 19 | #include <Library/PalLib.h>\r |
e1f414b6 | 20 | \r |
21 | /**\r | |
22 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
23 | calling CPU.\r | |
24 | \r | |
e1f414b6 | 25 | **/\r |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | InvalidateInstructionCache (\r | |
29 | VOID\r | |
30 | )\r | |
31 | {\r | |
ad400b07 | 32 | PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r |
e1f414b6 | 33 | }\r |
34 | \r | |
35 | /**\r | |
36 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
37 | of the calling CPU.\r | |
38 | \r | |
39 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
40 | Address is not aligned on a cache line boundary, then entire instruction\r | |
41 | cache line containing Address is invalidated. If Address + Length is not\r | |
42 | aligned on a cache line boundary, then the entire instruction cache line\r | |
43 | containing Address + Length -1 is invalidated. This function may choose to\r | |
44 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 45 | invalidating the specified range. If Length is 0, then no instruction cache\r |
e1f414b6 | 46 | lines are invalidated. Address is returned.\r |
47 | \r | |
48 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
49 | \r | |
50 | @param Address The base address of the instruction cache lines to\r | |
51 | invalidate. If the CPU is in a physical addressing mode, then\r | |
52 | Address is a physical address. If the CPU is in a virtual\r | |
53 | addressing mode, then Address is a virtual address.\r | |
54 | \r | |
55 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
56 | \r | |
eb1c78db | 57 | @return Address.\r |
e1f414b6 | 58 | \r |
59 | **/\r | |
60 | VOID *\r | |
61 | EFIAPI\r | |
62 | InvalidateInstructionCacheRange (\r | |
63 | IN VOID *Address,\r | |
64 | IN UINTN Length\r | |
65 | )\r | |
66 | {\r | |
cc39b88b | 67 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 68 | }\r |
69 | \r | |
70 | /**\r | |
35a17154 | 71 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 72 | of the calling CPU.\r |
73 | \r | |
35a17154 | 74 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 75 | of the calling CPU. This function guarantees that all dirty cache lines are\r |
76 | written back to system memory, and also invalidates all the data cache lines\r | |
77 | in the cache coherency domain of the calling CPU.\r | |
78 | \r | |
79 | **/\r | |
80 | VOID\r | |
81 | EFIAPI\r | |
82 | WriteBackInvalidateDataCache (\r | |
83 | VOID\r | |
84 | )\r | |
85 | {\r | |
ad400b07 | 86 | PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r |
e1f414b6 | 87 | }\r |
88 | \r | |
89 | /**\r | |
35a17154 | 90 | Writes back and invalidates a range of data cache lines in the cache\r |
e1f414b6 | 91 | coherency domain of the calling CPU.\r |
92 | \r | |
35a17154 | 93 | Writes back and invalidates the data cache lines specified by Address and\r |
e1f414b6 | 94 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
95 | cache line containing Address is written back and invalidated. If Address +\r | |
96 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
97 | line containing Address + Length -1 is written back and invalidated. This\r | |
98 | function may choose to write back and invalidate the entire data cache if\r | |
99 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 100 | range. If Length is 0, then no data cache lines are written back and\r |
e1f414b6 | 101 | invalidated. Address is returned.\r |
102 | \r | |
103 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
104 | \r | |
105 | @param Address The base address of the data cache lines to write back and\r | |
106 | invalidate. If the CPU is in a physical addressing mode, then\r | |
107 | Address is a physical address. If the CPU is in a virtual\r | |
108 | addressing mode, then Address is a virtual address.\r | |
109 | @param Length The number of bytes to write back and invalidate from the\r | |
110 | data cache.\r | |
111 | \r | |
38bbd3d9 | 112 | @return Address of cache invalidation.\r |
e1f414b6 | 113 | \r |
114 | **/\r | |
115 | VOID *\r | |
116 | EFIAPI\r | |
117 | WriteBackInvalidateDataCacheRange (\r | |
118 | IN VOID *Address,\r | |
119 | IN UINTN Length\r | |
120 | )\r | |
121 | {\r | |
cc39b88b | 122 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 123 | }\r |
124 | \r | |
125 | /**\r | |
126 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
127 | CPU.\r | |
128 | \r | |
129 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
130 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
131 | system memory. This function may also invalidate all the data cache lines in\r | |
132 | the cache coherency domain of the calling CPU.\r | |
133 | \r | |
134 | **/\r | |
135 | VOID\r | |
136 | EFIAPI\r | |
137 | WriteBackDataCache (\r | |
138 | VOID\r | |
139 | )\r | |
140 | {\r | |
4199d92d | 141 | PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);\r |
e1f414b6 | 142 | }\r |
143 | \r | |
144 | /**\r | |
145 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
146 | calling CPU.\r | |
147 | \r | |
148 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
149 | is not aligned on a cache line boundary, then entire data cache line\r | |
150 | containing Address is written back. If Address + Length is not aligned on a\r | |
151 | cache line boundary, then the entire data cache line containing Address +\r | |
152 | Length -1 is written back. This function may choose to write back the entire\r | |
153 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 154 | If Length is 0, then no data cache lines are written back. This function may\r |
e1f414b6 | 155 | also invalidate all the data cache lines in the specified range of the cache\r |
156 | coherency domain of the calling CPU. Address is returned.\r | |
157 | \r | |
158 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
159 | \r | |
160 | @param Address The base address of the data cache lines to write back. If\r | |
161 | the CPU is in a physical addressing mode, then Address is a\r | |
162 | physical address. If the CPU is in a virtual addressing\r | |
163 | mode, then Address is a virtual address.\r | |
164 | @param Length The number of bytes to write back from the data cache.\r | |
165 | \r | |
ad400b07 | 166 | @return Address of cache written in main memory.\r |
e1f414b6 | 167 | \r |
168 | **/\r | |
169 | VOID *\r | |
170 | EFIAPI\r | |
171 | WriteBackDataCacheRange (\r | |
172 | IN VOID *Address,\r | |
173 | IN UINTN Length\r | |
174 | )\r | |
175 | {\r | |
cc39b88b | 176 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 177 | }\r |
178 | \r | |
179 | /**\r | |
180 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
181 | CPU.\r | |
182 | \r | |
183 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
184 | CPU. This function must be used with care because dirty cache lines are not\r | |
185 | written back to system memory. It is typically used for cache diagnostics. If\r | |
186 | the CPU does not support invalidation of the entire data cache, then a write\r | |
187 | back and invalidate operation should be performed on the entire data cache.\r | |
188 | \r | |
189 | **/\r | |
190 | VOID\r | |
191 | EFIAPI\r | |
192 | InvalidateDataCache (\r | |
193 | VOID\r | |
194 | )\r | |
195 | {\r | |
ad400b07 | 196 | //\r |
35a17154 | 197 | // Invalidation of the entire data cache without writing back is not supported \r |
198 | // on IPF architecture, so a write back and invalidate operation is performed.\r | |
ad400b07 | 199 | //\r |
e1f414b6 | 200 | WriteBackInvalidateDataCache ();\r |
201 | }\r | |
202 | \r | |
203 | /**\r | |
204 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
205 | calling CPU.\r | |
206 | \r | |
207 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
208 | is not aligned on a cache line boundary, then entire data cache line\r | |
209 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
210 | cache line boundary, then the entire data cache line containing Address +\r | |
211 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 212 | outside the specified range. If Length is 0, then no data cache lines are\r |
e1f414b6 | 213 | invalidated. Address is returned. This function must be used with care\r |
214 | because dirty cache lines are not written back to system memory. It is\r | |
215 | typically used for cache diagnostics. If the CPU does not support\r | |
216 | invalidation of a data cache range, then a write back and invalidate\r | |
217 | operation should be performed on the data cache range.\r | |
218 | \r | |
219 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
220 | \r | |
221 | @param Address The base address of the data cache lines to invalidate. If\r | |
222 | the CPU is in a physical addressing mode, then Address is a\r | |
223 | physical address. If the CPU is in a virtual addressing mode,\r | |
224 | then Address is a virtual address.\r | |
225 | @param Length The number of bytes to invalidate from the data cache.\r | |
226 | \r | |
eb1c78db | 227 | @return Address.\r |
e1f414b6 | 228 | \r |
229 | **/\r | |
230 | VOID *\r | |
231 | EFIAPI\r | |
232 | InvalidateDataCacheRange (\r | |
233 | IN VOID *Address,\r | |
234 | IN UINTN Length\r | |
235 | )\r | |
236 | {\r | |
ad400b07 | 237 | //\r |
238 | // Invalidation of a data cache range without writing back is not supported on\r | |
239 | // IPF architecture, so write back and invalidate operation is performed.\r | |
240 | //\r | |
cc39b88b | 241 | return AsmFlushCacheRange (Address, Length);\r |
e1f414b6 | 242 | }\r |