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878ddf1f | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | typedef struct {\r | |
16 | UINT64 Status;\r | |
17 | UINT64 r9;\r | |
18 | UINT64 r10;\r | |
19 | UINT64 r11;\r | |
20 | } PAL_PROC_RETURN;\r | |
21 | \r | |
22 | PAL_PROC_RETURN\r | |
e65e8d10 | 23 | PalCallStatic (\r |
24 | IN CONST VOID *PalEntryPoint,\r | |
878ddf1f | 25 | IN UINT64 Arg1,\r |
26 | IN UINT64 Arg2,\r | |
27 | IN UINT64 Arg3,\r | |
28 | IN UINT64 Arg4\r | |
29 | );\r | |
30 | \r | |
9f84a609 | 31 | /**\r |
32 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
33 | calling CPU.\r | |
34 | \r | |
35 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
36 | calling CPU.\r | |
37 | \r | |
38 | **/\r | |
878ddf1f | 39 | VOID\r |
40 | EFIAPI\r | |
41 | InvalidateInstructionCache (\r | |
42 | VOID\r | |
43 | )\r | |
44 | {\r | |
e65e8d10 | 45 | PalCallStatic (NULL, 1, 1, 1, 0);\r |
9f84a609 | 46 | }\r |
47 | \r | |
48 | /**\r | |
49 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
50 | of the calling CPU.\r | |
51 | \r | |
52 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
53 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
54 | written back to system memory, and also invalidates all the data cache lines\r | |
55 | in the cache coherency domain of the calling CPU.\r | |
56 | \r | |
57 | **/\r | |
878ddf1f | 58 | VOID\r |
59 | EFIAPI\r | |
60 | WriteBackInvalidateDataCache (\r | |
61 | VOID\r | |
62 | )\r | |
63 | {\r | |
e65e8d10 | 64 | PalCallStatic (NULL, 1, 2, 1, 0);\r |
878ddf1f | 65 | }\r |
66 | \r | |
9f84a609 | 67 | /**\r |
68 | Writes Back and Invalidates a range of data cache lines in the cache\r | |
69 | coherency domain of the calling CPU.\r | |
70 | \r | |
71 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
72 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
73 | cache line containing Address is written back and invalidated. If Address +\r | |
74 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
75 | line containing Address + Length -1 is written back and invalidated. This\r | |
76 | function may choose to write back and invalidate the entire data cache if\r | |
77 | that is more efficient than writing back and invalidating the specified\r | |
78 | range. If Length is 0, the no data cache lines are written back and\r | |
79 | invalidated. Address is returned.\r | |
80 | \r | |
81 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
82 | \r | |
83 | @param Address The base address of the data cache lines to write back and\r | |
84 | invalidate. If the CPU is in a physical addressing mode, then\r | |
85 | Address is a physical address. If the CPU is in a virtual\r | |
86 | addressing mode, then Address is a virtual address.\r | |
87 | @param Length The number of bytes to write back and invalidate from the\r | |
88 | data cache.\r | |
89 | \r | |
90 | @return Address\r | |
91 | \r | |
92 | **/\r | |
878ddf1f | 93 | VOID *\r |
94 | EFIAPI\r | |
95 | WriteBackInvalidateDataCacheRange (\r | |
96 | IN VOID *Address,\r | |
97 | IN UINTN Length\r | |
98 | )\r | |
99 | {\r | |
9f84a609 | 100 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
101 | \r | |
102 | if (Length > 0) {\r | |
103 | WriteBackInvalidateDataCache ();\r | |
104 | }\r | |
878ddf1f | 105 | return Address;\r |
106 | }\r | |
107 | \r | |
9f84a609 | 108 | /**\r |
109 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
110 | CPU.\r | |
111 | \r | |
112 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
113 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
114 | system memory. This function may also invalidate all the data cache lines in\r | |
115 | the cache coherency domain of the calling CPU.\r | |
116 | \r | |
117 | **/\r | |
878ddf1f | 118 | VOID\r |
119 | EFIAPI\r | |
120 | WriteBackDataCache (\r | |
121 | VOID\r | |
122 | )\r | |
123 | {\r | |
e65e8d10 | 124 | PalCallStatic (NULL, 1, 2, 0, 0);\r |
878ddf1f | 125 | }\r |
126 | \r | |
9f84a609 | 127 | /**\r |
128 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
129 | calling CPU.\r | |
130 | \r | |
131 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
132 | is not aligned on a cache line boundary, then entire data cache line\r | |
133 | containing Address is written back. If Address + Length is not aligned on a\r | |
134 | cache line boundary, then the entire data cache line containing Address +\r | |
135 | Length -1 is written back. This function may choose to write back the entire\r | |
136 | data cache if that is more efficient than writing back the specified range.\r | |
137 | If Length is 0, the no data cache lines are written back. This function may\r | |
138 | also invalidate all the data cache lines in the specified range of the cache\r | |
139 | coherency domain of the calling CPU. Address is returned.\r | |
140 | \r | |
141 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
142 | \r | |
143 | @param Address The base address of the data cache lines to write back. If\r | |
144 | the CPU is in a physical addressing mode, then Address is a\r | |
145 | physical address. If the CPU is in a virtual addressing\r | |
146 | mode, then Address is a virtual address.\r | |
147 | @param Length The number of bytes to write back from the data cache.\r | |
148 | \r | |
149 | @return Address\r | |
150 | \r | |
151 | **/\r | |
878ddf1f | 152 | VOID *\r |
153 | EFIAPI\r | |
154 | WriteBackDataCacheRange (\r | |
155 | IN VOID *Address,\r | |
156 | IN UINTN Length\r | |
157 | )\r | |
158 | {\r | |
9f84a609 | 159 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
160 | \r | |
161 | if (Length > 0) {\r | |
162 | WriteBackDataCache ();\r | |
163 | }\r | |
878ddf1f | 164 | return Address;\r |
165 | }\r | |
166 | \r | |
9f84a609 | 167 | /**\r |
168 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
169 | CPU.\r | |
170 | \r | |
171 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
172 | CPU. This function must be used with care because dirty cache lines are not\r | |
173 | written back to system memory. It is typically used for cache diagnostics. If\r | |
174 | the CPU does not support invalidation of the entire data cache, then a write\r | |
175 | back and invalidate operation should be performed on the entire data cache.\r | |
176 | \r | |
177 | **/\r | |
878ddf1f | 178 | VOID\r |
179 | EFIAPI\r | |
180 | InvalidateDataCache (\r | |
181 | VOID\r | |
182 | )\r | |
183 | {\r | |
9f84a609 | 184 | WriteBackInvalidateDataCache ();\r |
878ddf1f | 185 | }\r |
186 | \r | |
9f84a609 | 187 | /**\r |
188 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
189 | calling CPU.\r | |
190 | \r | |
191 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
192 | is not aligned on a cache line boundary, then entire data cache line\r | |
193 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
194 | cache line boundary, then the entire data cache line containing Address +\r | |
195 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
196 | outside the specified range. If Length is 0, the no data cache lines are\r | |
197 | invalidated. Address is returned. This function must be used with care\r | |
198 | because dirty cache lines are not written back to system memory. It is\r | |
199 | typically used for cache diagnostics. If the CPU does not support\r | |
200 | invalidation of a data cache range, then a write back and invalidate\r | |
201 | operation should be performed on the data cache range.\r | |
202 | \r | |
203 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
204 | \r | |
205 | @param Address The base address of the data cache lines to invalidate. If\r | |
206 | the CPU is in a physical addressing mode, then Address is a\r | |
207 | physical address. If the CPU is in a virtual addressing mode,\r | |
208 | then Address is a virtual address.\r | |
209 | @param Length The number of bytes to invalidate from the data cache.\r | |
210 | \r | |
211 | @return Address\r | |
212 | \r | |
213 | **/\r | |
878ddf1f | 214 | VOID *\r |
215 | EFIAPI\r | |
216 | InvalidateDataCacheRange (\r | |
217 | IN VOID *Address,\r | |
218 | IN UINTN Length\r | |
219 | )\r | |
220 | {\r | |
9f84a609 | 221 | return WriteBackInvalidateDataCacheRange (Address, Length);\r |
878ddf1f | 222 | }\r |