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e1f414b6 | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
2f7c0ad1 | 5 | This program and the accompanying materials\r |
e1f414b6 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
35a17154 | 8 | http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 9 | \r |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
e1f414b6 | 13 | \r |
14 | **/\r | |
15 | \r | |
f734a10a A |
16 | #include <Base.h>\r |
17 | #include <Library/BaseLib.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
e1f414b6 | 19 | \r |
e1f414b6 | 20 | /**\r |
21 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
22 | calling CPU.\r | |
23 | \r | |
e1f414b6 | 24 | **/\r |
25 | VOID\r | |
26 | EFIAPI\r | |
27 | InvalidateInstructionCache (\r | |
28 | VOID\r | |
29 | )\r | |
30 | {\r | |
31 | }\r | |
32 | \r | |
33 | /**\r | |
34 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
35 | of the calling CPU.\r | |
36 | \r | |
37 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
38 | Address is not aligned on a cache line boundary, then entire instruction\r | |
39 | cache line containing Address is invalidated. If Address + Length is not\r | |
40 | aligned on a cache line boundary, then the entire instruction cache line\r | |
41 | containing Address + Length -1 is invalidated. This function may choose to\r | |
42 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 43 | invalidating the specified range. If Length is 0, then no instruction cache\r |
e1f414b6 | 44 | lines are invalidated. Address is returned.\r |
45 | \r | |
46 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
47 | \r | |
48 | @param Address The base address of the instruction cache lines to\r | |
49 | invalidate. If the CPU is in a physical addressing mode, then\r | |
50 | Address is a physical address. If the CPU is in a virtual\r | |
51 | addressing mode, then Address is a virtual address.\r | |
52 | \r | |
53 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
54 | \r | |
eb1c78db | 55 | @return Address.\r |
e1f414b6 | 56 | \r |
57 | **/\r | |
58 | VOID *\r | |
59 | EFIAPI\r | |
60 | InvalidateInstructionCacheRange (\r | |
61 | IN VOID *Address,\r | |
62 | IN UINTN Length\r | |
63 | )\r | |
64 | {\r | |
351d6e7f LG |
65 | if (Length == 0) {\r |
66 | return Address;\r | |
67 | }\r | |
68 | \r | |
69 | ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));\r | |
e1f414b6 | 70 | return Address;\r |
71 | }\r | |
72 | \r | |
73 | /**\r | |
35a17154 | 74 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 75 | of the calling CPU.\r |
76 | \r | |
35a17154 | 77 | Writes back and invalidates the entire data cache in cache coherency domain\r |
e1f414b6 | 78 | of the calling CPU. This function guarantees that all dirty cache lines are\r |
79 | written back to system memory, and also invalidates all the data cache lines\r | |
80 | in the cache coherency domain of the calling CPU.\r | |
81 | \r | |
82 | **/\r | |
83 | VOID\r | |
84 | EFIAPI\r | |
85 | WriteBackInvalidateDataCache (\r | |
86 | VOID\r | |
87 | )\r | |
88 | {\r | |
89 | AsmWbinvd ();\r | |
90 | }\r | |
91 | \r | |
92 | /**\r | |
35a17154 | 93 | Writes back and invalidates a range of data cache lines in the cache\r |
e1f414b6 | 94 | coherency domain of the calling CPU.\r |
95 | \r | |
35a17154 | 96 | Writes back and invalidates the data cache lines specified by Address and\r |
e1f414b6 | 97 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
98 | cache line containing Address is written back and invalidated. If Address +\r | |
99 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
100 | line containing Address + Length -1 is written back and invalidated. This\r | |
101 | function may choose to write back and invalidate the entire data cache if\r | |
102 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 103 | range. If Length is 0, then no data cache lines are written back and\r |
e1f414b6 | 104 | invalidated. Address is returned.\r |
105 | \r | |
106 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
107 | \r | |
108 | @param Address The base address of the data cache lines to write back and\r | |
109 | invalidate. If the CPU is in a physical addressing mode, then\r | |
110 | Address is a physical address. If the CPU is in a virtual\r | |
111 | addressing mode, then Address is a virtual address.\r | |
112 | @param Length The number of bytes to write back and invalidate from the\r | |
113 | data cache.\r | |
114 | \r | |
38bbd3d9 | 115 | @return Address of cache invalidation.\r |
e1f414b6 | 116 | \r |
117 | **/\r | |
118 | VOID *\r | |
119 | EFIAPI\r | |
120 | WriteBackInvalidateDataCacheRange (\r | |
121 | IN VOID *Address,\r | |
122 | IN UINTN Length\r | |
123 | )\r | |
124 | {\r | |
d2660fe3 MK |
125 | UINT32 RegEbx;\r |
126 | UINT32 RegEdx;\r | |
127 | UINTN CacheLineSize;\r | |
ad400b07 | 128 | UINTN Start;\r |
129 | UINTN End;\r | |
e1f414b6 | 130 | \r |
e1f414b6 | 131 | if (Length == 0) {\r |
132 | return Address;\r | |
133 | }\r | |
134 | \r | |
351d6e7f LG |
135 | ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));\r |
136 | \r | |
d2660fe3 | 137 | //\r |
9095d37b | 138 | // If the CPU does not support CLFLUSH instruction,\r |
d2660fe3 MK |
139 | // then promote flush range to flush entire cache.\r |
140 | //\r | |
141 | AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);\r | |
142 | if ((RegEdx & BIT19) == 0) {\r | |
143 | AsmWbinvd ();\r | |
144 | return Address;\r | |
145 | }\r | |
146 | \r | |
147 | //\r | |
148 | // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H\r | |
149 | //\r | |
150 | CacheLineSize = (RegEbx & 0xff00) >> 5;\r | |
151 | \r | |
e1f414b6 | 152 | Start = (UINTN)Address;\r |
38bbd3d9 | 153 | //\r |
154 | // Calculate the cache line alignment\r | |
d2660fe3 MK |
155 | //\r |
156 | End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);\r | |
157 | Start &= ~((UINTN)CacheLineSize - 1);\r | |
e1f414b6 | 158 | \r |
159 | do {\r | |
d2660fe3 | 160 | Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;\r |
e1f414b6 | 161 | } while (Start != End);\r |
162 | return Address;\r | |
163 | }\r | |
164 | \r | |
165 | /**\r | |
35a17154 | 166 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 167 | CPU.\r |
168 | \r | |
35a17154 | 169 | Writes back the entire data cache in cache coherency domain of the calling\r |
e1f414b6 | 170 | CPU. This function guarantees that all dirty cache lines are written back to\r |
171 | system memory. This function may also invalidate all the data cache lines in\r | |
172 | the cache coherency domain of the calling CPU.\r | |
173 | \r | |
174 | **/\r | |
175 | VOID\r | |
176 | EFIAPI\r | |
177 | WriteBackDataCache (\r | |
178 | VOID\r | |
179 | )\r | |
180 | {\r | |
181 | WriteBackInvalidateDataCache ();\r | |
182 | }\r | |
183 | \r | |
184 | /**\r | |
35a17154 | 185 | Writes back a range of data cache lines in the cache coherency domain of the\r |
e1f414b6 | 186 | calling CPU.\r |
187 | \r | |
35a17154 | 188 | Writes back the data cache lines specified by Address and Length. If Address\r |
e1f414b6 | 189 | is not aligned on a cache line boundary, then entire data cache line\r |
190 | containing Address is written back. If Address + Length is not aligned on a\r | |
191 | cache line boundary, then the entire data cache line containing Address +\r | |
192 | Length -1 is written back. This function may choose to write back the entire\r | |
193 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 194 | If Length is 0, then no data cache lines are written back. This function may\r |
e1f414b6 | 195 | also invalidate all the data cache lines in the specified range of the cache\r |
196 | coherency domain of the calling CPU. Address is returned.\r | |
197 | \r | |
198 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
199 | \r | |
200 | @param Address The base address of the data cache lines to write back. If\r | |
201 | the CPU is in a physical addressing mode, then Address is a\r | |
202 | physical address. If the CPU is in a virtual addressing\r | |
203 | mode, then Address is a virtual address.\r | |
204 | @param Length The number of bytes to write back from the data cache.\r | |
205 | \r | |
ad400b07 | 206 | @return Address of cache written in main memory.\r |
e1f414b6 | 207 | \r |
208 | **/\r | |
209 | VOID *\r | |
210 | EFIAPI\r | |
211 | WriteBackDataCacheRange (\r | |
212 | IN VOID *Address,\r | |
213 | IN UINTN Length\r | |
214 | )\r | |
215 | {\r | |
216 | return WriteBackInvalidateDataCacheRange (Address, Length);\r | |
217 | }\r | |
218 | \r | |
219 | /**\r | |
220 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
221 | CPU.\r | |
222 | \r | |
223 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
224 | CPU. This function must be used with care because dirty cache lines are not\r | |
225 | written back to system memory. It is typically used for cache diagnostics. If\r | |
226 | the CPU does not support invalidation of the entire data cache, then a write\r | |
227 | back and invalidate operation should be performed on the entire data cache.\r | |
228 | \r | |
229 | **/\r | |
230 | VOID\r | |
231 | EFIAPI\r | |
232 | InvalidateDataCache (\r | |
233 | VOID\r | |
234 | )\r | |
235 | {\r | |
236 | AsmInvd ();\r | |
237 | }\r | |
238 | \r | |
239 | /**\r | |
240 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
241 | calling CPU.\r | |
242 | \r | |
243 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
244 | is not aligned on a cache line boundary, then entire data cache line\r | |
245 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
246 | cache line boundary, then the entire data cache line containing Address +\r | |
247 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 248 | outside the specified range. If Length is 0, then no data cache lines are\r |
e1f414b6 | 249 | invalidated. Address is returned. This function must be used with care\r |
250 | because dirty cache lines are not written back to system memory. It is\r | |
251 | typically used for cache diagnostics. If the CPU does not support\r | |
252 | invalidation of a data cache range, then a write back and invalidate\r | |
253 | operation should be performed on the data cache range.\r | |
254 | \r | |
255 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
256 | \r | |
257 | @param Address The base address of the data cache lines to invalidate. If\r | |
258 | the CPU is in a physical addressing mode, then Address is a\r | |
259 | physical address. If the CPU is in a virtual addressing mode,\r | |
260 | then Address is a virtual address.\r | |
261 | @param Length The number of bytes to invalidate from the data cache.\r | |
262 | \r | |
eb1c78db | 263 | @return Address.\r |
e1f414b6 | 264 | \r |
265 | **/\r | |
266 | VOID *\r | |
267 | EFIAPI\r | |
268 | InvalidateDataCacheRange (\r | |
269 | IN VOID *Address,\r | |
270 | IN UINTN Length\r | |
271 | )\r | |
272 | {\r | |
ad400b07 | 273 | //\r |
274 | // Invalidation of a data cache range without writing back is not supported on\r | |
275 | // x86 architecture, so write back and invalidate operation is performed.\r | |
276 | //\r | |
e1f414b6 | 277 | return WriteBackInvalidateDataCacheRange (Address, Length);\r |
278 | }\r |