]>
Commit | Line | Data |
---|---|---|
9f4f2f0e | 1 | /** @file\r |
2 | AsmEnableCache function\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | /**\r | |
16 | Enabled caches.\r | |
17 | \r | |
18 | Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear \r | |
19 | the NW bit of CR0 to 0\r | |
20 | \r | |
21 | **/\r | |
22 | VOID\r | |
23 | EFIAPI\r | |
24 | AsmEnableCache (\r | |
25 | VOID\r | |
26 | )\r | |
27 | {\r | |
28 | _asm {\r | |
29 | wbinvd\r | |
30 | mov eax, cr0\r | |
31 | btr eax, 30\r | |
32 | btr eax, 29\r | |
33 | mov cr0, eax\r | |
34 | }\r | |
35 | }\r | |
36 | \r |